1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "efuse.h"
7 #include "fw.h"
8 #include "mac.h"
9 #include "phy.h"
10 #include "reg.h"
11 #include "rtw8851b.h"
12 #include "rtw8851b_rfk.h"
13 #include "rtw8851b_rfk_table.h"
14 #include "rtw8851b_table.h"
15 #include "txrx.h"
16 #include "util.h"
17
18 #define RTW8851B_FW_FORMAT_MAX 0
19 #define RTW8851B_FW_BASENAME "rtw89/rtw8851b_fw"
20 #define RTW8851B_MODULE_FIRMWARE \
21 RTW8851B_FW_BASENAME ".bin"
22
23 static const struct rtw89_hfc_ch_cfg rtw8851b_hfc_chcfg_pcie[] = {
24 {5, 343, grp_0}, /* ACH 0 */
25 {5, 343, grp_0}, /* ACH 1 */
26 {5, 343, grp_0}, /* ACH 2 */
27 {5, 343, grp_0}, /* ACH 3 */
28 {0, 0, grp_0}, /* ACH 4 */
29 {0, 0, grp_0}, /* ACH 5 */
30 {0, 0, grp_0}, /* ACH 6 */
31 {0, 0, grp_0}, /* ACH 7 */
32 {4, 344, grp_0}, /* B0MGQ */
33 {4, 344, grp_0}, /* B0HIQ */
34 {0, 0, grp_0}, /* B1MGQ */
35 {0, 0, grp_0}, /* B1HIQ */
36 {40, 0, 0} /* FWCMDQ */
37 };
38
39 static const struct rtw89_hfc_pub_cfg rtw8851b_hfc_pubcfg_pcie = {
40 448, /* Group 0 */
41 0, /* Group 1 */
42 448, /* Public Max */
43 0 /* WP threshold */
44 };
45
46 static const struct rtw89_hfc_param_ini rtw8851b_hfc_param_ini_pcie[] = {
47 [RTW89_QTA_SCC] = {rtw8851b_hfc_chcfg_pcie, &rtw8851b_hfc_pubcfg_pcie,
48 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
49 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
50 RTW89_HCIFC_POH},
51 [RTW89_QTA_INVALID] = {NULL},
52 };
53
54 static const struct rtw89_dle_mem rtw8851b_dle_mem_pcie[] = {
55 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
56 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
57 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
58 &rtw89_mac_size.ple_qt58},
59 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size6,
60 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
61 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
62 &rtw89_mac_size.ple_qt_51b_wow},
63 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
64 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
65 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
66 &rtw89_mac_size.ple_qt13},
67 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
68 NULL},
69 };
70
71 static const struct rtw89_reg3_def rtw8851b_btc_preagc_en_defs[] = {
72 {0x46D0, GENMASK(1, 0), 0x3},
73 {0x4AD4, GENMASK(31, 0), 0xf},
74 {0x4688, GENMASK(23, 16), 0x80},
75 {0x4688, GENMASK(31, 24), 0x80},
76 {0x4694, GENMASK(7, 0), 0x80},
77 {0x4694, GENMASK(15, 8), 0x80},
78 {0x4AE4, GENMASK(11, 6), 0x34},
79 {0x4AE4, GENMASK(17, 12), 0x0},
80 {0x469C, GENMASK(31, 26), 0x34},
81 };
82
83 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_en_defs);
84
85 static const struct rtw89_reg3_def rtw8851b_btc_preagc_dis_defs[] = {
86 {0x46D0, GENMASK(1, 0), 0x0},
87 {0x4AD4, GENMASK(31, 0), 0x60},
88 {0x4688, GENMASK(23, 16), 0x10},
89 {0x4690, GENMASK(31, 24), 0x2a},
90 {0x4694, GENMASK(15, 8), 0x2a},
91 {0x4AE4, GENMASK(11, 6), 0x26},
92 {0x4AE4, GENMASK(17, 12), 0x1e},
93 {0x469C, GENMASK(31, 26), 0x26},
94 };
95
96 static DECLARE_PHY_REG3_TBL(rtw8851b_btc_preagc_dis_defs);
97
98 static const u32 rtw8851b_h2c_regs[RTW89_H2CREG_MAX] = {
99 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
100 R_AX_H2CREG_DATA3
101 };
102
103 static const u32 rtw8851b_c2h_regs[RTW89_C2HREG_MAX] = {
104 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
105 R_AX_C2HREG_DATA3
106 };
107
108 static const struct rtw89_page_regs rtw8851b_page_regs = {
109 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
110 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
111 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
112 .ach_page_info = R_AX_ACH0_PAGE_INFO,
113 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
114 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
115 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
116 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
117 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
118 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
119 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
120 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
121 };
122
123 static const struct rtw89_reg_def rtw8851b_dcfo_comp = {
124 R_DCFO_COMP_S0_V2, B_DCFO_COMP_S0_MSK_V2
125 };
126
127 static const struct rtw89_imr_info rtw8851b_imr_info = {
128 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
129 .wsec_imr_reg = R_AX_SEC_DEBUG,
130 .wsec_imr_set = B_AX_IMR_ERROR,
131 .mpdu_tx_imr_set = 0,
132 .mpdu_rx_imr_set = 0,
133 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
134 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
135 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
136 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
137 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
138 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
139 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
140 .wde_imr_clr = B_AX_WDE_IMR_CLR,
141 .wde_imr_set = B_AX_WDE_IMR_SET,
142 .ple_imr_clr = B_AX_PLE_IMR_CLR,
143 .ple_imr_set = B_AX_PLE_IMR_SET,
144 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
145 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
146 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
147 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
148 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
149 .other_disp_imr_set = 0,
150 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
151 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
152 .bbrpt_err_imr_set = 0,
153 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
154 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
155 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
156 .cdma_imr_0_reg = R_AX_DLE_CTRL,
157 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
158 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
159 .cdma_imr_1_reg = 0,
160 .cdma_imr_1_clr = 0,
161 .cdma_imr_1_set = 0,
162 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
163 .phy_intf_imr_clr = 0,
164 .phy_intf_imr_set = 0,
165 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
166 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
167 .rmac_imr_set = B_AX_RMAC_IMR_SET,
168 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
169 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
170 .tmac_imr_set = B_AX_TMAC_IMR_SET,
171 };
172
173 static const struct rtw89_xtal_info rtw8851b_xtal_info = {
174 .xcap_reg = R_AX_XTAL_ON_CTRL3,
175 .sc_xo_mask = B_AX_XTAL_SC_XO_A_BLOCK_MASK,
176 .sc_xi_mask = B_AX_XTAL_SC_XI_A_BLOCK_MASK,
177 };
178
179 static const struct rtw89_rrsr_cfgs rtw8851b_rrsr_cfgs = {
180 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
181 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
182 };
183
184 static const struct rtw89_dig_regs rtw8851b_dig_regs = {
185 .seg0_pd_reg = R_SEG0R_PD_V1,
186 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
187 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
188 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
189 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
190 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
191 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
192 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
193 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
194 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
195 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
196 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
197 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
198 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
199 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
200 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
201 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
202 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
203 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
204 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
205 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
206 };
207
208 static const struct rtw89_edcca_regs rtw8851b_edcca_regs = {
209 .edcca_level = R_SEG0R_EDCCA_LVL_V1,
210 .edcca_mask = B_EDCCA_LVL_MSK0,
211 .edcca_p_mask = B_EDCCA_LVL_MSK1,
212 .ppdu_level = R_SEG0R_EDCCA_LVL_V1,
213 .ppdu_mask = B_EDCCA_LVL_MSK3,
214 .rpt_a = R_EDCCA_RPT_A,
215 .rpt_b = R_EDCCA_RPT_B,
216 .rpt_sel = R_EDCCA_RPT_SEL,
217 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
218 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
219 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
220 };
221
222 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
223 {255, 0, 0, 7}, /* 0 -> original */
224 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
225 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
226 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
227 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
228 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
229 {6, 1, 0, 7},
230 {13, 1, 0, 7},
231 {13, 1, 0, 7}
232 };
233
234 static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_dl[] = {
235 {255, 0, 0, 7}, /* 0 -> original */
236 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
237 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
238 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
239 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
240 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
241 {255, 1, 0, 7},
242 {255, 1, 0, 7},
243 {255, 1, 0, 7}
244 };
245
246 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8851b_mon_reg[] = {
247 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
248 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
249 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
250 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
251 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
252 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
253 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
254 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
255 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
256 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
257 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
258 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
259 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
260 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
261 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
262 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
263 };
264
265 static const u8 rtw89_btc_8851b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
266 static const u8 rtw89_btc_8851b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
267
rtw8851b_pwr_on_func(struct rtw89_dev * rtwdev)268 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
269 {
270 u32 val32;
271 u8 val8;
272 u32 ret;
273
274 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
275 B_AX_AFSM_PCIE_SUS_EN);
276 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
277 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
278 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
279 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
280
281 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
282 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
283 if (ret)
284 return ret;
285
286 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
287 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
288
289 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
290 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
291 if (ret)
292 return ret;
293
294 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
295 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
296 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
297 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
298
299 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
300 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
301
302 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
303 XTAL_SI_OFF_WEI);
304 if (ret)
305 return ret;
306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
307 XTAL_SI_OFF_EI);
308 if (ret)
309 return ret;
310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
311 if (ret)
312 return ret;
313 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
314 XTAL_SI_PON_WEI);
315 if (ret)
316 return ret;
317 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
318 XTAL_SI_PON_EI);
319 if (ret)
320 return ret;
321 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
322 if (ret)
323 return ret;
324 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
325 if (ret)
326 return ret;
327 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
328 if (ret)
329 return ret;
330 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
331 if (ret)
332 return ret;
333 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
334 if (ret)
335 return ret;
336
337 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
338 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
339 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
340
341 fsleep(1000);
342
343 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
344 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
345 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
346 B_AX_GPIO10_PULL_LOW_EN | B_AX_GPIO16_PULL_LOW_EN_V1);
347
348 if (rtwdev->hal.cv == CHIP_CAV) {
349 ret = rtw89_read_efuse_ver(rtwdev, &val8);
350 if (!ret)
351 rtwdev->hal.cv = val8;
352 }
353
354 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
355 B_AX_XTAL_SI_ADDR_NOT_CHK);
356 if (rtwdev->hal.cv != CHIP_CAV) {
357 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
358 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
359 }
360
361 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
362 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
363 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
364 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
365 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
366 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
367 B_AX_DMACREG_GCKEN);
368 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
369 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
370 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
371 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
372 B_AX_RMAC_EN);
373
374 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
375 PINMUX_EESK_FUNC_SEL_BT_LOG);
376
377 return 0;
378 }
379
rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev * rtwdev)380 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
381 {
382 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
383 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
384 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
385 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
386 }
387
rtw8851b_pwr_off_func(struct rtw89_dev * rtwdev)388 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
389 {
390 u32 val32;
391 u32 ret;
392
393 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
394 XTAL_SI_RFC2RF);
395 if (ret)
396 return ret;
397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
398 if (ret)
399 return ret;
400 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
401 if (ret)
402 return ret;
403 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
404 if (ret)
405 return ret;
406 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
407 XTAL_SI_SRAM2RFC);
408 if (ret)
409 return ret;
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
411 if (ret)
412 return ret;
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
414 if (ret)
415 return ret;
416
417 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
418 B_AX_XTAL_SI_ADDR_NOT_CHK);
419 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
420 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
421 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
422
423 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
424
425 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
426 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
427 if (ret)
428 return ret;
429
430 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
431
432 if (rtwdev->hal.cv == CHIP_CAV) {
433 rtw8851b_patch_swr_pfm2pwm(rtwdev);
434 } else {
435 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
436 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
437 }
438
439 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
440
441 return 0;
442 }
443
rtw8851b_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8851b_efuse * map)444 static void rtw8851b_efuse_parsing(struct rtw89_efuse *efuse,
445 struct rtw8851b_efuse *map)
446 {
447 ether_addr_copy(efuse->addr, map->e.mac_addr);
448 efuse->rfe_type = map->rfe_type;
449 efuse->xtal_cap = map->xtal_k;
450 }
451
rtw8851b_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)452 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
453 struct rtw8851b_efuse *map)
454 {
455 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
456 struct rtw8851b_tssi_offset *ofst[] = {&map->path_a_tssi};
457 u8 i, j;
458
459 tssi->thermal[RF_PATH_A] = map->path_a_therm;
460
461 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
462 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
463 sizeof(ofst[i]->cck_tssi));
464
465 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
466 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
467 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
468 i, j, tssi->tssi_cck[i][j]);
469
470 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
471 sizeof(ofst[i]->bw40_tssi));
472 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
473 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
474
475 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
476 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
477 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
478 i, j, tssi->tssi_mcs[i][j]);
479 }
480 }
481
_decode_efuse_gain(u8 data,s8 * high,s8 * low)482 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
483 {
484 if (high)
485 *high = sign_extend32(u8_get_bits(data, GENMASK(7, 4)), 3);
486 if (low)
487 *low = sign_extend32(u8_get_bits(data, GENMASK(3, 0)), 3);
488
489 return data != 0xff;
490 }
491
rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8851b_efuse * map)492 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
493 struct rtw8851b_efuse *map)
494 {
495 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
496 bool valid = false;
497
498 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
499 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
500 NULL);
501 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
502 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
503 NULL);
504 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
505 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
506 NULL);
507 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
508 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
509 NULL);
510 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
511 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
512 NULL);
513
514 gain->offset_valid = valid;
515 }
516
rtw8851b_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)517 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
518 enum rtw89_efuse_block block)
519 {
520 struct rtw89_efuse *efuse = &rtwdev->efuse;
521 struct rtw8851b_efuse *map;
522
523 map = (struct rtw8851b_efuse *)log_map;
524
525 efuse->country_code[0] = map->country_code[0];
526 efuse->country_code[1] = map->country_code[1];
527 rtw8851b_efuse_parsing_tssi(rtwdev, map);
528 rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
529
530 switch (rtwdev->hci.type) {
531 case RTW89_HCI_TYPE_PCIE:
532 rtw8851b_efuse_parsing(efuse, map);
533 break;
534 default:
535 return -EOPNOTSUPP;
536 }
537
538 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
539
540 return 0;
541 }
542
rtw8851b_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)543 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
544 {
545 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
546 static const u32 tssi_trim_addr[RF_PATH_NUM_8851B] = {0x5D6};
547 u32 addr = rtwdev->chip->phycap_addr;
548 bool pg = false;
549 u32 ofst;
550 u8 i, j;
551
552 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
553 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
554 /* addrs are in decreasing order */
555 ofst = tssi_trim_addr[i] - addr - j;
556 tssi->tssi_trim[i][j] = phycap_map[ofst];
557
558 if (phycap_map[ofst] != 0xff)
559 pg = true;
560 }
561 }
562
563 if (!pg) {
564 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
565 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
566 "[TSSI][TRIM] no PG, set all trim info to 0\n");
567 }
568
569 for (i = 0; i < RF_PATH_NUM_8851B; i++)
570 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
571 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
572 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
573 i, j, tssi->tssi_trim[i][j],
574 tssi_trim_addr[i] - j);
575 }
576
rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)577 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
578 u8 *phycap_map)
579 {
580 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
581 static const u32 thm_trim_addr[RF_PATH_NUM_8851B] = {0x5DF};
582 u32 addr = rtwdev->chip->phycap_addr;
583 u8 i;
584
585 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
586 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
587
588 rtw89_debug(rtwdev, RTW89_DBG_RFK,
589 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
590 i, info->thermal_trim[i]);
591
592 if (info->thermal_trim[i] != 0xff)
593 info->pg_thermal_trim = true;
594 }
595 }
596
rtw8851b_thermal_trim(struct rtw89_dev * rtwdev)597 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
598 {
599 #define __thm_setting(raw) \
600 ({ \
601 u8 __v = (raw); \
602 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
603 })
604 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
605 u8 i, val;
606
607 if (!info->pg_thermal_trim) {
608 rtw89_debug(rtwdev, RTW89_DBG_RFK,
609 "[THERMAL][TRIM] no PG, do nothing\n");
610
611 return;
612 }
613
614 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
615 val = __thm_setting(info->thermal_trim[i]);
616 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
617
618 rtw89_debug(rtwdev, RTW89_DBG_RFK,
619 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
620 i, val);
621 }
622 #undef __thm_setting
623 }
624
rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)625 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
626 u8 *phycap_map)
627 {
628 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
629 static const u32 pabias_trim_addr[] = {0x5DE};
630 u32 addr = rtwdev->chip->phycap_addr;
631 u8 i;
632
633 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
634 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
635
636 rtw89_debug(rtwdev, RTW89_DBG_RFK,
637 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
638 i, info->pa_bias_trim[i]);
639
640 if (info->pa_bias_trim[i] != 0xff)
641 info->pg_pa_bias_trim = true;
642 }
643 }
644
rtw8851b_pa_bias_trim(struct rtw89_dev * rtwdev)645 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
646 {
647 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
648 u8 pabias_2g, pabias_5g;
649 u8 i;
650
651 if (!info->pg_pa_bias_trim) {
652 rtw89_debug(rtwdev, RTW89_DBG_RFK,
653 "[PA_BIAS][TRIM] no PG, do nothing\n");
654
655 return;
656 }
657
658 for (i = 0; i < RF_PATH_NUM_8851B; i++) {
659 pabias_2g = u8_get_bits(info->pa_bias_trim[i], GENMASK(3, 0));
660 pabias_5g = u8_get_bits(info->pa_bias_trim[i], GENMASK(7, 4));
661
662 rtw89_debug(rtwdev, RTW89_DBG_RFK,
663 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
664 i, pabias_2g, pabias_5g);
665
666 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
667 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
668 }
669 }
670
rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev * rtwdev,u8 * phycap_map)671 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
672 {
673 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
674 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
675 };
676 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
677 u32 phycap_addr = rtwdev->chip->phycap_addr;
678 bool valid = false;
679 int path, i;
680 u8 data;
681
682 for (path = 0; path < BB_PATH_NUM_8851B; path++)
683 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
684 if (comp_addrs[path][i] == 0)
685 continue;
686
687 data = phycap_map[comp_addrs[path][i] - phycap_addr];
688 valid |= _decode_efuse_gain(data, NULL,
689 &gain->comp[path][i]);
690 }
691
692 gain->comp_valid = valid;
693 }
694
rtw8851b_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)695 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
696 {
697 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
698 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
699 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
700 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
701
702 return 0;
703 }
704
rtw8851b_set_bb_gpio(struct rtw89_dev * rtwdev,u8 gpio_idx,bool inv,u8 src_sel)705 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
706 u8 src_sel)
707 {
708 u32 addr, mask;
709
710 if (gpio_idx >= 32)
711 return;
712
713 /* 2 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 2 bits */
714 addr = R_RFE_SEL0_A2 + (gpio_idx / 16) * sizeof(u32);
715 mask = B_RFE_SEL0_MASK << (gpio_idx % 16) * 2;
716
717 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
718 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
719
720 /* 4 continual 32-bit registers for 32 GPIOs, and each GPIO occupies 4 bits */
721 addr = R_RFE_SEL0_BASE + (gpio_idx / 8) * sizeof(u32);
722 mask = B_RFE_SEL0_SRC_MASK << (gpio_idx % 8) * 4;
723
724 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
725 }
726
rtw8851b_set_mac_gpio(struct rtw89_dev * rtwdev,u8 func)727 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
728 {
729 static const struct rtw89_reg3_def func16 = {
730 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO16_FUNC_SEL_MASK, BIT(3)
731 };
732 static const struct rtw89_reg3_def func17 = {
733 R_AX_GPIO16_23_FUNC_SEL, B_AX_PINMUX_GPIO17_FUNC_SEL_MASK, BIT(7) >> 4,
734 };
735 const struct rtw89_reg3_def *def;
736
737 switch (func) {
738 case 16:
739 def = &func16;
740 break;
741 case 17:
742 def = &func17;
743 break;
744 default:
745 rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
746 return;
747 }
748
749 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
750 }
751
rtw8851b_rfe_gpio(struct rtw89_dev * rtwdev)752 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
753 {
754 u8 rfe_type = rtwdev->efuse.rfe_type;
755
756 if (rfe_type > 50)
757 return;
758
759 if (rfe_type % 3 == 2) {
760 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
761 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
762
763 rtw8851b_set_mac_gpio(rtwdev, 16);
764 rtw8851b_set_mac_gpio(rtwdev, 17);
765 }
766 }
767
rtw8851b_power_trim(struct rtw89_dev * rtwdev)768 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
769 {
770 rtw8851b_thermal_trim(rtwdev);
771 rtw8851b_pa_bias_trim(rtwdev);
772 }
773
rtw8851b_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)774 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
775 const struct rtw89_chan *chan,
776 u8 mac_idx)
777 {
778 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
779 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
780 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
781 u8 txsc20 = 0, txsc40 = 0;
782
783 switch (chan->band_width) {
784 case RTW89_CHANNEL_WIDTH_80:
785 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
786 fallthrough;
787 case RTW89_CHANNEL_WIDTH_40:
788 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
789 break;
790 default:
791 break;
792 }
793
794 switch (chan->band_width) {
795 case RTW89_CHANNEL_WIDTH_80:
796 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
797 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
798 break;
799 case RTW89_CHANNEL_WIDTH_40:
800 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
801 rtw89_write32(rtwdev, sub_carr, txsc20);
802 break;
803 case RTW89_CHANNEL_WIDTH_20:
804 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
805 rtw89_write32(rtwdev, sub_carr, 0);
806 break;
807 default:
808 break;
809 }
810
811 if (chan->channel > 14) {
812 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
813 rtw89_write8_set(rtwdev, chk_rate,
814 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
815 } else {
816 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
817 rtw89_write8_clr(rtwdev, chk_rate,
818 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
819 }
820 }
821
822 static const u32 rtw8851b_sco_barker_threshold[14] = {
823 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
824 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
825 };
826
827 static const u32 rtw8851b_sco_cck_threshold[14] = {
828 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
829 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
830 };
831
rtw8851b_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch)832 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
833 {
834 u8 ch_element = primary_ch - 1;
835
836 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
837 rtw8851b_sco_barker_threshold[ch_element]);
838 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
839 rtw8851b_sco_cck_threshold[ch_element]);
840 }
841
rtw8851b_sco_mapping(u8 central_ch)842 static u8 rtw8851b_sco_mapping(u8 central_ch)
843 {
844 if (central_ch == 1)
845 return 109;
846 else if (central_ch >= 2 && central_ch <= 6)
847 return 108;
848 else if (central_ch >= 7 && central_ch <= 10)
849 return 107;
850 else if (central_ch >= 11 && central_ch <= 14)
851 return 106;
852 else if (central_ch == 36 || central_ch == 38)
853 return 51;
854 else if (central_ch >= 40 && central_ch <= 58)
855 return 50;
856 else if (central_ch >= 60 && central_ch <= 64)
857 return 49;
858 else if (central_ch == 100 || central_ch == 102)
859 return 48;
860 else if (central_ch >= 104 && central_ch <= 126)
861 return 47;
862 else if (central_ch >= 128 && central_ch <= 151)
863 return 46;
864 else if (central_ch >= 153 && central_ch <= 177)
865 return 45;
866 else
867 return 0;
868 }
869
870 struct rtw8851b_bb_gain {
871 u32 gain_g[BB_PATH_NUM_8851B];
872 u32 gain_a[BB_PATH_NUM_8851B];
873 u32 gain_mask;
874 };
875
876 static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
877 { .gain_g = {0x4678}, .gain_a = {0x45DC},
878 .gain_mask = 0x00ff0000 },
879 { .gain_g = {0x4678}, .gain_a = {0x45DC},
880 .gain_mask = 0xff000000 },
881 { .gain_g = {0x467C}, .gain_a = {0x4660},
882 .gain_mask = 0x000000ff },
883 { .gain_g = {0x467C}, .gain_a = {0x4660},
884 .gain_mask = 0x0000ff00 },
885 { .gain_g = {0x467C}, .gain_a = {0x4660},
886 .gain_mask = 0x00ff0000 },
887 { .gain_g = {0x467C}, .gain_a = {0x4660},
888 .gain_mask = 0xff000000 },
889 { .gain_g = {0x4680}, .gain_a = {0x4664},
890 .gain_mask = 0x000000ff },
891 };
892
893 static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
894 { .gain_g = {0x4680}, .gain_a = {0x4664},
895 .gain_mask = 0x00ff0000 },
896 { .gain_g = {0x4680}, .gain_a = {0x4664},
897 .gain_mask = 0xff000000 },
898 };
899
rtw8851b_set_gain_error(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_rf_path path)900 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
901 enum rtw89_subband subband,
902 enum rtw89_rf_path path)
903 {
904 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
905 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
906 s32 val;
907 u32 reg;
908 u32 mask;
909 int i;
910
911 for (i = 0; i < LNA_GAIN_NUM; i++) {
912 if (subband == RTW89_CH_2G)
913 reg = bb_gain_lna[i].gain_g[path];
914 else
915 reg = bb_gain_lna[i].gain_a[path];
916
917 mask = bb_gain_lna[i].gain_mask;
918 val = gain->lna_gain[gain_band][path][i];
919 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
920 }
921
922 for (i = 0; i < TIA_GAIN_NUM; i++) {
923 if (subband == RTW89_CH_2G)
924 reg = bb_gain_tia[i].gain_g[path];
925 else
926 reg = bb_gain_tia[i].gain_a[path];
927
928 mask = bb_gain_tia[i].gain_mask;
929 val = gain->tia_gain[gain_band][path][i];
930 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
931 }
932 }
933
rtw8851b_set_gain_offset(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_phy_idx phy_idx)934 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
935 enum rtw89_subband subband,
936 enum rtw89_phy_idx phy_idx)
937 {
938 static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1};
939 static const u32 gain_err_addr[] = {R_P0_AGC_RSVD};
940 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
941 enum rtw89_gain_offset gain_ofdm_band;
942 s32 offset_ofdm, offset_cck;
943 s32 offset_a;
944 s32 tmp;
945 u8 path;
946
947 if (!efuse_gain->comp_valid)
948 goto next;
949
950 for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) {
951 tmp = efuse_gain->comp[path][subband];
952 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
953 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
954 }
955
956 next:
957 if (!efuse_gain->offset_valid)
958 return;
959
960 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
961
962 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
963
964 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
965 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
966 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
967
968 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
969 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
970
971 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
972 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
973 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
974
975 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
976 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
977 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
978
979 if (subband == RTW89_CH_2G) {
980 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
981 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
982 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
983 B_RX_RPL_OFST_CCK_MASK, tmp);
984 }
985 }
986
987 static
rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev * rtwdev,enum rtw89_subband subband)988 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
989 {
990 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
991 u8 band = rtw89_subband_to_bb_gain_band(subband);
992 u32 val;
993
994 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
995 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
996 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
997 val >>= B_P0_RPL1_SHIFT;
998 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
999 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
1000
1001 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
1002 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
1003 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
1004 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
1005 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
1006 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
1007
1008 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
1009 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
1010 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
1011 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
1012 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
1013 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
1014 }
1015
rtw8851b_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1016 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
1017 const struct rtw89_chan *chan,
1018 enum rtw89_phy_idx phy_idx)
1019 {
1020 u8 subband = chan->subband_type;
1021 u8 central_ch = chan->channel;
1022 bool is_2g = central_ch <= 14;
1023 u8 sco_comp;
1024
1025 if (is_2g)
1026 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1027 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
1028 else
1029 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1030 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
1031 /* SCO compensate FC setting */
1032 sco_comp = rtw8851b_sco_mapping(central_ch);
1033 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1034
1035 if (chan->band_type == RTW89_BAND_6G)
1036 return;
1037
1038 /* CCK parameters */
1039 if (central_ch == 14) {
1040 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1041 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1042 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1043 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1044 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1045 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1046 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1047 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1048 } else {
1049 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1050 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1051 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1052 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1053 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1054 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1055 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1056 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1057 }
1058
1059 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1060 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1061 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1062 }
1063
rtw8851b_bw_setting(struct rtw89_dev * rtwdev,u8 bw)1064 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1065 {
1066 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1067 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1068 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1069 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1070 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1071 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1072 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1073
1074 switch (bw) {
1075 case RTW89_CHANNEL_WIDTH_5:
1076 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1077 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1078 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1079 break;
1080 case RTW89_CHANNEL_WIDTH_10:
1081 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1082 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1083 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1084 break;
1085 case RTW89_CHANNEL_WIDTH_20:
1086 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1087 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1088 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1089 break;
1090 case RTW89_CHANNEL_WIDTH_40:
1091 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1092 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1093 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1094 break;
1095 case RTW89_CHANNEL_WIDTH_80:
1096 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1097 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1098 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1099 break;
1100 default:
1101 rtw89_warn(rtwdev, "Fail to set ADC\n");
1102 }
1103 }
1104
rtw8851b_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)1105 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1106 enum rtw89_phy_idx phy_idx)
1107 {
1108 switch (bw) {
1109 case RTW89_CHANNEL_WIDTH_5:
1110 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1111 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1112 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1113 break;
1114 case RTW89_CHANNEL_WIDTH_10:
1115 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1116 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1117 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1118 break;
1119 case RTW89_CHANNEL_WIDTH_20:
1120 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1121 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1122 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1123 break;
1124 case RTW89_CHANNEL_WIDTH_40:
1125 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1126 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1127 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1128 pri_ch, phy_idx);
1129 /* CCK primary channel */
1130 if (pri_ch == RTW89_SC_20_UPPER)
1131 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1132 else
1133 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1134
1135 break;
1136 case RTW89_CHANNEL_WIDTH_80:
1137 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1138 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1139 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1140 pri_ch, phy_idx);
1141 break;
1142 default:
1143 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1144 pri_ch);
1145 }
1146
1147 rtw8851b_bw_setting(rtwdev, bw);
1148 }
1149
rtw8851b_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en)1150 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1151 {
1152 if (cck_en) {
1153 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1154 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1155 B_PD_ARBITER_OFF, 0);
1156 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1157 } else {
1158 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1159 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1160 B_PD_ARBITER_OFF, 1);
1161 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1162 }
1163 }
1164
rtw8851b_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1165 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1166 const struct rtw89_chan *chan)
1167 {
1168 u8 center_chan = chan->channel;
1169
1170 switch (chan->band_type) {
1171 case RTW89_BAND_5G:
1172 if (center_chan == 151 || center_chan == 153 ||
1173 center_chan == 155 || center_chan == 163)
1174 return 5760;
1175 else if (center_chan == 54 || center_chan == 58)
1176 return 5280;
1177 break;
1178 default:
1179 break;
1180 }
1181
1182 return 0;
1183 }
1184
1185 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1186 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1187 #define MAX_TONE_NUM 2048
1188
rtw8851b_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1189 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1190 const struct rtw89_chan *chan,
1191 enum rtw89_phy_idx phy_idx)
1192 {
1193 u32 spur_freq;
1194 s32 freq_diff, csi_idx, csi_tone_idx;
1195
1196 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1197 if (spur_freq == 0) {
1198 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1199 0, phy_idx);
1200 return;
1201 }
1202
1203 freq_diff = (spur_freq - chan->freq) * 1000000;
1204 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1205 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1206
1207 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1208 csi_tone_idx, phy_idx);
1209 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1210 }
1211
1212 static const struct rtw89_nbi_reg_def rtw8851b_nbi_reg_def = {
1213 .notch1_idx = {0x46E4, 0xFF},
1214 .notch1_frac_idx = {0x46E4, 0xC00},
1215 .notch1_en = {0x46E4, 0x1000},
1216 .notch2_idx = {0x47A4, 0xFF},
1217 .notch2_frac_idx = {0x47A4, 0xC00},
1218 .notch2_en = {0x47A4, 0x1000},
1219 };
1220
rtw8851b_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1221 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1222 const struct rtw89_chan *chan)
1223 {
1224 const struct rtw89_nbi_reg_def *nbi = &rtw8851b_nbi_reg_def;
1225 s32 nbi_frac_idx, nbi_frac_tone_idx;
1226 s32 nbi_idx, nbi_tone_idx;
1227 bool notch2_chk = false;
1228 u32 spur_freq, fc;
1229 s32 freq_diff;
1230
1231 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1232 if (spur_freq == 0) {
1233 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1234 nbi->notch1_en.mask, 0);
1235 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1236 nbi->notch2_en.mask, 0);
1237 return;
1238 }
1239
1240 fc = chan->freq;
1241 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1242 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1243 if ((fc > spur_freq &&
1244 chan->channel < chan->primary_channel) ||
1245 (fc < spur_freq &&
1246 chan->channel > chan->primary_channel))
1247 notch2_chk = true;
1248 }
1249
1250 freq_diff = (spur_freq - fc) * 1000000;
1251 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1252 &nbi_frac_idx);
1253
1254 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1255 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1256 } else {
1257 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1258 128 : 256;
1259
1260 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1261 }
1262 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx,
1263 CARRIER_SPACING_78_125);
1264
1265 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1266 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1267 nbi->notch2_idx.mask, nbi_tone_idx);
1268 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1269 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1270 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1271 nbi->notch2_en.mask, 0);
1272 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1273 nbi->notch2_en.mask, 1);
1274 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1275 nbi->notch1_en.mask, 0);
1276 } else {
1277 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1278 nbi->notch1_idx.mask, nbi_tone_idx);
1279 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1280 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1281 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1282 nbi->notch1_en.mask, 0);
1283 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1284 nbi->notch1_en.mask, 1);
1285 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1286 nbi->notch2_en.mask, 0);
1287 }
1288 }
1289
rtw8851b_set_cfr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1290 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1291 {
1292 if (chan->band_type == RTW89_BAND_2G &&
1293 chan->band_width == RTW89_CHANNEL_WIDTH_20 &&
1294 (chan->channel == 1 || chan->channel == 13)) {
1295 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1296 B_PATH0_TX_CFR_LGC0, 0xf8);
1297 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1298 B_PATH0_TX_CFR_LGC1, 0x120);
1299 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1300 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x0);
1301 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1302 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x3);
1303 } else {
1304 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1305 B_PATH0_TX_CFR_LGC0, 0x120);
1306 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1307 B_PATH0_TX_CFR_LGC1, 0x3ff);
1308 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1309 B_PATH0_TX_POLAR_CLIPPING_LGC0, 0x3);
1310 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1311 B_PATH0_TX_POLAR_CLIPPING_LGC1, 0x7);
1312 }
1313 }
1314
rtw8851b_5m_mask(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1315 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1316 enum rtw89_phy_idx phy_idx)
1317 {
1318 u8 pri_ch = chan->pri_ch_idx;
1319 bool mask_5m_low;
1320 bool mask_5m_en;
1321
1322 switch (chan->band_width) {
1323 case RTW89_CHANNEL_WIDTH_40:
1324 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1325 mask_5m_en = true;
1326 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1327 break;
1328 case RTW89_CHANNEL_WIDTH_80:
1329 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1330 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1331 pri_ch == RTW89_SC_20_LOWEST;
1332 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1333 break;
1334 default:
1335 mask_5m_en = false;
1336 break;
1337 }
1338
1339 if (!mask_5m_en) {
1340 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1341 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1342 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1343 return;
1344 }
1345
1346 if (mask_5m_low) {
1347 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1348 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1349 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1350 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1351 } else {
1352 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1353 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1354 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1355 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1356 }
1357 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1358 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1359 }
1360
rtw8851b_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1361 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1362 {
1363 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1364 fsleep(1);
1365 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1366 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1367 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1368 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1369 }
1370
rtw8851b_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)1371 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1372 enum rtw89_phy_idx phy_idx, bool en)
1373 {
1374 if (en) {
1375 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1376 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1377 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1378 if (band == RTW89_BAND_2G)
1379 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1380 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1381 } else {
1382 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1383 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1384 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1385 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1386 fsleep(1);
1387 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1388 }
1389 }
1390
rtw8851b_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1391 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1392 enum rtw89_phy_idx phy_idx)
1393 {
1394 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1395 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);
1396 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1397 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1398 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1399 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);
1400 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1401 }
1402
1403 static
rtw8851b_bb_gpio_trsw(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 tx_path_en,u8 trsw_tx,u8 trsw_rx,u8 trsw_a,u8 trsw_b)1404 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1405 u8 tx_path_en, u8 trsw_tx,
1406 u8 trsw_rx, u8 trsw_a, u8 trsw_b)
1407 {
1408 u32 mask_ofst = 16;
1409 u32 val;
1410
1411 if (path != RF_PATH_A)
1412 return;
1413
1414 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1415 val = u32_encode_bits(trsw_a, B_P0_TRSW_A) |
1416 u32_encode_bits(trsw_b, B_P0_TRSW_B);
1417
1418 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1419 (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1420 }
1421
rtw8851b_bb_gpio_init(struct rtw89_dev * rtwdev)1422 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1423 {
1424 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1425 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1426 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1427 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1428 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1429
1430 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1431 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1432 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1433 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1434
1435 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1436 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1437 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1438 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1439 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1440 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1441 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1442 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1443 }
1444
rtw8851b_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1445 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1446 enum rtw89_phy_idx phy_idx)
1447 {
1448 u32 addr;
1449
1450 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1451 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1452 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1453 }
1454
rtw8851b_bb_sethw(struct rtw89_dev * rtwdev)1455 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1456 {
1457 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1458
1459 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1460
1461 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1462 rtw8851b_bb_gpio_init(rtwdev);
1463
1464 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1465 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1466
1467 /* read these registers after loading BB parameters */
1468 gain->offset_base[RTW89_PHY_0] =
1469 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1470 gain->rssi_base[RTW89_PHY_0] =
1471 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1472 }
1473
rtw8851b_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1474 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1475 enum rtw89_phy_idx phy_idx)
1476 {
1477 u8 band = chan->band_type, chan_idx;
1478 bool cck_en = chan->channel <= 14;
1479 u8 pri_ch_idx = chan->pri_ch_idx;
1480
1481 if (cck_en)
1482 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1483
1484 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1485 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1486 rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1487 rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1488 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1489
1490 if (chan->band_type == RTW89_BAND_5G) {
1491 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1492 B_PATH0_BT_SHARE_V1, 0x0);
1493 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1494 B_PATH0_BTG_PATH_V1, 0x0);
1495 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1496 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1497 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1498 B_BT_DYN_DC_EST_EN_MSK, 0x0);
1499 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1500 }
1501
1502 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1503 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1504 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1505 rtw8851b_set_cfr(rtwdev, chan);
1506 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1507 }
1508
rtw8851b_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1509 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1510 const struct rtw89_chan *chan,
1511 enum rtw89_mac_idx mac_idx,
1512 enum rtw89_phy_idx phy_idx)
1513 {
1514 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1515 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1516 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1517 }
1518
rtw8851b_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1519 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1520 enum rtw89_rf_path path)
1521 {
1522 if (en) {
1523 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1524 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1525 } else {
1526 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1527 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1528 }
1529 }
1530
rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1531 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1532 u8 phy_idx)
1533 {
1534 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1535 }
1536
rtw8851b_adc_en(struct rtw89_dev * rtwdev,bool en)1537 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1538 {
1539 if (en)
1540 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1541 else
1542 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1543 }
1544
rtw8851b_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1545 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1546 struct rtw89_channel_help_params *p,
1547 const struct rtw89_chan *chan,
1548 enum rtw89_mac_idx mac_idx,
1549 enum rtw89_phy_idx phy_idx)
1550 {
1551 if (enter) {
1552 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1553 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1554 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1555 rtw8851b_adc_en(rtwdev, false);
1556 fsleep(40);
1557 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1558 } else {
1559 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1560 rtw8851b_adc_en(rtwdev, true);
1561 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1562 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1563 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1564 }
1565 }
1566
rtw8851b_rfk_init(struct rtw89_dev * rtwdev)1567 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1568 {
1569 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1570 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1571 rtw8851b_lck_init(rtwdev);
1572
1573 rtw8851b_dpk_init(rtwdev);
1574 rtw8851b_aack(rtwdev);
1575 rtw8851b_rck(rtwdev);
1576 rtw8851b_dack(rtwdev);
1577 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0);
1578 }
1579
rtw8851b_rfk_channel(struct rtw89_dev * rtwdev)1580 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev)
1581 {
1582 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1583
1584 rtw8851b_rx_dck(rtwdev, phy_idx);
1585 rtw8851b_iqk(rtwdev, phy_idx);
1586 rtw8851b_tssi(rtwdev, phy_idx, true);
1587 rtw8851b_dpk(rtwdev, phy_idx);
1588 }
1589
rtw8851b_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1590 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1591 enum rtw89_phy_idx phy_idx)
1592 {
1593 rtw8851b_tssi_scan(rtwdev, phy_idx);
1594 }
1595
rtw8851b_rfk_scan(struct rtw89_dev * rtwdev,bool start)1596 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1597 {
1598 rtw8851b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1599 }
1600
rtw8851b_rfk_track(struct rtw89_dev * rtwdev)1601 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1602 {
1603 rtw8851b_dpk_track(rtwdev);
1604 rtw8851b_lck_track(rtwdev);
1605 }
1606
rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1607 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1608 enum rtw89_phy_idx phy_idx, s16 ref)
1609 {
1610 const u16 tssi_16dbm_cw = 0x12c;
1611 const u8 base_cw_0db = 0x27;
1612 const s8 ofst_int = 0;
1613 s16 pwr_s10_3;
1614 s16 rf_pwr_cw;
1615 u16 bb_pwr_cw;
1616 u32 pwr_cw;
1617 u32 tssi_ofst_cw;
1618
1619 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1620 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
1621 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
1622 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1623 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1624
1625 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1626 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1627 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1628 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1629
1630 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
1631 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
1632 u32_encode_bits(ref, B_DPD_REF);
1633 }
1634
rtw8851b_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1635 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1636 enum rtw89_phy_idx phy_idx)
1637 {
1638 static const u32 addr[RF_PATH_NUM_8851B] = {0x5800};
1639 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1640 const u8 ofst_ofdm = 0x4;
1641 const u8 ofst_cck = 0x8;
1642 const s16 ref_ofdm = 0;
1643 const s16 ref_cck = 0;
1644 u32 val;
1645 u8 i;
1646
1647 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1648
1649 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1650 B_AX_PWR_REF, 0x0);
1651
1652 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1653 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1654
1655 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1656 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1657 phy_idx);
1658
1659 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1660 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1661
1662 for (i = 0; i < RF_PATH_NUM_8851B; i++)
1663 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1664 phy_idx);
1665 }
1666
rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 tx_shape_idx,enum rtw89_phy_idx phy_idx)1667 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1668 const struct rtw89_chan *chan,
1669 u8 tx_shape_idx,
1670 enum rtw89_phy_idx phy_idx)
1671 {
1672 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1673 #define __DFIR_CFG_MASK 0xffffffff
1674 #define __DFIR_CFG_NR 8
1675 #define __DECL_DFIR_PARAM(_name, _val...) \
1676 static const u32 param_ ## _name[] = {_val}; \
1677 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1678
1679 __DECL_DFIR_PARAM(flat,
1680 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1681 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1682 __DECL_DFIR_PARAM(sharp,
1683 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1684 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1685 __DECL_DFIR_PARAM(sharp_14,
1686 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1687 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1688 u8 ch = chan->channel;
1689 const u32 *param;
1690 u32 addr;
1691 int i;
1692
1693 if (ch > 14) {
1694 rtw89_warn(rtwdev,
1695 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1696 return;
1697 }
1698
1699 if (ch == 14)
1700 param = param_sharp_14;
1701 else
1702 param = tx_shape_idx == 0 ? param_flat : param_sharp;
1703
1704 for (i = 0; i < __DFIR_CFG_NR; i++) {
1705 addr = __DFIR_CFG_ADDR(i);
1706 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1707 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1708 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1709 phy_idx);
1710 }
1711
1712 #undef __DECL_DFIR_PARAM
1713 #undef __DFIR_CFG_NR
1714 #undef __DFIR_CFG_MASK
1715 #undef __DECL_CFG_ADDR
1716 }
1717
rtw8851b_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1718 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1719 const struct rtw89_chan *chan,
1720 enum rtw89_phy_idx phy_idx)
1721 {
1722 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1723 u8 band = chan->band_type;
1724 u8 regd = rtw89_regd_get(rtwdev, band);
1725 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd];
1726 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd];
1727
1728 if (band == RTW89_BAND_2G)
1729 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1730
1731 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1732 tx_shape_ofdm);
1733 }
1734
rtw8851b_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1735 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1736 const struct rtw89_chan *chan,
1737 enum rtw89_phy_idx phy_idx)
1738 {
1739 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1740 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1741 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1742 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1743 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1744 }
1745
rtw8851b_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1746 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1747 enum rtw89_phy_idx phy_idx)
1748 {
1749 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1750 }
1751
1752 static
rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1753 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1754 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1755 {
1756 u32 reg;
1757
1758 if (pw_ofst < -16 || pw_ofst > 15) {
1759 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1760 return;
1761 }
1762
1763 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1764 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1765
1766 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1767 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1768
1769 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1770 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1771 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1772 }
1773
1774 static int
rtw8851b_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1775 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1776 {
1777 int ret;
1778
1779 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1780 if (ret)
1781 return ret;
1782
1783 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1784 if (ret)
1785 return ret;
1786
1787 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1788 if (ret)
1789 return ret;
1790
1791 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1792 RTW89_MAC_1 : RTW89_MAC_0);
1793
1794 return 0;
1795 }
1796
rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1797 static void rtw8851b_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1798 enum rtw89_phy_idx phy_idx)
1799 {
1800 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1801
1802 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8851b_btc_preagc_en_defs_tbl :
1803 &rtw8851b_btc_preagc_dis_defs_tbl);
1804
1805 if (!en) {
1806 if (chan->band_type == RTW89_BAND_2G) {
1807 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1808 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1809 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1810 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1811 } else {
1812 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1813 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1814 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1815 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1816 }
1817 }
1818 }
1819
rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1820 static void rtw8851b_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1821 enum rtw89_phy_idx phy_idx)
1822 {
1823 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1824
1825 if (en) {
1826 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1827 B_PATH0_BT_SHARE_V1, 0x1);
1828 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1829 B_PATH0_BTG_PATH_V1, 0x1);
1830 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1831 B_PATH0_G_LNA6_OP1DB_V1, 0x20);
1832 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1833 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x30);
1834 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1835 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1836 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1837 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1838 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1839 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1840 } else {
1841 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1842 B_PATH0_BT_SHARE_V1, 0x0);
1843 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1844 B_PATH0_BTG_PATH_V1, 0x0);
1845 if (chan->band_type == RTW89_BAND_2G) {
1846 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1847 B_PATH0_G_LNA6_OP1DB_V1, 0x80);
1848 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1849 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
1850 } else {
1851 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1852 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
1853 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1854 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1855 }
1856 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1857 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1858 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1859 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1860 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1861 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1862 }
1863 }
1864
rtw8851b_bb_ctrl_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path)1865 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1866 enum rtw89_rf_path_bit rx_path)
1867 {
1868 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1869 u32 rst_mask0;
1870
1871 if (rx_path == RF_A) {
1872 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1873 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1874 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1875 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1876 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1877 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1878 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1879 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1880 }
1881
1882 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1883
1884 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1885 if (rx_path == RF_A) {
1886 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1887 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1888 }
1889 }
1890
rtw8851b_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)1891 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1892 {
1893 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1894
1895 if (rtwdev->hal.rx_nss == 1) {
1896 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1897 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1898 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1899 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1900 }
1901
1902 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1903 }
1904
rtw8851b_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1905 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1906 {
1907 if (rtwdev->is_tssi_mode[rf_path]) {
1908 u32 addr = R_TSSI_THER + (rf_path << 13);
1909
1910 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1911 }
1912
1913 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1914 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1915 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1916
1917 fsleep(200);
1918
1919 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1920 }
1921
rtw8851b_btc_set_rfe(struct rtw89_dev * rtwdev)1922 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1923 {
1924 struct rtw89_btc *btc = &rtwdev->btc;
1925 struct rtw89_btc_module *module = &btc->mdinfo;
1926
1927 module->rfe_type = rtwdev->efuse.rfe_type;
1928 module->cv = rtwdev->hal.cv;
1929 module->bt_solo = 0;
1930 module->switch_type = BTC_SWITCH_INTERNAL;
1931 module->ant.isolation = 10;
1932 module->kt_ver_adie = rtwdev->hal.acv;
1933
1934 if (module->rfe_type == 0)
1935 return;
1936
1937 /* rfe_type 3*n+1: 1-Ant(shared),
1938 * 3*n+2: 2-Ant+Div(non-shared),
1939 * 3*n+3: 2-Ant+no-Div(non-shared)
1940 */
1941 module->ant.num = (module->rfe_type % 3 == 1) ? 1 : 2;
1942 /* WL-1ss at S0, btg at s0 (On 1 WL RF) */
1943 module->ant.single_pos = RF_PATH_A;
1944 module->ant.btg_pos = RF_PATH_A;
1945 module->ant.stream_cnt = 1;
1946
1947 if (module->ant.num == 1) {
1948 module->ant.type = BTC_ANT_SHARED;
1949 module->bt_pos = BTC_BT_BTG;
1950 module->wa_type = 1;
1951 module->ant.diversity = 0;
1952 } else { /* ant.num == 2 */
1953 module->ant.type = BTC_ANT_DEDICATED;
1954 module->bt_pos = BTC_BT_ALONE;
1955 module->switch_type = BTC_SWITCH_EXTERNAL;
1956 module->wa_type = 0;
1957 if (module->rfe_type % 3 == 2)
1958 module->ant.diversity = 1;
1959 }
1960 }
1961
1962 static
rtw8851b_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1963 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1964 {
1965 if (group > BTC_BT_SS_GROUP)
1966 group--; /* Tx-group=1, Rx-group=2 */
1967
1968 if (rtwdev->btc.mdinfo.ant.type == BTC_ANT_SHARED) /* 1-Ant */
1969 group += 3;
1970
1971 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
1972 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
1973 }
1974
rtw8851b_btc_init_cfg(struct rtw89_dev * rtwdev)1975 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
1976 {
1977 static const struct rtw89_mac_ax_coex coex_params = {
1978 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1979 .direction = RTW89_MAC_AX_COEX_INNER,
1980 };
1981 const struct rtw89_chip_info *chip = rtwdev->chip;
1982 struct rtw89_btc *btc = &rtwdev->btc;
1983 struct rtw89_btc_module *module = &btc->mdinfo;
1984 struct rtw89_btc_ant_info *ant = &module->ant;
1985 u8 path, path_min, path_max;
1986
1987 /* PTA init */
1988 rtw89_mac_coex_init(rtwdev, &coex_params);
1989
1990 /* set WL Tx response = Hi-Pri */
1991 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1992 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1993
1994 /* for 1-Ant && 1-ss case: only 1-path */
1995 if (ant->stream_cnt == 1) {
1996 path_min = ant->single_pos;
1997 path_max = path_min;
1998 } else {
1999 path_min = RF_PATH_A;
2000 path_max = RF_PATH_B;
2001 }
2002
2003 for (path = path_min; path <= path_max; path++) {
2004 /* set rf gnt-debug off */
2005 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
2006
2007 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
2008 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
2009
2010 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
2011 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
2012
2013 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
2014 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2015
2016 /* if GNT_WL = 0 && BT = Tx_group -->
2017 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
2018 */
2019 if (ant->type == BTC_ANT_SHARED && ant->btg_pos == path)
2020 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2021 else
2022 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2023
2024 /* set DEBUG_LUT_RFMODE_MASK = 0 to stop trx-mask-setup */
2025 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2026 }
2027
2028 /* set PTA break table */
2029 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2030
2031 /* enable BT counter 0xda40[16,2] = 2b'11 */
2032 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2033
2034 btc->cx.wl.status.map.init_ok = true;
2035 }
2036
2037 static
rtw8851b_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)2038 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2039 {
2040 u32 bitmap;
2041 u32 reg;
2042
2043 switch (map) {
2044 case BTC_PRI_MASK_TX_RESP:
2045 reg = R_BTC_BT_COEX_MSK_TABLE;
2046 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
2047 break;
2048 case BTC_PRI_MASK_BEACON:
2049 reg = R_AX_WL_PRI_MSK;
2050 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
2051 break;
2052 case BTC_PRI_MASK_RX_CCK:
2053 reg = R_BTC_BT_COEX_MSK_TABLE;
2054 bitmap = B_BTC_PRI_MASK_RXCCK_V1;
2055 break;
2056 default:
2057 return;
2058 }
2059
2060 if (state)
2061 rtw89_write32_set(rtwdev, reg, bitmap);
2062 else
2063 rtw89_write32_clr(rtwdev, reg, bitmap);
2064 }
2065
2066 union rtw8851b_btc_wl_txpwr_ctrl {
2067 u32 txpwr_val;
2068 struct {
2069 union {
2070 u16 ctrl_all_time;
2071 struct {
2072 s16 data:9;
2073 u16 rsvd:6;
2074 u16 flag:1;
2075 } all_time;
2076 };
2077 union {
2078 u16 ctrl_gnt_bt;
2079 struct {
2080 s16 data:9;
2081 u16 rsvd:7;
2082 } gnt_bt;
2083 };
2084 };
2085 } __packed;
2086
2087 static void
rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)2088 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2089 {
2090 union rtw8851b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2091 s32 val;
2092
2093 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2094 do { \
2095 u32 _wrt = FIELD_PREP(_msk, _val); \
2096 BUILD_BUG_ON(!!(_msk & _en)); \
2097 if (_cond) \
2098 _wrt |= _en; \
2099 else \
2100 _wrt &= ~_en; \
2101 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2102 _msk | _en, _wrt); \
2103 } while (0)
2104
2105 switch (arg.ctrl_all_time) {
2106 case 0xffff:
2107 val = 0;
2108 break;
2109 default:
2110 val = arg.all_time.data;
2111 break;
2112 }
2113
2114 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2115 val, B_AX_FORCE_PWR_BY_RATE_EN,
2116 arg.ctrl_all_time != 0xffff);
2117
2118 switch (arg.ctrl_gnt_bt) {
2119 case 0xffff:
2120 val = 0;
2121 break;
2122 default:
2123 val = arg.gnt_bt.data;
2124 break;
2125 }
2126
2127 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2128 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2129
2130 #undef __write_ctrl
2131 }
2132
2133 static
rtw8851b_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2134 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2135 {
2136 val = clamp_t(s8, val, -100, 0) + 100;
2137 val = min(val + 6, 100); /* compensate offset */
2138
2139 return val;
2140 }
2141
2142 static
rtw8851b_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2143 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2144 {
2145 /* Feature move to firmware */
2146 }
2147
rtw8851b_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2148 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2149 {
2150 struct rtw89_btc *btc = &rtwdev->btc;
2151 struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
2152
2153 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2154 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2155 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2156
2157 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2158 if (state)
2159 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2160 else
2161 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2162
2163 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2164 }
2165
2166 #define LNA2_51B_MA 0x700
2167
2168 static const struct rtw89_reg2_def btc_8851b_rf_0[] = {{0x2, 0x0}};
2169 static const struct rtw89_reg2_def btc_8851b_rf_1[] = {{0x2, 0x1}};
2170
rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)2171 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2172 {
2173 /* To improve BT ACI in co-rx
2174 * level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2175 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2176 */
2177 struct rtw89_btc *btc = &rtwdev->btc;
2178 struct rtw89_btc_ant_info *ant = &btc->mdinfo.ant;
2179 const struct rtw89_reg2_def *rf;
2180 u32 n, i, val;
2181
2182 switch (level) {
2183 case 0: /* original */
2184 default:
2185 btc->dm.wl_lna2 = 0;
2186 break;
2187 case 1: /* for FDD free-run */
2188 btc->dm.wl_lna2 = 0;
2189 break;
2190 case 2: /* for BTG Co-Rx*/
2191 btc->dm.wl_lna2 = 1;
2192 break;
2193 }
2194
2195 if (btc->dm.wl_lna2 == 0) {
2196 rf = btc_8851b_rf_0;
2197 n = ARRAY_SIZE(btc_8851b_rf_0);
2198 } else {
2199 rf = btc_8851b_rf_1;
2200 n = ARRAY_SIZE(btc_8851b_rf_1);
2201 }
2202
2203 for (i = 0; i < n; i++, rf++) {
2204 val = rf->data;
2205 /* bit[10] = 1 if non-shared-ant for 8851b */
2206 if (btc->mdinfo.ant.type == BTC_ANT_DEDICATED)
2207 val |= 0x4;
2208
2209 rtw89_write_rf(rtwdev, ant->btg_pos, rf->addr, LNA2_51B_MA, val);
2210 }
2211 }
2212
rtw8851b_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2213 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2214 struct rtw89_rx_phy_ppdu *phy_ppdu,
2215 struct ieee80211_rx_status *status)
2216 {
2217 u16 chan = phy_ppdu->chan_idx;
2218 enum nl80211_band band;
2219 u8 ch;
2220
2221 if (chan == 0)
2222 return;
2223
2224 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2225 status->freq = ieee80211_channel_to_frequency(ch, band);
2226 status->band = band;
2227 }
2228
rtw8851b_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2229 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2230 struct rtw89_rx_phy_ppdu *phy_ppdu,
2231 struct ieee80211_rx_status *status)
2232 {
2233 u8 path;
2234 u8 *rx_power = phy_ppdu->rssi;
2235
2236 status->signal = RTW89_RSSI_RAW_TO_DBM(rx_power[RF_PATH_A]);
2237
2238 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2239 status->chains |= BIT(path);
2240 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2241 }
2242 if (phy_ppdu->valid)
2243 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2244 }
2245
rtw8851b_mac_enable_bb_rf(struct rtw89_dev * rtwdev)2246 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2247 {
2248 int ret;
2249
2250 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2251 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2252 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2253 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2254 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2255
2256 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2257 FULL_BIT_MASK);
2258 if (ret)
2259 return ret;
2260
2261 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2262 FULL_BIT_MASK);
2263 if (ret)
2264 return ret;
2265
2266 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2267
2268 return 0;
2269 }
2270
rtw8851b_mac_disable_bb_rf(struct rtw89_dev * rtwdev)2271 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2272 {
2273 u8 wl_rfc_s0;
2274 u8 wl_rfc_s1;
2275 int ret;
2276
2277 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2278 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2279
2280 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2281 if (ret)
2282 return ret;
2283 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2284 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2285 FULL_BIT_MASK);
2286 if (ret)
2287 return ret;
2288
2289 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2290 if (ret)
2291 return ret;
2292 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2293 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2294 FULL_BIT_MASK);
2295 return ret;
2296 }
2297
2298 static const struct rtw89_chip_ops rtw8851b_chip_ops = {
2299 .enable_bb_rf = rtw8851b_mac_enable_bb_rf,
2300 .disable_bb_rf = rtw8851b_mac_disable_bb_rf,
2301 .bb_preinit = NULL,
2302 .bb_reset = rtw8851b_bb_reset,
2303 .bb_sethw = rtw8851b_bb_sethw,
2304 .read_rf = rtw89_phy_read_rf_v1,
2305 .write_rf = rtw89_phy_write_rf_v1,
2306 .set_channel = rtw8851b_set_channel,
2307 .set_channel_help = rtw8851b_set_channel_help,
2308 .read_efuse = rtw8851b_read_efuse,
2309 .read_phycap = rtw8851b_read_phycap,
2310 .fem_setup = NULL,
2311 .rfe_gpio = rtw8851b_rfe_gpio,
2312 .rfk_init = rtw8851b_rfk_init,
2313 .rfk_channel = rtw8851b_rfk_channel,
2314 .rfk_band_changed = rtw8851b_rfk_band_changed,
2315 .rfk_scan = rtw8851b_rfk_scan,
2316 .rfk_track = rtw8851b_rfk_track,
2317 .power_trim = rtw8851b_power_trim,
2318 .set_txpwr = rtw8851b_set_txpwr,
2319 .set_txpwr_ctrl = rtw8851b_set_txpwr_ctrl,
2320 .init_txpwr_unit = rtw8851b_init_txpwr_unit,
2321 .get_thermal = rtw8851b_get_thermal,
2322 .ctrl_btg_bt_rx = rtw8851b_ctrl_btg_bt_rx,
2323 .query_ppdu = rtw8851b_query_ppdu,
2324 .ctrl_nbtg_bt_tx = rtw8851b_ctrl_nbtg_bt_tx,
2325 .cfg_txrx_path = rtw8851b_bb_cfg_txrx_path,
2326 .set_txpwr_ul_tb_offset = rtw8851b_set_txpwr_ul_tb_offset,
2327 .pwr_on_func = rtw8851b_pwr_on_func,
2328 .pwr_off_func = rtw8851b_pwr_off_func,
2329 .query_rxdesc = rtw89_core_query_rxdesc,
2330 .fill_txdesc = rtw89_core_fill_txdesc,
2331 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2332 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2333 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2334 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2335 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2336 .h2c_dctl_sec_cam = NULL,
2337
2338 .btc_set_rfe = rtw8851b_btc_set_rfe,
2339 .btc_init_cfg = rtw8851b_btc_init_cfg,
2340 .btc_set_wl_pri = rtw8851b_btc_set_wl_pri,
2341 .btc_set_wl_txpwr_ctrl = rtw8851b_btc_set_wl_txpwr_ctrl,
2342 .btc_get_bt_rssi = rtw8851b_btc_get_bt_rssi,
2343 .btc_update_bt_cnt = rtw8851b_btc_update_bt_cnt,
2344 .btc_wl_s1_standby = rtw8851b_btc_wl_s1_standby,
2345 .btc_set_wl_rx_gain = rtw8851b_btc_set_wl_rx_gain,
2346 .btc_set_policy = rtw89_btc_set_policy_v1,
2347 };
2348
2349 #ifdef CONFIG_PM
2350 static const struct wiphy_wowlan_support rtw_wowlan_stub_8851b = {
2351 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2352 .n_patterns = RTW89_MAX_PATTERN_NUM,
2353 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2354 .pattern_min_len = 1,
2355 };
2356 #endif
2357
2358 const struct rtw89_chip_info rtw8851b_chip_info = {
2359 .chip_id = RTL8851B,
2360 .chip_gen = RTW89_CHIP_AX,
2361 .ops = &rtw8851b_chip_ops,
2362 .mac_def = &rtw89_mac_gen_ax,
2363 .phy_def = &rtw89_phy_gen_ax,
2364 .fw_basename = RTW8851B_FW_BASENAME,
2365 .fw_format_max = RTW8851B_FW_FORMAT_MAX,
2366 .try_ce_fw = true,
2367 .bbmcu_nr = 0,
2368 .needed_fw_elms = 0,
2369 .fifo_size = 196608,
2370 .small_fifo_size = true,
2371 .dle_scc_rsvd_size = 98304,
2372 .max_amsdu_limit = 3500,
2373 .dis_2g_40m_ul_ofdma = true,
2374 .rsvd_ple_ofst = 0x2f800,
2375 .hfc_param_ini = rtw8851b_hfc_param_ini_pcie,
2376 .dle_mem = rtw8851b_dle_mem_pcie,
2377 .wde_qempty_acq_grpnum = 4,
2378 .wde_qempty_mgq_grpsel = 4,
2379 .rf_base_addr = {0xe000},
2380 .pwr_on_seq = NULL,
2381 .pwr_off_seq = NULL,
2382 .bb_table = &rtw89_8851b_phy_bb_table,
2383 .bb_gain_table = &rtw89_8851b_phy_bb_gain_table,
2384 .rf_table = {&rtw89_8851b_phy_radioa_table,},
2385 .nctl_table = &rtw89_8851b_phy_nctl_table,
2386 .nctl_post_table = &rtw8851b_nctl_post_defs_tbl,
2387 .dflt_parms = &rtw89_8851b_dflt_parms,
2388 .rfe_parms_conf = rtw89_8851b_rfe_parms_conf,
2389 .txpwr_factor_rf = 2,
2390 .txpwr_factor_mac = 1,
2391 .dig_table = NULL,
2392 .dig_regs = &rtw8851b_dig_regs,
2393 .tssi_dbw_table = NULL,
2394 .support_chanctx_num = 0,
2395 .support_bands = BIT(NL80211_BAND_2GHZ) |
2396 BIT(NL80211_BAND_5GHZ),
2397 .support_bw160 = false,
2398 .support_unii4 = true,
2399 .ul_tb_waveform_ctrl = true,
2400 .ul_tb_pwr_diff = false,
2401 .hw_sec_hdr = false,
2402 .rf_path_num = 1,
2403 .tx_nss = 1,
2404 .rx_nss = 1,
2405 .acam_num = 32,
2406 .bcam_num = 20,
2407 .scam_num = 128,
2408 .bacam_num = 2,
2409 .bacam_dynamic_num = 4,
2410 .bacam_ver = RTW89_BACAM_V0,
2411 .ppdu_max_usr = 4,
2412 .sec_ctrl_efuse_size = 4,
2413 .physical_efuse_size = 1216,
2414 .logical_efuse_size = 2048,
2415 .limit_efuse_size = 1280,
2416 .dav_phy_efuse_size = 0,
2417 .dav_log_efuse_size = 0,
2418 .efuse_blocks = NULL,
2419 .phycap_addr = 0x580,
2420 .phycap_size = 128,
2421 .para_ver = 0,
2422 .wlcx_desired = 0x06000000,
2423 .btcx_desired = 0x7,
2424 .scbd = 0x1,
2425 .mailbox = 0x1,
2426
2427 .afh_guard_ch = 6,
2428 .wl_rssi_thres = rtw89_btc_8851b_wl_rssi_thres,
2429 .bt_rssi_thres = rtw89_btc_8851b_bt_rssi_thres,
2430 .rssi_tol = 2,
2431 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8851b_mon_reg),
2432 .mon_reg = rtw89_btc_8851b_mon_reg,
2433 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_ul),
2434 .rf_para_ulink = rtw89_btc_8851b_rf_ul,
2435 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8851b_rf_dl),
2436 .rf_para_dlink = rtw89_btc_8851b_rf_dl,
2437 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2438 BIT(RTW89_PS_MODE_CLK_GATED),
2439 .low_power_hci_modes = 0,
2440 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2441 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2442 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2443 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2444 .txwd_info_size = sizeof(struct rtw89_txwd_info),
2445 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2446 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2447 .h2c_regs = rtw8851b_h2c_regs,
2448 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2449 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2450 .c2h_regs = rtw8851b_c2h_regs,
2451 .page_regs = &rtw8851b_page_regs,
2452 .cfo_src_fd = true,
2453 .cfo_hw_comp = true,
2454 .dcfo_comp = &rtw8851b_dcfo_comp,
2455 .dcfo_comp_sft = 12,
2456 .imr_info = &rtw8851b_imr_info,
2457 .imr_dmac_table = NULL,
2458 .imr_cmac_table = NULL,
2459 .rrsr_cfgs = &rtw8851b_rrsr_cfgs,
2460 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
2461 .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
2462 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
2463 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
2464 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
2465 .edcca_regs = &rtw8851b_edcca_regs,
2466 #ifdef CONFIG_PM
2467 .wowlan_stub = &rtw_wowlan_stub_8851b,
2468 #endif
2469 .xtal_info = &rtw8851b_xtal_info,
2470 };
2471 EXPORT_SYMBOL(rtw8851b_chip_info);
2472
2473 MODULE_FIRMWARE(RTW8851B_MODULE_FIRMWARE);
2474 MODULE_AUTHOR("Realtek Corporation");
2475 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8851B driver");
2476 MODULE_LICENSE("Dual BSD/GPL");
2477