1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9 #include "reg.h"
10
11 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
12 #define ADDR_CAM_ENT_SIZE 0x40
13 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
14 #define BSSID_CAM_ENT_SIZE 0x08
15 #define HFC_PAGE_UNIT 64
16 #define RPWM_TRY_CNT 3
17
18 enum rtw89_mac_hwmod_sel {
19 RTW89_DMAC_SEL = 0,
20 RTW89_CMAC_SEL = 1,
21
22 RTW89_MAC_INVALID,
23 };
24
25 enum rtw89_mac_fwd_target {
26 RTW89_FWD_DONT_CARE = 0,
27 RTW89_FWD_TO_HOST = 1,
28 RTW89_FWD_TO_WLAN_CPU = 2
29 };
30
31 enum rtw89_mac_wd_dma_intvl {
32 RTW89_MAC_WD_DMA_INTVL_0S,
33 RTW89_MAC_WD_DMA_INTVL_256NS,
34 RTW89_MAC_WD_DMA_INTVL_512NS,
35 RTW89_MAC_WD_DMA_INTVL_768NS,
36 RTW89_MAC_WD_DMA_INTVL_1US,
37 RTW89_MAC_WD_DMA_INTVL_1_5US,
38 RTW89_MAC_WD_DMA_INTVL_2US,
39 RTW89_MAC_WD_DMA_INTVL_4US,
40 RTW89_MAC_WD_DMA_INTVL_8US,
41 RTW89_MAC_WD_DMA_INTVL_16US,
42 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
43 };
44
45 enum rtw89_mac_multi_tag_num {
46 RTW89_MAC_TAG_NUM_1,
47 RTW89_MAC_TAG_NUM_2,
48 RTW89_MAC_TAG_NUM_3,
49 RTW89_MAC_TAG_NUM_4,
50 RTW89_MAC_TAG_NUM_5,
51 RTW89_MAC_TAG_NUM_6,
52 RTW89_MAC_TAG_NUM_7,
53 RTW89_MAC_TAG_NUM_8,
54 RTW89_MAC_TAG_NUM_DEF = 0xFE
55 };
56
57 enum rtw89_mac_lbc_tmr {
58 RTW89_MAC_LBC_TMR_8US = 0,
59 RTW89_MAC_LBC_TMR_16US,
60 RTW89_MAC_LBC_TMR_32US,
61 RTW89_MAC_LBC_TMR_64US,
62 RTW89_MAC_LBC_TMR_128US,
63 RTW89_MAC_LBC_TMR_256US,
64 RTW89_MAC_LBC_TMR_512US,
65 RTW89_MAC_LBC_TMR_1MS,
66 RTW89_MAC_LBC_TMR_2MS,
67 RTW89_MAC_LBC_TMR_4MS,
68 RTW89_MAC_LBC_TMR_8MS,
69 RTW89_MAC_LBC_TMR_DEF = 0xFE
70 };
71
72 enum rtw89_mac_cpuio_op_cmd_type {
73 CPUIO_OP_CMD_GET_1ST_PID = 0,
74 CPUIO_OP_CMD_GET_NEXT_PID = 1,
75 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
76 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
77 CPUIO_OP_CMD_DEQ = 8,
78 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
79 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
80 };
81
82 enum rtw89_mac_wde_dle_port_id {
83 WDE_DLE_PORT_ID_DISPATCH = 0,
84 WDE_DLE_PORT_ID_PKTIN = 1,
85 WDE_DLE_PORT_ID_CMAC0 = 3,
86 WDE_DLE_PORT_ID_CMAC1 = 4,
87 WDE_DLE_PORT_ID_CPU_IO = 6,
88 WDE_DLE_PORT_ID_WDRLS = 7,
89 WDE_DLE_PORT_ID_END = 8
90 };
91
92 enum rtw89_mac_wde_dle_queid_wdrls {
93 WDE_DLE_QUEID_TXOK = 0,
94 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
95 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
96 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
97 WDE_DLE_QUEID_NO_REPORT = 4
98 };
99
100 enum rtw89_mac_ple_dle_port_id {
101 PLE_DLE_PORT_ID_DISPATCH = 0,
102 PLE_DLE_PORT_ID_MPDU = 1,
103 PLE_DLE_PORT_ID_SEC = 2,
104 PLE_DLE_PORT_ID_CMAC0 = 3,
105 PLE_DLE_PORT_ID_CMAC1 = 4,
106 PLE_DLE_PORT_ID_WDRLS = 5,
107 PLE_DLE_PORT_ID_CPU_IO = 6,
108 PLE_DLE_PORT_ID_PLRLS = 7,
109 PLE_DLE_PORT_ID_END = 8
110 };
111
112 enum rtw89_mac_ple_dle_queid_plrls {
113 PLE_DLE_QUEID_NO_REPORT = 0x0
114 };
115
116 enum rtw89_machdr_frame_type {
117 RTW89_MGNT = 0,
118 RTW89_CTRL = 1,
119 RTW89_DATA = 2,
120 };
121
122 enum rtw89_mac_dle_dfi_type {
123 DLE_DFI_TYPE_FREEPG = 0,
124 DLE_DFI_TYPE_QUOTA = 1,
125 DLE_DFI_TYPE_PAGELLT = 2,
126 DLE_DFI_TYPE_PKTINFO = 3,
127 DLE_DFI_TYPE_PREPKTLLT = 4,
128 DLE_DFI_TYPE_NXTPKTLLT = 5,
129 DLE_DFI_TYPE_QLNKTBL = 6,
130 DLE_DFI_TYPE_QEMPTY = 7,
131 };
132
133 enum rtw89_mac_dle_wde_quota_id {
134 WDE_QTAID_HOST_IF = 0,
135 WDE_QTAID_WLAN_CPU = 1,
136 WDE_QTAID_DATA_CPU = 2,
137 WDE_QTAID_PKTIN = 3,
138 WDE_QTAID_CPUIO = 4,
139 };
140
141 enum rtw89_mac_dle_ple_quota_id {
142 PLE_QTAID_B0_TXPL = 0,
143 PLE_QTAID_B1_TXPL = 1,
144 PLE_QTAID_C2H = 2,
145 PLE_QTAID_H2C = 3,
146 PLE_QTAID_WLAN_CPU = 4,
147 PLE_QTAID_MPDU = 5,
148 PLE_QTAID_CMAC0_RX = 6,
149 PLE_QTAID_CMAC1_RX = 7,
150 PLE_QTAID_CMAC1_BBRPT = 8,
151 PLE_QTAID_WDRLS = 9,
152 PLE_QTAID_CPUIO = 10,
153 };
154
155 enum rtw89_mac_dle_ctrl_type {
156 DLE_CTRL_TYPE_WDE = 0,
157 DLE_CTRL_TYPE_PLE = 1,
158 DLE_CTRL_TYPE_NUM = 2,
159 };
160
161 enum rtw89_mac_ax_l0_to_l1_event {
162 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
163 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
164 MAC_AX_L0_TO_L1_RLS_PKID = 2,
165 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
166 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
167 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
168 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
169 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
170 };
171
172 #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) ((shift_tu) * 1024 / 32)
173
174 enum rtw89_mac_dbg_port_sel {
175 /* CMAC 0 related */
176 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
177 RTW89_DBG_PORT_SEL_SCH_C0,
178 RTW89_DBG_PORT_SEL_TMAC_C0,
179 RTW89_DBG_PORT_SEL_RMAC_C0,
180 RTW89_DBG_PORT_SEL_RMACST_C0,
181 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
182 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
183 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
184 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
185 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
186 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
187 /* CMAC 1 related */
188 RTW89_DBG_PORT_SEL_PTCL_C1,
189 RTW89_DBG_PORT_SEL_SCH_C1,
190 RTW89_DBG_PORT_SEL_TMAC_C1,
191 RTW89_DBG_PORT_SEL_RMAC_C1,
192 RTW89_DBG_PORT_SEL_RMACST_C1,
193 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
194 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
195 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
196 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
197 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
198 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
199 /* DLE related */
200 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
201 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
202 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
203 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
204 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
205 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
206 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
207 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
208 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
209 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
210 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
211 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
212 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
213 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
214 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
215 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
216 RTW89_DBG_PORT_SEL_PKTINFO,
217 /* DISPATCHER related */
218 RTW89_DBG_PORT_SEL_DSPT_HDT_TX0,
219 RTW89_DBG_PORT_SEL_DSPT_HDT_TX1,
220 RTW89_DBG_PORT_SEL_DSPT_HDT_TX2,
221 RTW89_DBG_PORT_SEL_DSPT_HDT_TX3,
222 RTW89_DBG_PORT_SEL_DSPT_HDT_TX4,
223 RTW89_DBG_PORT_SEL_DSPT_HDT_TX5,
224 RTW89_DBG_PORT_SEL_DSPT_HDT_TX6,
225 RTW89_DBG_PORT_SEL_DSPT_HDT_TX7,
226 RTW89_DBG_PORT_SEL_DSPT_HDT_TX8,
227 RTW89_DBG_PORT_SEL_DSPT_HDT_TX9,
228 RTW89_DBG_PORT_SEL_DSPT_HDT_TXA,
229 RTW89_DBG_PORT_SEL_DSPT_HDT_TXB,
230 RTW89_DBG_PORT_SEL_DSPT_HDT_TXC,
231 RTW89_DBG_PORT_SEL_DSPT_HDT_TXD,
232 RTW89_DBG_PORT_SEL_DSPT_HDT_TXE,
233 RTW89_DBG_PORT_SEL_DSPT_HDT_TXF,
234 RTW89_DBG_PORT_SEL_DSPT_CDT_TX0,
235 RTW89_DBG_PORT_SEL_DSPT_CDT_TX1,
236 RTW89_DBG_PORT_SEL_DSPT_CDT_TX3,
237 RTW89_DBG_PORT_SEL_DSPT_CDT_TX4,
238 RTW89_DBG_PORT_SEL_DSPT_CDT_TX5,
239 RTW89_DBG_PORT_SEL_DSPT_CDT_TX6,
240 RTW89_DBG_PORT_SEL_DSPT_CDT_TX7,
241 RTW89_DBG_PORT_SEL_DSPT_CDT_TX8,
242 RTW89_DBG_PORT_SEL_DSPT_CDT_TX9,
243 RTW89_DBG_PORT_SEL_DSPT_CDT_TXA,
244 RTW89_DBG_PORT_SEL_DSPT_CDT_TXB,
245 RTW89_DBG_PORT_SEL_DSPT_CDT_TXC,
246 RTW89_DBG_PORT_SEL_DSPT_HDT_RX0,
247 RTW89_DBG_PORT_SEL_DSPT_HDT_RX1,
248 RTW89_DBG_PORT_SEL_DSPT_HDT_RX2,
249 RTW89_DBG_PORT_SEL_DSPT_HDT_RX3,
250 RTW89_DBG_PORT_SEL_DSPT_HDT_RX4,
251 RTW89_DBG_PORT_SEL_DSPT_HDT_RX5,
252 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0,
253 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0,
254 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1,
255 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2,
256 RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1,
257 RTW89_DBG_PORT_SEL_DSPT_STF_CTRL,
258 RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL,
259 RTW89_DBG_PORT_SEL_DSPT_WDE_INTF,
260 RTW89_DBG_PORT_SEL_DSPT_PLE_INTF,
261 RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL,
262 /* PCIE related */
263 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
264 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
265 RTW89_DBG_PORT_SEL_PCIE_CVT,
266 RTW89_DBG_PORT_SEL_PCIE_CXPL,
267 RTW89_DBG_PORT_SEL_PCIE_IO,
268 RTW89_DBG_PORT_SEL_PCIE_MISC,
269 RTW89_DBG_PORT_SEL_PCIE_MISC2,
270
271 /* keep last */
272 RTW89_DBG_PORT_SEL_LAST,
273 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
274 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
275 };
276
277 /* SRAM mem dump */
278 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
279 #define R_BE_INDIR_ACCESS_ENTRY 0x80000
280
281 #define AXIDMA_BASE_ADDR 0x18006000
282 #define STA_SCHED_BASE_ADDR 0x18808000
283 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
284 #define SECURITY_CAM_BASE_ADDR 0x18814000
285 #define WOW_CAM_BASE_ADDR 0x18815000
286 #define CMAC_TBL_BASE_ADDR 0x18840000
287 #define ADDR_CAM_BASE_ADDR 0x18850000
288 #define BSSID_CAM_BASE_ADDR 0x18853000
289 #define BA_CAM_BASE_ADDR 0x18854000
290 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
291 #define SHARED_BUF_BASE_ADDR 0x18700000
292 #define DMAC_TBL_BASE_ADDR 0x18800000
293 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
294 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
295 #define TXD_FIFO_0_BASE_ADDR 0x18856200
296 #define TXD_FIFO_1_BASE_ADDR 0x188A1080
297 #define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
298 #define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
299 #define TXDATA_FIFO_0_BASE_ADDR 0x18856000
300 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
301 #define CPU_LOCAL_BASE_ADDR 0x18003000
302
303 #define WD_PAGE_BASE_ADDR_BE 0x0
304 #define CPU_LOCAL_BASE_ADDR_BE 0x18003000
305 #define AXIDMA_BASE_ADDR_BE 0x18006000
306 #define SHARED_BUF_BASE_ADDR_BE 0x18700000
307 #define DMAC_TBL_BASE_ADDR_BE 0x18800000
308 #define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
309 #define STA_SCHED_BASE_ADDR_BE 0x18818000
310 #define NAT25_CAM_BASE_ADDR_BE 0x18820000
311 #define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
312 #define SEC_CAM_BASE_ADDR_BE 0x18824000
313 #define WOW_CAM_BASE_ADDR_BE 0x18828000
314 #define MLD_TBL_BASE_ADDR_BE 0x18829000
315 #define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
316 #define CMAC_TBL_BASE_ADDR_BE 0x18840000
317 #define ADDR_CAM_BASE_ADDR_BE 0x18850000
318 #define BSSID_CAM_BASE_ADDR_BE 0x18858000
319 #define BA_CAM_BASE_ADDR_BE 0x18859000
320 #define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
321 #define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
322 #define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
323 #define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
324 #define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
325 #define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
326 #define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
327
328 #define CCTL_INFO_SIZE 32
329
330 enum rtw89_mac_mem_sel {
331 RTW89_MAC_MEM_AXIDMA,
332 RTW89_MAC_MEM_SHARED_BUF,
333 RTW89_MAC_MEM_DMAC_TBL,
334 RTW89_MAC_MEM_SHCUT_MACHDR,
335 RTW89_MAC_MEM_STA_SCHED,
336 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
337 RTW89_MAC_MEM_SECURITY_CAM,
338 RTW89_MAC_MEM_WOW_CAM,
339 RTW89_MAC_MEM_CMAC_TBL,
340 RTW89_MAC_MEM_ADDR_CAM,
341 RTW89_MAC_MEM_BA_CAM,
342 RTW89_MAC_MEM_BCN_IE_CAM0,
343 RTW89_MAC_MEM_BCN_IE_CAM1,
344 RTW89_MAC_MEM_TXD_FIFO_0,
345 RTW89_MAC_MEM_TXD_FIFO_1,
346 RTW89_MAC_MEM_TXDATA_FIFO_0,
347 RTW89_MAC_MEM_TXDATA_FIFO_1,
348 RTW89_MAC_MEM_CPU_LOCAL,
349 RTW89_MAC_MEM_BSSID_CAM,
350 RTW89_MAC_MEM_TXD_FIFO_0_V1,
351 RTW89_MAC_MEM_TXD_FIFO_1_V1,
352 RTW89_MAC_MEM_WD_PAGE,
353
354 /* keep last */
355 RTW89_MAC_MEM_NUM,
356 };
357
358 enum rtw89_rpwm_req_pwr_state {
359 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
360 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
361 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
362 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
363 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
364 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
365 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
366 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
367 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
368 };
369
370 struct rtw89_pwr_cfg {
371 u16 addr;
372 u8 cv_msk;
373 u8 intf_msk;
374 u8 base:4;
375 u8 cmd:4;
376 u8 msk;
377 u8 val;
378 };
379
380 enum rtw89_mac_c2h_ofld_func {
381 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
382 RTW89_MAC_C2H_FUNC_READ_RSP,
383 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
384 RTW89_MAC_C2H_FUNC_BCN_RESEND,
385 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
386 RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT = 0x6,
387 RTW89_MAC_C2H_FUNC_SCANOFLD_RSP = 0x9,
388 RTW89_MAC_C2H_FUNC_BCNFLTR_RPT = 0xd,
389 RTW89_MAC_C2H_FUNC_OFLD_MAX,
390 };
391
392 enum rtw89_mac_c2h_info_func {
393 RTW89_MAC_C2H_FUNC_REC_ACK,
394 RTW89_MAC_C2H_FUNC_DONE_ACK,
395 RTW89_MAC_C2H_FUNC_C2H_LOG,
396 RTW89_MAC_C2H_FUNC_BCN_CNT,
397 RTW89_MAC_C2H_FUNC_INFO_MAX,
398 };
399
400 enum rtw89_mac_c2h_mcc_func {
401 RTW89_MAC_C2H_FUNC_MCC_RCV_ACK = 0,
402 RTW89_MAC_C2H_FUNC_MCC_REQ_ACK = 1,
403 RTW89_MAC_C2H_FUNC_MCC_TSF_RPT = 2,
404 RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT = 3,
405
406 NUM_OF_RTW89_MAC_C2H_FUNC_MCC,
407 };
408
409 enum rtw89_mac_c2h_class {
410 RTW89_MAC_C2H_CLASS_INFO,
411 RTW89_MAC_C2H_CLASS_OFLD,
412 RTW89_MAC_C2H_CLASS_TWT,
413 RTW89_MAC_C2H_CLASS_WOW,
414 RTW89_MAC_C2H_CLASS_MCC,
415 RTW89_MAC_C2H_CLASS_FWDBG,
416 RTW89_MAC_C2H_CLASS_MAX,
417 };
418
419 enum rtw89_mac_mcc_status {
420 RTW89_MAC_MCC_ADD_ROLE_OK = 0,
421 RTW89_MAC_MCC_START_GROUP_OK = 1,
422 RTW89_MAC_MCC_STOP_GROUP_OK = 2,
423 RTW89_MAC_MCC_DEL_GROUP_OK = 3,
424 RTW89_MAC_MCC_RESET_GROUP_OK = 4,
425 RTW89_MAC_MCC_SWITCH_CH_OK = 5,
426 RTW89_MAC_MCC_TXNULL0_OK = 6,
427 RTW89_MAC_MCC_TXNULL1_OK = 7,
428
429 RTW89_MAC_MCC_SWITCH_EARLY = 10,
430 RTW89_MAC_MCC_TBTT = 11,
431 RTW89_MAC_MCC_DURATION_START = 12,
432 RTW89_MAC_MCC_DURATION_END = 13,
433
434 RTW89_MAC_MCC_ADD_ROLE_FAIL = 20,
435 RTW89_MAC_MCC_START_GROUP_FAIL = 21,
436 RTW89_MAC_MCC_STOP_GROUP_FAIL = 22,
437 RTW89_MAC_MCC_DEL_GROUP_FAIL = 23,
438 RTW89_MAC_MCC_RESET_GROUP_FAIL = 24,
439 RTW89_MAC_MCC_SWITCH_CH_FAIL = 25,
440 RTW89_MAC_MCC_TXNULL0_FAIL = 26,
441 RTW89_MAC_MCC_TXNULL1_FAIL = 27,
442 };
443
444 struct rtw89_mac_ax_coex {
445 #define RTW89_MAC_AX_COEX_RTK_MODE 0
446 #define RTW89_MAC_AX_COEX_CSR_MODE 1
447 u8 pta_mode;
448 #define RTW89_MAC_AX_COEX_INNER 0
449 #define RTW89_MAC_AX_COEX_OUTPUT 1
450 #define RTW89_MAC_AX_COEX_INPUT 2
451 u8 direction;
452 };
453
454 struct rtw89_mac_ax_plt {
455 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
456 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
457 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
458 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
459 u8 band;
460 u8 tx;
461 u8 rx;
462 };
463
464 enum rtw89_mac_bf_rrsc_rate {
465 RTW89_MAC_BF_RRSC_6M = 0,
466 RTW89_MAC_BF_RRSC_9M = 1,
467 RTW89_MAC_BF_RRSC_12M,
468 RTW89_MAC_BF_RRSC_18M,
469 RTW89_MAC_BF_RRSC_24M,
470 RTW89_MAC_BF_RRSC_36M,
471 RTW89_MAC_BF_RRSC_48M,
472 RTW89_MAC_BF_RRSC_54M,
473 RTW89_MAC_BF_RRSC_HT_MSC0,
474 RTW89_MAC_BF_RRSC_HT_MSC1,
475 RTW89_MAC_BF_RRSC_HT_MSC2,
476 RTW89_MAC_BF_RRSC_HT_MSC3,
477 RTW89_MAC_BF_RRSC_HT_MSC4,
478 RTW89_MAC_BF_RRSC_HT_MSC5,
479 RTW89_MAC_BF_RRSC_HT_MSC6,
480 RTW89_MAC_BF_RRSC_HT_MSC7,
481 RTW89_MAC_BF_RRSC_VHT_MSC0,
482 RTW89_MAC_BF_RRSC_VHT_MSC1,
483 RTW89_MAC_BF_RRSC_VHT_MSC2,
484 RTW89_MAC_BF_RRSC_VHT_MSC3,
485 RTW89_MAC_BF_RRSC_VHT_MSC4,
486 RTW89_MAC_BF_RRSC_VHT_MSC5,
487 RTW89_MAC_BF_RRSC_VHT_MSC6,
488 RTW89_MAC_BF_RRSC_VHT_MSC7,
489 RTW89_MAC_BF_RRSC_HE_MSC0,
490 RTW89_MAC_BF_RRSC_HE_MSC1,
491 RTW89_MAC_BF_RRSC_HE_MSC2,
492 RTW89_MAC_BF_RRSC_HE_MSC3,
493 RTW89_MAC_BF_RRSC_HE_MSC4,
494 RTW89_MAC_BF_RRSC_HE_MSC5,
495 RTW89_MAC_BF_RRSC_HE_MSC6,
496 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
497 RTW89_MAC_BF_RRSC_MAX = 32
498 };
499
500 #define RTW89_R32_EA 0xEAEAEAEA
501 #define RTW89_R32_DEAD 0xDEADBEEF
502 #define MAC_REG_POOL_COUNT 10
503 #define ACCESS_CMAC(_addr) \
504 ({typeof(_addr) __addr = (_addr); \
505 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
506 #define RTW89_MAC_AX_BAND_REG_OFFSET 0x2000
507 #define RTW89_MAC_BE_BAND_REG_OFFSET 0x4000
508
509 #define PTCL_IDLE_POLL_CNT 10000
510 #define SW_CVR_DUR_US 8
511 #define SW_CVR_CNT 8
512
513 #define DLE_BOUND_UNIT (8 * 1024)
514 #define DLE_WAIT_CNT 2000
515 #define TRXCFG_WAIT_CNT 2000
516
517 #define RTW89_WDE_PG_64 64
518 #define RTW89_WDE_PG_128 128
519 #define RTW89_WDE_PG_256 256
520
521 #define S_AX_WDE_PAGE_SEL_64 0
522 #define S_AX_WDE_PAGE_SEL_128 1
523 #define S_AX_WDE_PAGE_SEL_256 2
524
525 #define RTW89_PLE_PG_64 64
526 #define RTW89_PLE_PG_128 128
527 #define RTW89_PLE_PG_256 256
528
529 #define S_AX_PLE_PAGE_SEL_64 0
530 #define S_AX_PLE_PAGE_SEL_128 1
531 #define S_AX_PLE_PAGE_SEL_256 2
532
533 #define B_CMAC0_MGQ_NORMAL BIT(2)
534 #define B_CMAC0_MGQ_NO_PWRSAV BIT(3)
535 #define B_CMAC0_CPUMGQ BIT(4)
536 #define B_CMAC1_MGQ_NORMAL BIT(10)
537 #define B_CMAC1_MGQ_NO_PWRSAV BIT(11)
538 #define B_CMAC1_CPUMGQ BIT(12)
539
540 #define B_CMAC0_MGQ_NORMAL_BE BIT(2)
541 #define B_CMAC1_MGQ_NORMAL_BE BIT(30)
542
543 #define QEMP_ACQ_GRP_MACID_NUM 8
544 #define QEMP_ACQ_GRP_QSEL_SH 4
545 #define QEMP_ACQ_GRP_QSEL_MASK 0xF
546
547 #define SDIO_LOCAL_BASE_ADDR 0x80000000
548
549 #define PWR_CMD_WRITE 0
550 #define PWR_CMD_POLL 1
551 #define PWR_CMD_DELAY 2
552 #define PWR_CMD_END 3
553
554 #define PWR_INTF_MSK_SDIO BIT(0)
555 #define PWR_INTF_MSK_USB BIT(1)
556 #define PWR_INTF_MSK_PCIE BIT(2)
557 #define PWR_INTF_MSK_ALL 0x7
558
559 #define PWR_BASE_MAC 0
560 #define PWR_BASE_USB 1
561 #define PWR_BASE_PCIE 2
562 #define PWR_BASE_SDIO 3
563
564 #define PWR_CV_MSK_A BIT(0)
565 #define PWR_CV_MSK_B BIT(1)
566 #define PWR_CV_MSK_C BIT(2)
567 #define PWR_CV_MSK_D BIT(3)
568 #define PWR_CV_MSK_E BIT(4)
569 #define PWR_CV_MSK_F BIT(5)
570 #define PWR_CV_MSK_G BIT(6)
571 #define PWR_CV_MSK_TEST BIT(7)
572 #define PWR_CV_MSK_ALL 0xFF
573
574 #define PWR_DELAY_US 0
575 #define PWR_DELAY_MS 1
576
577 /* STA scheduler */
578 #define SS_MACID_SH 8
579 #define SS_TX_LEN_MSK 0x1FFFFF
580 #define SS_CTRL1_R_TX_LEN 5
581 #define SS_CTRL1_R_NEXT_LINK 20
582 #define SS_LINK_SIZE 256
583
584 /* MAC debug port */
585 #define TMAC_DBG_SEL_C0 0xA5
586 #define RMAC_DBG_SEL_C0 0xA6
587 #define TRXPTCL_DBG_SEL_C0 0xA7
588 #define TMAC_DBG_SEL_C1 0xB5
589 #define RMAC_DBG_SEL_C1 0xB6
590 #define TRXPTCL_DBG_SEL_C1 0xB7
591 #define FW_PROG_CNTR_DBG_SEL 0xF2
592 #define PCIE_TXDMA_DBG_SEL 0x30
593 #define PCIE_RXDMA_DBG_SEL 0x31
594 #define PCIE_CVT_DBG_SEL 0x32
595 #define PCIE_CXPL_DBG_SEL 0x33
596 #define PCIE_IO_DBG_SEL 0x37
597 #define PCIE_MISC_DBG_SEL 0x38
598 #define PCIE_MISC2_DBG_SEL 0x00
599 #define MAC_DBG_SEL 1
600 #define RMAC_CMAC_DBG_SEL 1
601
602 /* TRXPTCL dbg port sel */
603 #define TRXPTRL_DBG_SEL_TMAC 0
604 #define TRXPTRL_DBG_SEL_RMAC 1
605
606 struct rtw89_cpuio_ctrl {
607 u16 pkt_num;
608 u16 start_pktid;
609 u16 end_pktid;
610 u8 cmd_type;
611 u8 macid;
612 u8 src_pid;
613 u8 src_qid;
614 u8 dst_pid;
615 u8 dst_qid;
616 u16 pktid;
617 };
618
619 struct rtw89_mac_dbg_port_info {
620 u32 sel_addr;
621 u8 sel_byte;
622 u32 sel_msk;
623 u32 srt;
624 u32 end;
625 u32 rd_addr;
626 u8 rd_byte;
627 u32 rd_msk;
628 };
629
630 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
631 #define QLNKTBL_ADDR_INFO_SEL_0 0
632 #define QLNKTBL_ADDR_INFO_SEL_1 1
633 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
634 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
635
636 struct rtw89_mac_dle_dfi_ctrl {
637 enum rtw89_mac_dle_ctrl_type type;
638 u32 target;
639 u32 addr;
640 u32 out_data;
641 };
642
643 struct rtw89_mac_dle_dfi_quota {
644 enum rtw89_mac_dle_ctrl_type dle_type;
645 u32 qtaid;
646 u16 rsv_pgnum;
647 u16 use_pgnum;
648 };
649
650 struct rtw89_mac_dle_dfi_qempty {
651 enum rtw89_mac_dle_ctrl_type dle_type;
652 u32 grpsel;
653 u32 qempty;
654 };
655
656 enum rtw89_mac_dle_rsvd_qt_type {
657 DLE_RSVD_QT_MPDU_INFO,
658 DLE_RSVD_QT_B0_CSI,
659 DLE_RSVD_QT_B1_CSI,
660 DLE_RSVD_QT_B0_LMR,
661 DLE_RSVD_QT_B1_LMR,
662 DLE_RSVD_QT_B0_FTM,
663 DLE_RSVD_QT_B1_FTM,
664 };
665
666 struct rtw89_mac_dle_rsvd_qt_cfg {
667 u16 pktid;
668 u16 pg_num;
669 u32 size;
670 };
671
672 enum rtw89_mac_error_scenario {
673 RTW89_RXI300_ERROR = 1,
674 RTW89_WCPU_CPU_EXCEPTION = 2,
675 RTW89_WCPU_ASSERTION = 3,
676 };
677
678 #define RTW89_ERROR_SCENARIO(__err) ((__err) >> 28)
679
680 /* Define DBG and recovery enum */
681 enum mac_ax_err_info {
682 /* Get error info */
683
684 /* L0 */
685 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
686 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
687 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
688 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
689
690 /* L1 */
691 MAC_AX_ERR_L1_PREERR_DMAC = 0x999,
692 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
693 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
694 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
695 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
696 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
697
698 /* L2 */
699 /* address hole (master) */
700 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
701 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
702 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
703 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
704 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
705 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
706 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
707 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
708
709 /* AHB bridge timeout (master) */
710 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
711 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
712 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
713 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
714 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
715 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
716 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
717 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
718
719 /* APB_SA bridge timeout (master + slave) */
720 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
721 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
722 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
723 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
724 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
725 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
726 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
727 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
728 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
729 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
730 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
731 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
732 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
733 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
734 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
735 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
736 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
737 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
738 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
739 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
740 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
741 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
742 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
743 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
744 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
745 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
746 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
747 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
748 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
749 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
750 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
751 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
752 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
753 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
754 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
755 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
756 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
757 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
758 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
759 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
760 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
761 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
762 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
763 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
764 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
765 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
766 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
767 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
768 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
769 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
770 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
771 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
772 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
773 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
774 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
775 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
776 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
777 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
778 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
779 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
780 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
781 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
782 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
783 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
784 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
785 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
786 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
787 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
788 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
789 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
790 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
791 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
792 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
793 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
794 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
795 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
796 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
797 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
798 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
799 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
800 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
801 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
802 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
803 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
804 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
805 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
806 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
807
808 /* APB_BBRF bridge timeout (master) */
809 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
810 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
811 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
812 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
813 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
814 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
815 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
816 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
817 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
818 MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT = 0x2599,
819 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
820 MAC_AX_ERR_ASSERTION = 0x4000,
821 MAC_AX_ERR_RXI300 = 0x5000,
822 MAC_AX_GET_ERR_MAX,
823 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
824
825 /* set error info */
826 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
827 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
828 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
829 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
830 MAC_AX_ERR_L1_RESET_START_DMAC = 0x000A,
831 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
832 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
833 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
834 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
835 MAC_AX_SET_ERR_MAX,
836 };
837
838 struct rtw89_mac_size_set {
839 const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;
840 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c0;
841 const struct rtw89_hfc_prec_cfg hfc_prec_cfg_c2;
842 const struct rtw89_dle_size wde_size0;
843 const struct rtw89_dle_size wde_size0_v1;
844 const struct rtw89_dle_size wde_size4;
845 const struct rtw89_dle_size wde_size4_v1;
846 const struct rtw89_dle_size wde_size6;
847 const struct rtw89_dle_size wde_size7;
848 const struct rtw89_dle_size wde_size9;
849 const struct rtw89_dle_size wde_size18;
850 const struct rtw89_dle_size wde_size19;
851 const struct rtw89_dle_size ple_size0;
852 const struct rtw89_dle_size ple_size0_v1;
853 const struct rtw89_dle_size ple_size3_v1;
854 const struct rtw89_dle_size ple_size4;
855 const struct rtw89_dle_size ple_size6;
856 const struct rtw89_dle_size ple_size8;
857 const struct rtw89_dle_size ple_size18;
858 const struct rtw89_dle_size ple_size19;
859 const struct rtw89_wde_quota wde_qt0;
860 const struct rtw89_wde_quota wde_qt0_v1;
861 const struct rtw89_wde_quota wde_qt4;
862 const struct rtw89_wde_quota wde_qt6;
863 const struct rtw89_wde_quota wde_qt7;
864 const struct rtw89_wde_quota wde_qt17;
865 const struct rtw89_wde_quota wde_qt18;
866 const struct rtw89_ple_quota ple_qt0;
867 const struct rtw89_ple_quota ple_qt1;
868 const struct rtw89_ple_quota ple_qt4;
869 const struct rtw89_ple_quota ple_qt5;
870 const struct rtw89_ple_quota ple_qt9;
871 const struct rtw89_ple_quota ple_qt13;
872 const struct rtw89_ple_quota ple_qt18;
873 const struct rtw89_ple_quota ple_qt44;
874 const struct rtw89_ple_quota ple_qt45;
875 const struct rtw89_ple_quota ple_qt46;
876 const struct rtw89_ple_quota ple_qt47;
877 const struct rtw89_ple_quota ple_qt58;
878 const struct rtw89_ple_quota ple_qt_52a_wow;
879 const struct rtw89_ple_quota ple_qt_52b_wow;
880 const struct rtw89_ple_quota ple_qt_51b_wow;
881 const struct rtw89_rsvd_quota ple_rsvd_qt0;
882 const struct rtw89_rsvd_quota ple_rsvd_qt1;
883 const struct rtw89_dle_rsvd_size rsvd0_size0;
884 const struct rtw89_dle_rsvd_size rsvd1_size0;
885 };
886
887 extern const struct rtw89_mac_size_set rtw89_mac_size;
888
889 struct rtw89_mac_gen_def {
890 u32 band1_offset;
891 u32 filter_model_addr;
892 u32 indir_access_addr;
893 const u32 *mem_base_addrs;
894 u32 rx_fltr;
895 const struct rtw89_port_reg *port_base;
896 u32 agg_len_ht;
897
898 struct rtw89_reg_def muedca_ctrl;
899 struct rtw89_reg_def bfee_ctrl;
900
901 int (*check_mac_en)(struct rtw89_dev *rtwdev, u8 band,
902 enum rtw89_mac_hwmod_sel sel);
903 int (*sys_init)(struct rtw89_dev *rtwdev);
904 int (*trx_init)(struct rtw89_dev *rtwdev);
905 void (*hci_func_en)(struct rtw89_dev *rtwdev);
906 void (*dmac_func_pre_en)(struct rtw89_dev *rtwdev);
907 void (*dle_func_en)(struct rtw89_dev *rtwdev, bool enable);
908 void (*dle_clk_en)(struct rtw89_dev *rtwdev, bool enable);
909 void (*bf_assoc)(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
910 struct ieee80211_sta *sta);
911
912 int (*typ_fltr_opt)(struct rtw89_dev *rtwdev,
913 enum rtw89_machdr_frame_type type,
914 enum rtw89_mac_fwd_target fwd_target,
915 u8 mac_idx);
916
917 int (*dle_mix_cfg)(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg);
918 int (*chk_dle_rdy)(struct rtw89_dev *rtwdev, bool wde_or_ple);
919 int (*dle_buf_req)(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id);
920 void (*hfc_func_en)(struct rtw89_dev *rtwdev, bool en, bool h2c_en);
921 void (*hfc_h2c_cfg)(struct rtw89_dev *rtwdev);
922 void (*hfc_mix_cfg)(struct rtw89_dev *rtwdev);
923 void (*hfc_get_mix_info)(struct rtw89_dev *rtwdev);
924 void (*wde_quota_cfg)(struct rtw89_dev *rtwdev,
925 const struct rtw89_wde_quota *min_cfg,
926 const struct rtw89_wde_quota *max_cfg,
927 u16 ext_wde_min_qt_wcpu);
928 void (*ple_quota_cfg)(struct rtw89_dev *rtwdev,
929 const struct rtw89_ple_quota *min_cfg,
930 const struct rtw89_ple_quota *max_cfg);
931 int (*set_cpuio)(struct rtw89_dev *rtwdev,
932 struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
933
934 void (*disable_cpu)(struct rtw89_dev *rtwdev);
935 int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
936 bool dlfw, bool include_bb);
937 u8 (*fwdl_get_status)(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
938 int (*fwdl_check_path_ready)(struct rtw89_dev *rtwdev, bool h2c_or_fwdl);
939 int (*parse_efuse_map)(struct rtw89_dev *rtwdev);
940 int (*parse_phycap_map)(struct rtw89_dev *rtwdev);
941 int (*cnv_efuse_state)(struct rtw89_dev *rtwdev, bool idle);
942
943 bool (*get_txpwr_cr)(struct rtw89_dev *rtwdev,
944 enum rtw89_phy_idx phy_idx,
945 u32 reg_base, u32 *cr);
946
947 int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
948 int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
949
950 void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
951 void (*dump_err_status)(struct rtw89_dev *rtwdev,
952 enum mac_ax_err_info err);
953
954 bool (*is_txq_empty)(struct rtw89_dev *rtwdev);
955 };
956
957 extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax;
958 extern const struct rtw89_mac_gen_def rtw89_mac_gen_be;
959
960 static inline
rtw89_mac_reg_by_idx(struct rtw89_dev * rtwdev,u32 reg_base,u8 band)961 u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band)
962 {
963 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
964
965 return band == 0 ? reg_base : (reg_base + mac->band1_offset);
966 }
967
968 static inline
rtw89_mac_reg_by_port(struct rtw89_dev * rtwdev,u32 base,u8 port,u8 mac_idx)969 u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx)
970 {
971 return rtw89_mac_reg_by_idx(rtwdev, base + port * 0x40, mac_idx);
972 }
973
974 static inline u32
rtw89_read32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base)975 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base)
976 {
977 u32 reg;
978
979 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
980 return rtw89_read32(rtwdev, reg);
981 }
982
983 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask)984 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
985 u32 base, u32 mask)
986 {
987 u32 reg;
988
989 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
990 return rtw89_read32_mask(rtwdev, reg, mask);
991 }
992
993 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 data)994 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
995 u32 data)
996 {
997 u32 reg;
998
999 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1000 rtw89_write32(rtwdev, reg, data);
1001 }
1002
1003 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u32 data)1004 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1005 u32 base, u32 mask, u32 data)
1006 {
1007 u32 reg;
1008
1009 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1010 rtw89_write32_mask(rtwdev, reg, mask, data);
1011 }
1012
1013 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u16 data)1014 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1015 u32 base, u32 mask, u16 data)
1016 {
1017 u32 reg;
1018
1019 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1020 rtw89_write16_mask(rtwdev, reg, mask, data);
1021 }
1022
1023 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)1024 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1025 u32 base, u32 bit)
1026 {
1027 u32 reg;
1028
1029 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1030 rtw89_write32_clr(rtwdev, reg, bit);
1031 }
1032
1033 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u16 bit)1034 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1035 u32 base, u16 bit)
1036 {
1037 u32 reg;
1038
1039 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1040 rtw89_write16_clr(rtwdev, reg, bit);
1041 }
1042
1043 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)1044 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1045 u32 base, u32 bit)
1046 {
1047 u32 reg;
1048
1049 reg = rtw89_mac_reg_by_port(rtwdev, base, rtwvif->port, rtwvif->mac_idx);
1050 rtw89_write32_set(rtwdev, reg, bit);
1051 }
1052
1053 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
1054 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb);
1055 int rtw89_mac_init(struct rtw89_dev *rtwdev);
1056 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1057 enum rtw89_qta_mode ext_mode);
1058 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en);
1059 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1060 enum rtw89_qta_mode mode);
1061 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1062 static inline
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 band,enum rtw89_mac_hwmod_sel sel)1063 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
1064 enum rtw89_mac_hwmod_sel sel)
1065 {
1066 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1067
1068 return mac->check_mac_en(rtwdev, band, sel);
1069 }
1070
1071 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
1072 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
1073 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl);
1074 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
1075 struct rtw89_mac_dle_dfi_quota *quota);
1076 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev);
1077 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
1078 struct rtw89_mac_dle_dfi_qempty *qempty);
1079 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
1080 enum mac_ax_err_info err);
1081 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
1082 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1083 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
1084 struct rtw89_vif *rtwvif,
1085 struct rtw89_vif *rtwvif_src,
1086 u16 offset_tu);
1087 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
1088 u64 *tsf);
1089 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
1090 struct ieee80211_vif *vif);
1091 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1092 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en);
1093 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
1094 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
1095 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
1096
rtw89_chip_enable_bb_rf(struct rtw89_dev * rtwdev)1097 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
1098 {
1099 const struct rtw89_chip_info *chip = rtwdev->chip;
1100
1101 return chip->ops->enable_bb_rf(rtwdev);
1102 }
1103
rtw89_chip_disable_bb_rf(struct rtw89_dev * rtwdev)1104 static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
1105 {
1106 const struct rtw89_chip_info *chip = rtwdev->chip;
1107
1108 return chip->ops->disable_bb_rf(rtwdev);
1109 }
1110
rtw89_chip_reset_bb_rf(struct rtw89_dev * rtwdev)1111 static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev)
1112 {
1113 int ret;
1114
1115 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1116 return 0;
1117
1118 ret = rtw89_chip_disable_bb_rf(rtwdev);
1119 if (ret)
1120 return ret;
1121 ret = rtw89_chip_enable_bb_rf(rtwdev);
1122 if (ret)
1123 return ret;
1124
1125 return 0;
1126 }
1127
1128 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
1129 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
1130 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
1131 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1132 u32 len, u8 class, u8 func);
1133 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
1134 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
1135 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1136 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
1137 u32 *tx_en, enum rtw89_sch_tx_sel sel);
1138 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1139 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
1140 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable);
1141 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
1142 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1143 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
1144 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
1145 const struct rtw89_mac_ax_coex *coex);
1146 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
1147 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1148 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
1149 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
1150 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
1151 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band);
1152 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
1153 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
1154 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
1155 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
1156 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl);
1157 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
1158 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev);
1159
1160 static inline
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1161 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1162 struct ieee80211_sta *sta)
1163 {
1164 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1165
1166 if (mac->bf_assoc)
1167 mac->bf_assoc(rtwdev, vif, sta);
1168 }
1169
1170 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1171 struct ieee80211_sta *sta);
1172 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1173 struct ieee80211_bss_conf *conf);
1174 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
1175 struct ieee80211_sta *sta, bool disconnect);
1176 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
1177 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en);
1178 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1179 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1180 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
1181 struct rtw89_vif *rtwvif, bool en);
1182 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause);
1183
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)1184 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
1185 {
1186 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
1187 return;
1188
1189 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
1190 return;
1191
1192 _rtw89_mac_bf_monitor_track(rtwdev);
1193 }
1194
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)1195 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
1196 enum rtw89_phy_idx phy_idx,
1197 u32 reg_base, u32 *val)
1198 {
1199 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1200 u32 cr;
1201
1202 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1203 return -EINVAL;
1204
1205 *val = rtw89_read32(rtwdev, cr);
1206 return 0;
1207 }
1208
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)1209 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
1210 enum rtw89_phy_idx phy_idx,
1211 u32 reg_base, u32 val)
1212 {
1213 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1214 u32 cr;
1215
1216 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1217 return -EINVAL;
1218
1219 rtw89_write32(rtwdev, cr, val);
1220 return 0;
1221 }
1222
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)1223 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
1224 enum rtw89_phy_idx phy_idx,
1225 u32 reg_base, u32 mask, u32 val)
1226 {
1227 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1228 u32 cr;
1229
1230 if (!mac->get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
1231 return -EINVAL;
1232
1233 rtw89_write32_mask(rtwdev, cr, mask, val);
1234 return 0;
1235 }
1236
rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev * rtwdev,bool enable)1237 static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev,
1238 bool enable)
1239 {
1240 const struct rtw89_chip_info *chip = rtwdev->chip;
1241
1242 if (enable)
1243 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1244 B_AX_HCI_TXDMA_EN);
1245 else
1246 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1247 B_AX_HCI_TXDMA_EN);
1248 }
1249
rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev * rtwdev,bool enable)1250 static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev,
1251 bool enable)
1252 {
1253 const struct rtw89_chip_info *chip = rtwdev->chip;
1254
1255 if (enable)
1256 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1257 B_AX_HCI_RXDMA_EN);
1258 else
1259 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1260 B_AX_HCI_RXDMA_EN);
1261 }
1262
rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev * rtwdev,bool enable)1263 static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev,
1264 bool enable)
1265 {
1266 const struct rtw89_chip_info *chip = rtwdev->chip;
1267
1268 if (enable)
1269 rtw89_write32_set(rtwdev, chip->hci_func_en_addr,
1270 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1271 else
1272 rtw89_write32_clr(rtwdev, chip->hci_func_en_addr,
1273 B_AX_HCI_TXDMA_EN | B_AX_HCI_RXDMA_EN);
1274 }
1275
rtw89_mac_get_power_state(struct rtw89_dev * rtwdev)1276 static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev)
1277 {
1278 u32 val;
1279
1280 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE,
1281 B_AX_WLMAC_PWR_STE_MASK);
1282
1283 return !!val;
1284 }
1285
1286 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1287 bool resume, u32 tx_time);
1288 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
1289 u32 *tx_time);
1290 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
1291 struct rtw89_sta *rtwsta,
1292 bool resume, u8 tx_retry);
1293 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
1294 struct rtw89_sta *rtwsta, u8 *tx_retry);
1295
1296 enum rtw89_mac_xtal_si_offset {
1297 XTAL0 = 0x0,
1298 XTAL3 = 0x3,
1299 XTAL_SI_XTAL_SC_XI = 0x04,
1300 #define XTAL_SC_XI_MASK GENMASK(7, 0)
1301 XTAL_SI_XTAL_SC_XO = 0x05,
1302 #define XTAL_SC_XO_MASK GENMASK(7, 0)
1303 XTAL_SI_XREF_MODE = 0x0B,
1304 XTAL_SI_PWR_CUT = 0x10,
1305 #define XTAL_SI_SMALL_PWR_CUT BIT(0)
1306 #define XTAL_SI_BIG_PWR_CUT BIT(1)
1307 XTAL_SI_XTAL_DRV = 0x15,
1308 #define XTAL_SI_DRV_LATCH BIT(4)
1309 XTAL_SI_XTAL_XMD_2 = 0x24,
1310 #define XTAL_SI_LDO_LPS GENMASK(6, 4)
1311 XTAL_SI_XTAL_XMD_4 = 0x26,
1312 #define XTAL_SI_LPS_CAP GENMASK(3, 0)
1313 XTAL_SI_XREF_RF1 = 0x2D,
1314 XTAL_SI_XREF_RF2 = 0x2E,
1315 XTAL_SI_CV = 0x41,
1316 #define XTAL_SI_ACV_MASK GENMASK(3, 0)
1317 XTAL_SI_LOW_ADDR = 0x62,
1318 #define XTAL_SI_LOW_ADDR_MASK GENMASK(7, 0)
1319 XTAL_SI_CTRL = 0x63,
1320 #define XTAL_SI_MODE_SEL_MASK GENMASK(7, 6)
1321 #define XTAL_SI_RDY BIT(5)
1322 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
1323 XTAL_SI_READ_VAL = 0x7A,
1324 XTAL_SI_WL_RFC_S0 = 0x80,
1325 #define XTAL_SI_RF00S_EN GENMASK(2, 0)
1326 #define XTAL_SI_RF00 BIT(0)
1327 XTAL_SI_WL_RFC_S1 = 0x81,
1328 #define XTAL_SI_RF10S_EN GENMASK(2, 0)
1329 #define XTAL_SI_RF10 BIT(0)
1330 XTAL_SI_ANAPAR_WL = 0x90,
1331 #define XTAL_SI_SRAM2RFC BIT(7)
1332 #define XTAL_SI_GND_SHDN_WL BIT(6)
1333 #define XTAL_SI_SHDN_WL BIT(5)
1334 #define XTAL_SI_RFC2RF BIT(4)
1335 #define XTAL_SI_OFF_EI BIT(3)
1336 #define XTAL_SI_OFF_WEI BIT(2)
1337 #define XTAL_SI_PON_EI BIT(1)
1338 #define XTAL_SI_PON_WEI BIT(0)
1339 XTAL_SI_SRAM_CTRL = 0xA1,
1340 #define XTAL_SI_SRAM_DIS BIT(1)
1341 #define FULL_BIT_MASK GENMASK(7, 0)
1342 XTAL_SI_PLL = 0xE0,
1343 XTAL_SI_PLL_1 = 0xE1,
1344 };
1345
1346 static inline
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)1347 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
1348 {
1349 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1350
1351 return mac->write_xtal_si(rtwdev, offset, val, mask);
1352 }
1353
1354 static inline
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)1355 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
1356 {
1357 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1358
1359 return mac->read_xtal_si(rtwdev, offset, val);
1360 }
1361
1362 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
1363 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
1364 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
1365 enum rtw89_mac_idx band);
1366 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
1367 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
1368 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1369 enum rtw89_mac_dle_rsvd_qt_type type,
1370 struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
1371
1372 #endif
1373