1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../pci.h"
7 #include "../base.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "dm.h"
12 #include "hw.h"
13 #include "sw.h"
14 #include "trx.h"
15 #include "led.h"
16
17 #include <linux/module.h>
18
rtl92d_init_aspm_vars(struct ieee80211_hw * hw)19 static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
20 {
21 struct rtl_priv *rtlpriv = rtl_priv(hw);
22 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
23
24 /*
25 * ASPM PS mode.
26 * 0 - Disable ASPM,
27 * 1 - Enable ASPM without Clock Req,
28 * 2 - Enable ASPM with Clock Req,
29 * 3 - Alwyas Enable ASPM with Clock Req,
30 * 4 - Always Enable ASPM without Clock Req.
31 * set defult to RTL8192CE:3 RTL8192E:2
32 * */
33 rtlpci->const_pci_aspm = 3;
34
35 /*Setting for PCI-E device */
36 rtlpci->const_devicepci_aspm_setting = 0x03;
37
38 /*Setting for PCI-E bridge */
39 rtlpci->const_hostpci_aspm_setting = 0x02;
40
41 /*
42 * In Hw/Sw Radio Off situation.
43 * 0 - Default,
44 * 1 - From ASPM setting without low Mac Pwr,
45 * 2 - From ASPM setting with low Mac Pwr,
46 * 3 - Bus D3
47 * set default to RTL8192CE:0 RTL8192SE:2
48 */
49 rtlpci->const_hwsw_rfoff_d3 = 0;
50
51 /*
52 * This setting works for those device with
53 * backdoor ASPM setting such as EPHY setting.
54 * 0 - Not support ASPM,
55 * 1 - Support ASPM,
56 * 2 - According to chipset.
57 */
58 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
59 }
60
rtl92d_init_sw_vars(struct ieee80211_hw * hw)61 static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
62 {
63 int err;
64 u8 tid;
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
67 char *fw_name = "rtlwifi/rtl8192defw.bin";
68
69 rtlpriv->dm.dm_initialgain_enable = true;
70 rtlpriv->dm.dm_flag = 0;
71 rtlpriv->dm.disable_framebursting = false;
72 rtlpriv->dm.thermalvalue = 0;
73 rtlpriv->dm.useramask = true;
74
75 /* dual mac */
76 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
77 rtlpriv->phy.current_channel = 36;
78 else
79 rtlpriv->phy.current_channel = 1;
80
81 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
82 rtlpriv->rtlhal.disable_amsdu_8k = true;
83 /* No long RX - reduce fragmentation */
84 rtlpci->rxbuffersize = 4096;
85 }
86
87 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
88
89 rtlpci->receive_config = (
90 RCR_APPFCS
91 | RCR_AMF
92 | RCR_ADF
93 | RCR_APP_MIC
94 | RCR_APP_ICV
95 | RCR_AICV
96 | RCR_ACRC32
97 | RCR_AB
98 | RCR_AM
99 | RCR_APM
100 | RCR_APP_PHYST_RXFF
101 | RCR_HTC_LOC_CTRL
102 );
103
104 rtlpci->irq_mask[0] = (u32) (
105 IMR_ROK
106 | IMR_VODOK
107 | IMR_VIDOK
108 | IMR_BEDOK
109 | IMR_BKDOK
110 | IMR_MGNTDOK
111 | IMR_HIGHDOK
112 | IMR_BDOK
113 | IMR_RDU
114 | IMR_RXFOVW
115 );
116
117 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
118
119 /* for LPS & IPS */
120 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
121 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
122 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
123 if (!rtlpriv->psc.inactiveps)
124 pr_info("Power Save off (module option)\n");
125 if (!rtlpriv->psc.fwctrl_lps)
126 pr_info("FW Power Save off (module option)\n");
127 rtlpriv->psc.reg_fwctrl_lps = 3;
128 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
129 /* for ASPM, you can close aspm through
130 * set const_support_pciaspm = 0 */
131 rtl92d_init_aspm_vars(hw);
132
133 if (rtlpriv->psc.reg_fwctrl_lps == 1)
134 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
135 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
136 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
137 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
138 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
139
140 /* for early mode */
141 rtlpriv->rtlhal.earlymode_enable = false;
142 for (tid = 0; tid < 8; tid++)
143 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
144
145 /* for firmware buf */
146 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
147 if (!rtlpriv->rtlhal.pfirmware) {
148 pr_err("Can't alloc buffer for fw\n");
149 return 1;
150 }
151
152 rtlpriv->max_fw_size = 0x8000;
153 pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
154 pr_info("Loading firmware file %s\n", fw_name);
155
156 /* request fw */
157 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
158 rtlpriv->io.dev, GFP_KERNEL, hw,
159 rtl_fw_cb);
160 if (err) {
161 pr_err("Failed to request firmware!\n");
162 vfree(rtlpriv->rtlhal.pfirmware);
163 rtlpriv->rtlhal.pfirmware = NULL;
164 return 1;
165 }
166
167 return 0;
168 }
169
rtl92d_deinit_sw_vars(struct ieee80211_hw * hw)170 static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
171 {
172 struct rtl_priv *rtlpriv = rtl_priv(hw);
173 u8 tid;
174
175 if (rtlpriv->rtlhal.pfirmware) {
176 vfree(rtlpriv->rtlhal.pfirmware);
177 rtlpriv->rtlhal.pfirmware = NULL;
178 }
179 for (tid = 0; tid < 8; tid++)
180 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
181 }
182
183 static struct rtl_hal_ops rtl8192de_hal_ops = {
184 .init_sw_vars = rtl92d_init_sw_vars,
185 .deinit_sw_vars = rtl92d_deinit_sw_vars,
186 .read_eeprom_info = rtl92de_read_eeprom_info,
187 .interrupt_recognized = rtl92de_interrupt_recognized,
188 .hw_init = rtl92de_hw_init,
189 .hw_disable = rtl92de_card_disable,
190 .hw_suspend = rtl92de_suspend,
191 .hw_resume = rtl92de_resume,
192 .enable_interrupt = rtl92de_enable_interrupt,
193 .disable_interrupt = rtl92de_disable_interrupt,
194 .set_network_type = rtl92de_set_network_type,
195 .set_chk_bssid = rtl92de_set_check_bssid,
196 .set_qos = rtl92de_set_qos,
197 .set_bcn_reg = rtl92de_set_beacon_related_registers,
198 .set_bcn_intv = rtl92de_set_beacon_interval,
199 .update_interrupt_mask = rtl92de_update_interrupt_mask,
200 .get_hw_reg = rtl92de_get_hw_reg,
201 .set_hw_reg = rtl92de_set_hw_reg,
202 .update_rate_tbl = rtl92de_update_hal_rate_tbl,
203 .fill_tx_desc = rtl92de_tx_fill_desc,
204 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
205 .query_rx_desc = rtl92de_rx_query_desc,
206 .set_channel_access = rtl92de_update_channel_access_setting,
207 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
208 .set_bw_mode = rtl92d_phy_set_bw_mode,
209 .switch_channel = rtl92d_phy_sw_chnl,
210 .dm_watchdog = rtl92d_dm_watchdog,
211 .scan_operation_backup = rtl_phy_scan_operation_backup,
212 .set_rf_power_state = rtl92d_phy_set_rf_power_state,
213 .led_control = rtl92de_led_control,
214 .set_desc = rtl92de_set_desc,
215 .get_desc = rtl92de_get_desc,
216 .is_tx_desc_closed = rtl92de_is_tx_desc_closed,
217 .tx_polling = rtl92de_tx_polling,
218 .enable_hw_sec = rtl92de_enable_hw_security_config,
219 .set_key = rtl92de_set_key,
220 .get_bbreg = rtl92d_phy_query_bb_reg,
221 .set_bbreg = rtl92d_phy_set_bb_reg,
222 .get_rfreg = rtl92d_phy_query_rf_reg,
223 .set_rfreg = rtl92d_phy_set_rf_reg,
224 .linked_set_reg = rtl92d_linked_set_reg,
225 .get_btc_status = rtl_btc_status_false,
226 };
227
228 static struct rtl_mod_params rtl92de_mod_params = {
229 .sw_crypto = false,
230 .inactiveps = true,
231 .swctrl_lps = true,
232 .fwctrl_lps = false,
233 .aspm_support = 1,
234 .debug_level = 0,
235 .debug_mask = 0,
236 };
237
238 static const struct rtl_hal_cfg rtl92de_hal_cfg = {
239 .bar_id = 2,
240 .write_readback = true,
241 .name = "rtl8192de",
242 .ops = &rtl8192de_hal_ops,
243 .mod_params = &rtl92de_mod_params,
244
245 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
246 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
247 .maps[SYS_CLK] = REG_SYS_CLKR,
248 .maps[MAC_RCR_AM] = RCR_AM,
249 .maps[MAC_RCR_AB] = RCR_AB,
250 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
251 .maps[MAC_RCR_ACF] = RCR_ACF,
252 .maps[MAC_RCR_AAP] = RCR_AAP,
253
254 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
255 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
256 .maps[EFUSE_CLK] = 0, /* just for 92se */
257 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
258 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
259 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
260 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
261 .maps[EFUSE_ANA8M] = 0, /* just for 92se */
262 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
263 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
264 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
265
266 .maps[RWCAM] = REG_CAMCMD,
267 .maps[WCAMI] = REG_CAMWRITE,
268 .maps[RCAMO] = REG_CAMREAD,
269 .maps[CAMDBG] = REG_CAMDBG,
270 .maps[SECR] = REG_SECCFG,
271 .maps[SEC_CAM_NONE] = CAM_NONE,
272 .maps[SEC_CAM_WEP40] = CAM_WEP40,
273 .maps[SEC_CAM_TKIP] = CAM_TKIP,
274 .maps[SEC_CAM_AES] = CAM_AES,
275 .maps[SEC_CAM_WEP104] = CAM_WEP104,
276
277 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
278 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
279 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
280 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
281 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
282 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
283 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
284 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
285 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
286 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
287 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
288 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
289 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
290 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
291 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
292 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
293
294 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
295 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
296 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
297 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
298 .maps[RTL_IMR_RDU] = IMR_RDU,
299 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
300 .maps[RTL_IMR_BDOK] = IMR_BDOK,
301 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
302 .maps[RTL_IMR_TBDER] = IMR_TBDER,
303 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
304 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
305 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
306 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
307 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
308 .maps[RTL_IMR_VODOK] = IMR_VODOK,
309 .maps[RTL_IMR_ROK] = IMR_ROK,
310 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
311
312 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
313 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
314 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
315 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
316 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
317 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
318 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
319 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
320 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
321 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
322 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
323 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
324
325 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
326 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
327 };
328
329 static const struct pci_device_id rtl92de_pci_ids[] = {
330 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
331 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
332 {},
333 };
334
335 MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
336
337 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
338 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
339 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
340 MODULE_LICENSE("GPL");
341 MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
342 MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
343
344 module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
345 module_param_named(debug_level, rtl92de_mod_params.debug_level, int, 0644);
346 module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
347 module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
348 module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
349 module_param_named(aspm, rtl92de_mod_params.aspm_support, int, 0444);
350 module_param_named(debug_mask, rtl92de_mod_params.debug_mask, ullong, 0644);
351 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
352 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
353 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
354 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
355 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
356 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
357 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
358
359 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
360
361 static struct pci_driver rtl92de_driver = {
362 .name = KBUILD_MODNAME,
363 .id_table = rtl92de_pci_ids,
364 .probe = rtl_pci_probe,
365 .remove = rtl_pci_disconnect,
366 .driver.pm = &rtlwifi_pm_ops,
367 };
368
369 /* add global spin lock to solve the problem that
370 * Dul mac register operation on the same time */
371 DEFINE_SPINLOCK(globalmutex_power);
372 DEFINE_SPINLOCK(globalmutex_for_fwdownload);
373 DEFINE_SPINLOCK(globalmutex_for_power_and_efuse);
374
rtl92de_module_init(void)375 static int __init rtl92de_module_init(void)
376 {
377 int ret = 0;
378
379 ret = pci_register_driver(&rtl92de_driver);
380 if (ret)
381 WARN_ONCE(true, "rtl8192de: No device found\n");
382 return ret;
383 }
384
rtl92de_module_exit(void)385 static void __exit rtl92de_module_exit(void)
386 {
387 pci_unregister_driver(&rtl92de_driver);
388 }
389
390 module_init(rtl92de_module_init);
391 module_exit(rtl92de_module_exit);
392