1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/crash_dump.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/mlx5/fs.h>
47 #include <linux/rhashtable.h>
48 #include <net/udp_tunnel.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/dcbnl.h"
57 #include "en/fs.h"
58 #include "en/qos.h"
59 #include "lib/hv_vhca.h"
60 #include "lib/clock.h"
61 #include "en/rx_res.h"
62 #include "en/selq.h"
63
64 extern const struct net_device_ops mlx5e_netdev_ops;
65 struct page_pool;
66
67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
68 #define MLX5E_METADATA_ETHER_LEN 8
69
70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
71
72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
74
75 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE
76
77 #define MLX5_RX_HEADROOM NET_SKB_PAD
78 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
79 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
80
81 #define MLX5E_RX_MAX_HEAD (256)
82 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9)
83 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE)
84 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64)
85 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024)
86 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096)
87
88 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
89 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
90 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
91 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
92 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
93 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
94
95 #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18
96
97 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz.
98 * These are theoretical maximums, which can be further restricted by
99 * capabilities. These values are used for static resource allocations and
100 * sanity checks.
101 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE
102 * size actually used at runtime, but it's not a problem when calculating static
103 * array sizes.
104 */
105 #define MLX5_UMR_MAX_FLEX_SPACE \
106 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \
107 MLX5_UMR_FLEX_ALIGNMENT))
108 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \
109 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt))
110
111 #define MLX5E_MAX_RQ_NUM_MTTS \
112 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */
113 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */
114 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
115
116 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
117 #define MLX5E_LOG_MAX_RX_WQE_BULK \
118 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
119
120 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
121 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
122 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
123
124 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
125 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
126 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
127
128 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
129
130 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
131 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
132
133 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
136 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
139 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
141
142 #define MLX5E_MIN_NUM_CHANNELS 0x1
143 #define MLX5E_MAX_NUM_CHANNELS 256
144 #define MLX5E_TX_CQ_POLL_BUDGET 128
145 #define MLX5E_TX_XSK_POLL_BUDGET 64
146 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
147
148 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\
149 (sizeof(struct mlx5e_umr_wqe) +\
150 (sizeof(struct mlx5_klm) * (sgl_len)))
151
152 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \
153 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB))
154
155 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\
156 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS))
157
158 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\
159 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm))
160
161 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\
162 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT)
163
164 #define MLX5E_MAX_KLM_PER_WQE(mdev) \
165 MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * mlx5e_get_max_sq_aligned_wqebbs(mdev))
166
167 #define mlx5e_state_dereference(priv, p) \
168 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock))
169
170 enum mlx5e_devcom_events {
171 MPV_DEVCOM_MASTER_UP,
172 MPV_DEVCOM_MASTER_DOWN,
173 MPV_DEVCOM_IPSEC_MASTER_UP,
174 MPV_DEVCOM_IPSEC_MASTER_DOWN,
175 };
176
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)177 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
178 {
179 if (mlx5_lag_is_lacp_owner(mdev))
180 return 1;
181
182 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
183 }
184
mlx5_min_rx_wqes(int wq_type,u32 wq_size)185 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
186 {
187 switch (wq_type) {
188 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
189 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
190 wq_size / 2);
191 default:
192 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
193 wq_size / 2);
194 }
195 }
196
197 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)198 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
199 {
200 return is_kdump_kernel() ?
201 MLX5E_MIN_NUM_CHANNELS :
202 min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS,
203 (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size)));
204 }
205
206 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in
207 * bytes units. Driver hardens the limitation to 1KB (16
208 * WQEBBs), unless firmware capability is stricter.
209 */
mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev * mdev)210 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev)
211 {
212 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX);
213
214 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS,
215 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB);
216 }
217
mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev * mdev)218 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev)
219 {
220 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS.
221 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16,
222 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64)
223 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower
224 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be
225 * cache-aligned.
226 */
227 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev);
228
229 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1);
230 #if L1_CACHE_BYTES >= 128
231 wqebbs = ALIGN_DOWN(wqebbs, 2);
232 #endif
233 return wqebbs;
234 }
235
236 struct mlx5e_tx_wqe {
237 struct mlx5_wqe_ctrl_seg ctrl;
238 struct mlx5_wqe_eth_seg eth;
239 struct mlx5_wqe_data_seg data[];
240 };
241
242 struct mlx5e_rx_wqe_ll {
243 struct mlx5_wqe_srq_next_seg next;
244 struct mlx5_wqe_data_seg data[];
245 };
246
247 struct mlx5e_rx_wqe_cyc {
248 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data);
249 };
250
251 struct mlx5e_umr_wqe {
252 struct mlx5_wqe_ctrl_seg ctrl;
253 struct mlx5_wqe_umr_ctrl_seg uctrl;
254 struct mlx5_mkey_seg mkc;
255 union {
256 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts);
257 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms);
258 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms);
259 };
260 };
261
262 enum mlx5e_priv_flag {
263 MLX5E_PFLAG_RX_CQE_BASED_MODER,
264 MLX5E_PFLAG_TX_CQE_BASED_MODER,
265 MLX5E_PFLAG_RX_CQE_COMPRESS,
266 MLX5E_PFLAG_RX_STRIDING_RQ,
267 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
268 MLX5E_PFLAG_XDP_TX_MPWQE,
269 MLX5E_PFLAG_SKB_TX_MPWQE,
270 MLX5E_PFLAG_TX_PORT_TS,
271 MLX5E_NUM_PFLAGS, /* Keep last */
272 };
273
274 #define MLX5E_SET_PFLAG(params, pflag, enable) \
275 do { \
276 if (enable) \
277 (params)->pflags |= BIT(pflag); \
278 else \
279 (params)->pflags &= ~(BIT(pflag)); \
280 } while (0)
281
282 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
283
284 enum packet_merge {
285 MLX5E_PACKET_MERGE_NONE,
286 MLX5E_PACKET_MERGE_LRO,
287 MLX5E_PACKET_MERGE_SHAMPO,
288 };
289
290 struct mlx5e_packet_merge_param {
291 enum packet_merge type;
292 u32 timeout;
293 struct {
294 u8 match_criteria_type;
295 u8 alignment_granularity;
296 } shampo;
297 };
298
299 struct mlx5e_params {
300 u8 log_sq_size;
301 u8 rq_wq_type;
302 u8 log_rq_mtu_frames;
303 u16 num_channels;
304 struct {
305 u16 mode;
306 u8 num_tc;
307 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE];
308 struct {
309 u64 max_rate[TC_MAX_QUEUE];
310 u32 hw_id[TC_MAX_QUEUE];
311 } channel;
312 } mqprio;
313 bool rx_cqe_compress_def;
314 struct dim_cq_moder rx_cq_moderation;
315 struct dim_cq_moder tx_cq_moderation;
316 struct mlx5e_packet_merge_param packet_merge;
317 u8 tx_min_inline_mode;
318 bool vlan_strip_disable;
319 bool scatter_fcs_en;
320 bool rx_dim_enabled;
321 bool tx_dim_enabled;
322 u32 pflags;
323 struct bpf_prog *xdp_prog;
324 struct mlx5e_xsk *xsk;
325 unsigned int sw_mtu;
326 int hard_mtu;
327 bool ptp_rx;
328 __be32 terminate_lkey_be;
329 };
330
mlx5e_get_dcb_num_tc(struct mlx5e_params * params)331 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params)
332 {
333 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ?
334 params->mqprio.num_tc : 1;
335 }
336
337 /* Keep this enum consistent with the corresponding strings array
338 * declared in en/reporter_rx.c
339 */
340 enum {
341 MLX5E_RQ_STATE_ENABLED = 0,
342 MLX5E_RQ_STATE_RECOVERING,
343 MLX5E_RQ_STATE_DIM,
344 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
345 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
346 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */
347 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */
348 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */
349 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */
350 MLX5E_NUM_RQ_STATES, /* Must be kept last */
351 };
352
353 struct mlx5e_cq {
354 /* data path - accessed per cqe */
355 struct mlx5_cqwq wq;
356
357 /* data path - accessed per napi poll */
358 u16 event_ctr;
359 struct napi_struct *napi;
360 struct mlx5_core_cq mcq;
361 struct mlx5e_ch_stats *ch_stats;
362
363 /* control */
364 struct net_device *netdev;
365 struct mlx5_core_dev *mdev;
366 struct workqueue_struct *workqueue;
367 struct mlx5_wq_ctrl wq_ctrl;
368 } ____cacheline_aligned_in_smp;
369
370 struct mlx5e_cq_decomp {
371 /* cqe decompression */
372 struct mlx5_cqe64 title;
373 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
374 u8 mini_arr_idx;
375 u16 left;
376 u16 wqe_counter;
377 bool last_cqe_title;
378 } ____cacheline_aligned_in_smp;
379
380 enum mlx5e_dma_map_type {
381 MLX5E_DMA_MAP_SINGLE,
382 MLX5E_DMA_MAP_PAGE
383 };
384
385 struct mlx5e_sq_dma {
386 dma_addr_t addr;
387 u32 size;
388 enum mlx5e_dma_map_type type;
389 };
390
391 /* Keep this enum consistent with with the corresponding strings array
392 * declared in en/reporter_tx.c
393 */
394 enum {
395 MLX5E_SQ_STATE_ENABLED = 0,
396 MLX5E_SQ_STATE_MPWQE,
397 MLX5E_SQ_STATE_RECOVERING,
398 MLX5E_SQ_STATE_IPSEC,
399 MLX5E_SQ_STATE_DIM,
400 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
401 MLX5E_SQ_STATE_PENDING_XSK_TX,
402 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC,
403 MLX5E_SQ_STATE_XDP_MULTIBUF,
404 MLX5E_NUM_SQ_STATES, /* Must be kept last */
405 };
406
407 struct mlx5e_tx_mpwqe {
408 /* Current MPWQE session */
409 struct mlx5e_tx_wqe *wqe;
410 u32 bytes_count;
411 u8 ds_count;
412 u8 pkt_count;
413 u8 inline_on;
414 };
415
416 struct mlx5e_skb_fifo {
417 struct sk_buff **fifo;
418 u16 *pc;
419 u16 *cc;
420 u16 mask;
421 };
422
423 struct mlx5e_ptpsq;
424
425 struct mlx5e_txqsq {
426 /* data path */
427
428 /* dirtied @completion */
429 u16 cc;
430 u16 skb_fifo_cc;
431 u32 dma_fifo_cc;
432 struct dim dim; /* Adaptive Moderation */
433
434 /* dirtied @xmit */
435 u16 pc ____cacheline_aligned_in_smp;
436 u16 skb_fifo_pc;
437 u32 dma_fifo_pc;
438 struct mlx5e_tx_mpwqe mpwqe;
439
440 struct mlx5e_cq cq;
441
442 /* read only */
443 struct mlx5_wq_cyc wq;
444 u32 dma_fifo_mask;
445 struct mlx5e_sq_stats *stats;
446 struct {
447 struct mlx5e_sq_dma *dma_fifo;
448 struct mlx5e_skb_fifo skb_fifo;
449 struct mlx5e_tx_wqe_info *wqe_info;
450 } db;
451 void __iomem *uar_map;
452 struct netdev_queue *txq;
453 u32 sqn;
454 u16 stop_room;
455 u8 max_sq_mpw_wqebbs;
456 u8 min_inline_mode;
457 struct device *pdev;
458 __be32 mkey_be;
459 unsigned long state;
460 unsigned int hw_mtu;
461 struct mlx5_clock *clock;
462 struct net_device *netdev;
463 struct mlx5_core_dev *mdev;
464 struct mlx5e_channel *channel;
465 struct mlx5e_priv *priv;
466
467 /* control path */
468 struct mlx5_wq_ctrl wq_ctrl;
469 int ch_ix;
470 int txq_ix;
471 u32 rate_limit;
472 struct work_struct recover_work;
473 struct mlx5e_ptpsq *ptpsq;
474 cqe_ts_to_ns ptp_cyc2time;
475 } ____cacheline_aligned_in_smp;
476
477 struct mlx5e_xdp_info_fifo {
478 union mlx5e_xdp_info *xi;
479 u32 *cc;
480 u32 *pc;
481 u32 mask;
482 };
483
484 struct mlx5e_xdpsq;
485 struct mlx5e_xmit_data;
486 struct xsk_tx_metadata;
487 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
488 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
489 struct mlx5e_xmit_data *,
490 int,
491 struct xsk_tx_metadata *);
492
493 struct mlx5e_xdpsq {
494 /* data path */
495
496 /* dirtied @completion */
497 u32 xdpi_fifo_cc;
498 u16 cc;
499
500 /* dirtied @xmit */
501 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
502 u16 pc;
503 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
504 struct mlx5e_tx_mpwqe mpwqe;
505
506 struct mlx5e_cq cq;
507
508 /* read only */
509 struct xsk_buff_pool *xsk_pool;
510 struct mlx5_wq_cyc wq;
511 struct mlx5e_xdpsq_stats *stats;
512 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
513 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
514 struct {
515 struct mlx5e_xdp_wqe_info *wqe_info;
516 struct mlx5e_xdp_info_fifo xdpi_fifo;
517 } db;
518 void __iomem *uar_map;
519 u32 sqn;
520 struct device *pdev;
521 __be32 mkey_be;
522 u16 stop_room;
523 u8 max_sq_mpw_wqebbs;
524 u8 min_inline_mode;
525 unsigned long state;
526 unsigned int hw_mtu;
527
528 /* control path */
529 struct mlx5_wq_ctrl wq_ctrl;
530 struct mlx5e_channel *channel;
531 } ____cacheline_aligned_in_smp;
532
533 struct mlx5e_ktls_resync_resp;
534
535 struct mlx5e_icosq {
536 /* data path */
537 u16 cc;
538 u16 pc;
539
540 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
541 struct mlx5e_cq cq;
542
543 /* write@xmit, read@completion */
544 struct {
545 struct mlx5e_icosq_wqe_info *wqe_info;
546 } db;
547
548 /* read only */
549 struct mlx5_wq_cyc wq;
550 void __iomem *uar_map;
551 u32 sqn;
552 u16 reserved_room;
553 unsigned long state;
554 struct mlx5e_ktls_resync_resp *ktls_resync;
555
556 /* control path */
557 struct mlx5_wq_ctrl wq_ctrl;
558 struct mlx5e_channel *channel;
559
560 struct work_struct recover_work;
561 } ____cacheline_aligned_in_smp;
562
563 struct mlx5e_frag_page {
564 struct page *page;
565 u16 frags;
566 };
567
568 enum mlx5e_wqe_frag_flag {
569 MLX5E_WQE_FRAG_LAST_IN_PAGE,
570 MLX5E_WQE_FRAG_SKIP_RELEASE,
571 };
572
573 struct mlx5e_wqe_frag_info {
574 union {
575 struct mlx5e_frag_page *frag_page;
576 struct xdp_buff **xskp;
577 };
578 u32 offset;
579 u8 flags;
580 };
581
582 union mlx5e_alloc_units {
583 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages);
584 DECLARE_FLEX_ARRAY(struct page *, pages);
585 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs);
586 };
587
588 struct mlx5e_mpw_info {
589 u16 consumed_strides;
590 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE);
591 struct mlx5e_frag_page linear_page;
592 union mlx5e_alloc_units alloc_units;
593 };
594
595 #define MLX5E_MAX_RX_FRAGS 4
596
597 struct mlx5e_rq;
598 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
599 typedef struct sk_buff *
600 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
601 struct mlx5_cqe64 *cqe, u16 cqe_bcnt,
602 u32 head_offset, u32 page_idx);
603 typedef struct sk_buff *
604 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi,
605 struct mlx5_cqe64 *cqe, u32 cqe_bcnt);
606 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
607 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
608 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool);
609
610 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
611 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params);
612
613 enum mlx5e_rq_flag {
614 MLX5E_RQ_FLAG_XDP_XMIT,
615 MLX5E_RQ_FLAG_XDP_REDIRECT,
616 };
617
618 struct mlx5e_rq_frag_info {
619 int frag_size;
620 int frag_stride;
621 };
622
623 struct mlx5e_rq_frags_info {
624 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
625 u8 num_frags;
626 u8 log_num_frags;
627 u16 wqe_bulk;
628 u16 refill_unit;
629 u8 wqe_index_mask;
630 };
631
632 struct mlx5e_dma_info {
633 dma_addr_t addr;
634 union {
635 struct mlx5e_frag_page *frag_page;
636 struct page *page;
637 };
638 };
639
640 struct mlx5e_shampo_hd {
641 u32 mkey;
642 struct mlx5e_dma_info *info;
643 struct mlx5e_frag_page *pages;
644 u16 curr_page_index;
645 u16 hd_per_wq;
646 u16 hd_per_wqe;
647 unsigned long *bitmap;
648 u16 pi;
649 u16 ci;
650 __be32 key;
651 u64 last_addr;
652 };
653
654 struct mlx5e_hw_gro_data {
655 struct sk_buff *skb;
656 struct flow_keys fk;
657 int second_ip_id;
658 };
659
660 enum mlx5e_mpwrq_umr_mode {
661 MLX5E_MPWRQ_UMR_MODE_ALIGNED,
662 MLX5E_MPWRQ_UMR_MODE_UNALIGNED,
663 MLX5E_MPWRQ_UMR_MODE_OVERSIZED,
664 MLX5E_MPWRQ_UMR_MODE_TRIPLE,
665 };
666
667 struct mlx5e_rq {
668 /* data path */
669 union {
670 struct {
671 struct mlx5_wq_cyc wq;
672 struct mlx5e_wqe_frag_info *frags;
673 union mlx5e_alloc_units *alloc_units;
674 struct mlx5e_rq_frags_info info;
675 mlx5e_fp_skb_from_cqe skb_from_cqe;
676 } wqe;
677 struct {
678 struct mlx5_wq_ll wq;
679 struct mlx5e_umr_wqe umr_wqe;
680 struct mlx5e_mpw_info *info;
681 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
682 __be32 umr_mkey_be;
683 u16 num_strides;
684 u16 actual_wq_head;
685 u8 log_stride_sz;
686 u8 umr_in_progress;
687 u8 umr_last_bulk;
688 u8 umr_completed;
689 u8 min_wqe_bulk;
690 u8 page_shift;
691 u8 pages_per_wqe;
692 u8 umr_wqebbs;
693 u8 mtts_per_wqe;
694 u8 umr_mode;
695 struct mlx5e_shampo_hd *shampo;
696 } mpwqe;
697 };
698 struct {
699 u16 headroom;
700 u32 frame0_sz;
701 u8 map_dir; /* dma map direction */
702 } buff;
703
704 struct device *pdev;
705 struct net_device *netdev;
706 struct mlx5e_rq_stats *stats;
707 struct mlx5e_cq cq;
708 struct mlx5e_cq_decomp cqd;
709 struct hwtstamp_config *tstamp;
710 struct mlx5_clock *clock;
711 struct mlx5e_icosq *icosq;
712 struct mlx5e_priv *priv;
713
714 struct mlx5e_hw_gro_data *hw_gro_data;
715
716 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
717 mlx5e_fp_post_rx_wqes post_wqes;
718 mlx5e_fp_dealloc_wqe dealloc_wqe;
719
720 unsigned long state;
721 int ix;
722 unsigned int hw_mtu;
723
724 struct dim dim; /* Dynamic Interrupt Moderation */
725
726 /* XDP */
727 struct bpf_prog __rcu *xdp_prog;
728 struct mlx5e_xdpsq *xdpsq;
729 DECLARE_BITMAP(flags, 8);
730 struct page_pool *page_pool;
731
732 /* AF_XDP zero-copy */
733 struct xsk_buff_pool *xsk_pool;
734
735 struct work_struct recover_work;
736
737 /* control */
738 struct mlx5_wq_ctrl wq_ctrl;
739 __be32 mkey_be;
740 u8 wq_type;
741 u32 rqn;
742 struct mlx5_core_dev *mdev;
743 struct mlx5e_channel *channel;
744 struct mlx5e_dma_info wqe_overflow;
745
746 /* XDP read-mostly */
747 struct xdp_rxq_info xdp_rxq;
748 cqe_ts_to_ns ptp_cyc2time;
749 } ____cacheline_aligned_in_smp;
750
751 enum mlx5e_channel_state {
752 MLX5E_CHANNEL_STATE_XSK,
753 MLX5E_CHANNEL_NUM_STATES
754 };
755
756 struct mlx5e_channel {
757 /* data path */
758 struct mlx5e_rq rq;
759 struct mlx5e_xdpsq rq_xdpsq;
760 struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC];
761 struct mlx5e_icosq icosq; /* internal control operations */
762 struct mlx5e_txqsq __rcu * __rcu *qos_sqs;
763 bool xdp;
764 struct napi_struct napi;
765 struct device *pdev;
766 struct net_device *netdev;
767 __be32 mkey_be;
768 u16 qos_sqs_size;
769 u8 num_tc;
770 u8 lag_port;
771
772 /* XDP_REDIRECT */
773 struct mlx5e_xdpsq xdpsq;
774
775 /* AF_XDP zero-copy */
776 struct mlx5e_rq xskrq;
777 struct mlx5e_xdpsq xsksq;
778
779 /* Async ICOSQ */
780 struct mlx5e_icosq async_icosq;
781 /* async_icosq can be accessed from any CPU - the spinlock protects it. */
782 spinlock_t async_icosq_lock;
783
784 /* data path - accessed per napi poll */
785 const struct cpumask *aff_mask;
786 struct mlx5e_ch_stats *stats;
787
788 /* control */
789 struct mlx5e_priv *priv;
790 struct mlx5_core_dev *mdev;
791 struct hwtstamp_config *tstamp;
792 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
793 int ix;
794 int cpu;
795 /* Sync between icosq recovery and XSK enable/disable. */
796 struct mutex icosq_recovery_lock;
797 };
798
799 struct mlx5e_ptp;
800
801 struct mlx5e_channels {
802 struct mlx5e_channel **c;
803 struct mlx5e_ptp *ptp;
804 unsigned int num;
805 struct mlx5e_params params;
806 };
807
808 struct mlx5e_channel_stats {
809 struct mlx5e_ch_stats ch;
810 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
811 struct mlx5e_rq_stats rq;
812 struct mlx5e_rq_stats xskrq;
813 struct mlx5e_xdpsq_stats rq_xdpsq;
814 struct mlx5e_xdpsq_stats xdpsq;
815 struct mlx5e_xdpsq_stats xsksq;
816 } ____cacheline_aligned_in_smp;
817
818 struct mlx5e_ptp_stats {
819 struct mlx5e_ch_stats ch;
820 struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];
821 struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];
822 struct mlx5e_rq_stats rq;
823 } ____cacheline_aligned_in_smp;
824
825 enum {
826 MLX5E_STATE_OPENED,
827 MLX5E_STATE_DESTROYING,
828 MLX5E_STATE_XDP_TX_ENABLED,
829 MLX5E_STATE_XDP_ACTIVE,
830 MLX5E_STATE_CHANNELS_ACTIVE,
831 };
832
833 struct mlx5e_modify_sq_param {
834 int curr_state;
835 int next_state;
836 int rl_update;
837 int rl_index;
838 bool qos_update;
839 u16 qos_queue_group_id;
840 };
841
842 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
843 struct mlx5e_hv_vhca_stats_agent {
844 struct mlx5_hv_vhca_agent *agent;
845 struct delayed_work work;
846 u16 delay;
847 void *buf;
848 };
849 #endif
850
851 struct mlx5e_xsk {
852 /* XSK buffer pools are stored separately from channels,
853 * because we don't want to lose them when channels are
854 * recreated. The kernel also stores buffer pool, but it doesn't
855 * distinguish between zero-copy and non-zero-copy UMEMs, so
856 * rely on our mechanism.
857 */
858 struct xsk_buff_pool **pools;
859 u16 refcnt;
860 bool ever_used;
861 };
862
863 /* Temporary storage for variables that are allocated when struct mlx5e_priv is
864 * initialized, and used where we can't allocate them because that functions
865 * must not fail. Use with care and make sure the same variable is not used
866 * simultaneously by multiple users.
867 */
868 struct mlx5e_scratchpad {
869 cpumask_var_t cpumask;
870 };
871
872 struct mlx5e_trap;
873 struct mlx5e_htb;
874
875 struct mlx5e_priv {
876 /* priv data path fields - start */
877 struct mlx5e_selq selq;
878 struct mlx5e_txqsq **txq2sq;
879 #ifdef CONFIG_MLX5_CORE_EN_DCB
880 struct mlx5e_dcbx_dp dcbx_dp;
881 #endif
882 /* priv data path fields - end */
883
884 unsigned long state;
885 struct mutex state_lock; /* Protects Interface state */
886 struct mlx5e_rq drop_rq;
887
888 struct mlx5e_channels channels;
889 struct mlx5e_rx_res *rx_res;
890 u32 *tx_rates;
891
892 struct mlx5e_flow_steering *fs;
893
894 struct workqueue_struct *wq;
895 struct work_struct update_carrier_work;
896 struct work_struct set_rx_mode_work;
897 struct work_struct tx_timeout_work;
898 struct work_struct update_stats_work;
899 struct work_struct monitor_counters_work;
900 struct mlx5_nb monitor_counters_nb;
901
902 struct mlx5_core_dev *mdev;
903 struct net_device *netdev;
904 struct mlx5e_trap *en_trap;
905 struct mlx5e_stats stats;
906 struct mlx5e_channel_stats **channel_stats;
907 struct mlx5e_channel_stats trap_stats;
908 struct mlx5e_ptp_stats ptp_stats;
909 struct mlx5e_sq_stats **htb_qos_sq_stats;
910 u16 htb_max_qos_sqs;
911 u16 stats_nch;
912 u16 max_nch;
913 u8 max_opened_tc;
914 bool tx_ptp_opened;
915 bool rx_ptp_opened;
916 struct hwtstamp_config tstamp;
917 u16 q_counter;
918 u16 drop_rq_q_counter;
919 struct notifier_block events_nb;
920 struct notifier_block blocking_events_nb;
921
922 struct udp_tunnel_nic_info nic_info;
923 #ifdef CONFIG_MLX5_CORE_EN_DCB
924 struct mlx5e_dcbx dcbx;
925 #endif
926
927 const struct mlx5e_profile *profile;
928 void *ppriv;
929 #ifdef CONFIG_MLX5_MACSEC
930 struct mlx5e_macsec *macsec;
931 #endif
932 #ifdef CONFIG_MLX5_EN_IPSEC
933 struct mlx5e_ipsec *ipsec;
934 #endif
935 #ifdef CONFIG_MLX5_EN_TLS
936 struct mlx5e_tls *tls;
937 #endif
938 struct devlink_health_reporter *tx_reporter;
939 struct devlink_health_reporter *rx_reporter;
940 struct mlx5e_xsk xsk;
941 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
942 struct mlx5e_hv_vhca_stats_agent stats_agent;
943 #endif
944 struct mlx5e_scratchpad scratchpad;
945 struct mlx5e_htb *htb;
946 struct mlx5e_mqprio_rl *mqprio_rl;
947 struct dentry *dfs_root;
948 struct mlx5_devcom_comp_dev *devcom;
949 };
950
951 struct mlx5e_dev {
952 struct mlx5e_priv *priv;
953 struct devlink_port dl_port;
954 };
955
956 struct mlx5e_rx_handlers {
957 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
958 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
959 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo;
960 };
961
962 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
963
964 enum mlx5e_profile_feature {
965 MLX5E_PROFILE_FEATURE_PTP_RX,
966 MLX5E_PROFILE_FEATURE_PTP_TX,
967 MLX5E_PROFILE_FEATURE_QOS_HTB,
968 MLX5E_PROFILE_FEATURE_FS_VLAN,
969 MLX5E_PROFILE_FEATURE_FS_TC,
970 };
971
972 struct mlx5e_profile {
973 int (*init)(struct mlx5_core_dev *mdev,
974 struct net_device *netdev);
975 void (*cleanup)(struct mlx5e_priv *priv);
976 int (*init_rx)(struct mlx5e_priv *priv);
977 void (*cleanup_rx)(struct mlx5e_priv *priv);
978 int (*init_tx)(struct mlx5e_priv *priv);
979 void (*cleanup_tx)(struct mlx5e_priv *priv);
980 void (*enable)(struct mlx5e_priv *priv);
981 void (*disable)(struct mlx5e_priv *priv);
982 int (*update_rx)(struct mlx5e_priv *priv);
983 void (*update_stats)(struct mlx5e_priv *priv);
984 void (*update_carrier)(struct mlx5e_priv *priv);
985 int (*max_nch_limit)(struct mlx5_core_dev *mdev);
986 u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,
987 u8 lag_port, u8 tc);
988 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
989 mlx5e_stats_grp_t *stats_grps;
990 const struct mlx5e_rx_handlers *rx_handlers;
991 int max_tc;
992 u32 features;
993 };
994
995 u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,
996 struct mlx5e_priv *priv,
997 const struct mlx5e_profile *profile,
998 u8 lag_port, u8 tc);
999
1000 #define mlx5e_profile_feature_cap(profile, feature) \
1001 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
1002
1003 void mlx5e_build_ptys2ethtool_map(void);
1004
1005 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift,
1006 enum mlx5e_mpwrq_umr_mode umr_mode);
1007
1008 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close);
1009 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
1010 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
1011
1012 int mlx5e_self_test_num(struct mlx5e_priv *priv);
1013 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data);
1014 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
1015 u64 *buf);
1016 void mlx5e_set_rx_mode_work(struct work_struct *work);
1017
1018 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
1019 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
1020 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter);
1021
1022 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
1023 u16 vid);
1024 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
1025 u16 vid);
1026 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
1027
1028 struct mlx5e_xsk_param;
1029
1030 struct mlx5e_rq_param;
1031 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param,
1032 struct mlx5e_xsk_param *xsk, int node,
1033 struct mlx5e_rq *rq);
1034 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
1035 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1036 void mlx5e_close_rq(struct mlx5e_rq *rq);
1037 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param);
1038 void mlx5e_destroy_rq(struct mlx5e_rq *rq);
1039
1040 struct mlx5e_sq_param;
1041 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1042 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
1043 struct mlx5e_xdpsq *sq, bool is_redirect);
1044 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1045
1046 struct mlx5e_create_cq_param {
1047 struct net_device *netdev;
1048 struct workqueue_struct *wq;
1049 struct napi_struct *napi;
1050 struct mlx5e_ch_stats *ch_stats;
1051 int node;
1052 int ix;
1053 };
1054
1055 struct mlx5e_cq_param;
1056 int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder,
1057 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
1058 struct mlx5e_cq *cq);
1059 void mlx5e_close_cq(struct mlx5e_cq *cq);
1060
1061 int mlx5e_open_locked(struct net_device *netdev);
1062 int mlx5e_close_locked(struct net_device *netdev);
1063
1064 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c);
1065 void mlx5e_trigger_napi_sched(struct napi_struct *napi);
1066
1067 int mlx5e_open_channels(struct mlx5e_priv *priv,
1068 struct mlx5e_channels *chs);
1069 void mlx5e_close_channels(struct mlx5e_channels *chs);
1070
1071 /* Function pointer to be used to modify HW or kernel settings while
1072 * switching channels
1073 */
1074 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
1075 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
1076 int fn##_ctx(struct mlx5e_priv *priv, void *context) \
1077 { \
1078 return fn(priv); \
1079 }
1080 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1081 int mlx5e_safe_switch_params(struct mlx5e_priv *priv,
1082 struct mlx5e_params *new_params,
1083 mlx5e_fp_preactivate preactivate,
1084 void *context, bool reset);
1085 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv);
1086 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
1087 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1088 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1089 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx);
1090
1091 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state);
1092 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1093 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1094 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1095 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1096
1097 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1098 struct mlx5e_modify_sq_param *p);
1099 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix,
1100 struct mlx5e_params *params, struct mlx5e_sq_param *param,
1101 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id,
1102 struct mlx5e_sq_stats *sq_stats);
1103 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1104 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
1105 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
1106 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1107 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
1108 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
1109 struct mlx5e_create_sq_param;
1110 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1111 struct mlx5e_sq_param *param,
1112 struct mlx5e_create_sq_param *csp,
1113 u16 qos_queue_group_id,
1114 u32 *sqn);
1115 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1116 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq);
1117
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1118 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1119 {
1120 return MLX5_CAP_ETH(mdev, swp) &&
1121 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1122 }
1123
1124 extern const struct ethtool_ops mlx5e_ethtool_ops;
1125
1126 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1127 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises);
1128 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1129 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
1130 bool enable_mc_lb);
1131 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
1132
1133 /* common netdev helpers */
1134 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1135 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1136 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1137 struct mlx5e_rq *drop_rq);
1138 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1139
1140 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1141 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1142
1143 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1144 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1145 int mlx5e_close(struct net_device *netdev);
1146 int mlx5e_open(struct net_device *netdev);
1147
1148 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1149
1150 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1151 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
1152 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1153 mlx5e_fp_preactivate preactivate);
1154 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
1155
1156 /* ethtool helpers */
1157 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1158 struct ethtool_drvinfo *drvinfo);
1159 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1160 uint32_t stringset, uint8_t *data);
1161 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1162 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1163 struct ethtool_stats *stats, u64 *data);
1164 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1165 struct ethtool_ringparam *param,
1166 struct kernel_ethtool_ringparam *kernel_param);
1167 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1168 struct ethtool_ringparam *param);
1169 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1170 struct ethtool_channels *ch);
1171 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1172 struct ethtool_channels *ch);
1173 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1174 struct ethtool_coalesce *coal,
1175 struct kernel_ethtool_coalesce *kernel_coal);
1176 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1177 struct ethtool_coalesce *coal,
1178 struct kernel_ethtool_coalesce *kernel_coal,
1179 struct netlink_ext_ack *extack);
1180 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1181 struct ethtool_link_ksettings *link_ksettings);
1182 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1183 const struct ethtool_link_ksettings *link_ksettings);
1184 int mlx5e_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh);
1185 int mlx5e_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh,
1186 struct netlink_ext_ack *extack);
1187 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1188 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1189 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1190 struct ethtool_ts_info *info);
1191 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1192 struct ethtool_flash *flash);
1193 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1194 struct ethtool_pauseparam *pauseparam);
1195 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1196 struct ethtool_pauseparam *pauseparam);
1197
1198 /* mlx5e generic netdev management API */
1199 static inline bool
mlx5e_tx_mpwqe_supported(struct mlx5_core_dev * mdev)1200 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev)
1201 {
1202 return !is_kdump_kernel() &&
1203 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe);
1204 }
1205
1206 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev);
1207 int mlx5e_priv_init(struct mlx5e_priv *priv,
1208 const struct mlx5e_profile *profile,
1209 struct net_device *netdev,
1210 struct mlx5_core_dev *mdev);
1211 void mlx5e_priv_cleanup(struct mlx5e_priv *priv);
1212 struct net_device *
1213 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile);
1214 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1215 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1216 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1217 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv,
1218 const struct mlx5e_profile *new_profile, void *new_ppriv);
1219 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv);
1220 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1221 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu);
1222 void mlx5e_rx_dim_work(struct work_struct *work);
1223 void mlx5e_tx_dim_work(struct work_struct *work);
1224
1225 void mlx5e_set_xdp_feature(struct net_device *netdev);
1226 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1227 struct net_device *netdev,
1228 netdev_features_t features);
1229 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1230 #ifdef CONFIG_MLX5_ESWITCH
1231 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1232 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1233 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1234 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1235 #endif
1236 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey);
1237 #endif /* __MLX5_EN_H__ */
1238