1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2022, Intel Corporation. */
3 
4 #include "ice.h"
5 #include "ice_lib.h"
6 #include "ice_trace.h"
7 #include <linux/dpll.h>
8 
9 #define ICE_CGU_STATE_ACQ_ERR_THRESHOLD		50
10 #define ICE_DPLL_PIN_IDX_INVALID		0xff
11 #define ICE_DPLL_RCLK_NUM_PER_PF		1
12 
13 /**
14  * enum ice_dpll_pin_type - enumerate ice pin types:
15  * @ICE_DPLL_PIN_INVALID: invalid pin type
16  * @ICE_DPLL_PIN_TYPE_INPUT: input pin
17  * @ICE_DPLL_PIN_TYPE_OUTPUT: output pin
18  * @ICE_DPLL_PIN_TYPE_RCLK_INPUT: recovery clock input pin
19  */
20 enum ice_dpll_pin_type {
21 	ICE_DPLL_PIN_INVALID,
22 	ICE_DPLL_PIN_TYPE_INPUT,
23 	ICE_DPLL_PIN_TYPE_OUTPUT,
24 	ICE_DPLL_PIN_TYPE_RCLK_INPUT,
25 };
26 
27 static const char * const pin_type_name[] = {
28 	[ICE_DPLL_PIN_TYPE_INPUT] = "input",
29 	[ICE_DPLL_PIN_TYPE_OUTPUT] = "output",
30 	[ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
31 };
32 
33 /**
34  * ice_dpll_is_reset - check if reset is in progress
35  * @pf: private board structure
36  * @extack: error reporting
37  *
38  * If reset is in progress, fill extack with error.
39  *
40  * Return:
41  * * false - no reset in progress
42  * * true - reset in progress
43  */
ice_dpll_is_reset(struct ice_pf * pf,struct netlink_ext_ack * extack)44 static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack *extack)
45 {
46 	if (ice_is_reset_in_progress(pf->state)) {
47 		NL_SET_ERR_MSG(extack, "PF reset in progress");
48 		return true;
49 	}
50 	return false;
51 }
52 
53 /**
54  * ice_dpll_pin_freq_set - set pin's frequency
55  * @pf: private board structure
56  * @pin: pointer to a pin
57  * @pin_type: type of pin being configured
58  * @freq: frequency to be set
59  * @extack: error reporting
60  *
61  * Set requested frequency on a pin.
62  *
63  * Context: Called under pf->dplls.lock
64  * Return:
65  * * 0 - success
66  * * negative - error on AQ or wrong pin type given
67  */
68 static int
ice_dpll_pin_freq_set(struct ice_pf * pf,struct ice_dpll_pin * pin,enum ice_dpll_pin_type pin_type,const u32 freq,struct netlink_ext_ack * extack)69 ice_dpll_pin_freq_set(struct ice_pf *pf, struct ice_dpll_pin *pin,
70 		      enum ice_dpll_pin_type pin_type, const u32 freq,
71 		      struct netlink_ext_ack *extack)
72 {
73 	u8 flags;
74 	int ret;
75 
76 	switch (pin_type) {
77 	case ICE_DPLL_PIN_TYPE_INPUT:
78 		flags = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ;
79 		ret = ice_aq_set_input_pin_cfg(&pf->hw, pin->idx, flags,
80 					       pin->flags[0], freq, 0);
81 		break;
82 	case ICE_DPLL_PIN_TYPE_OUTPUT:
83 		flags = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_FREQ;
84 		ret = ice_aq_set_output_pin_cfg(&pf->hw, pin->idx, flags,
85 						0, freq, 0);
86 		break;
87 	default:
88 		return -EINVAL;
89 	}
90 	if (ret) {
91 		NL_SET_ERR_MSG_FMT(extack,
92 				   "err:%d %s failed to set pin freq:%u on pin:%u\n",
93 				   ret,
94 				   ice_aq_str(pf->hw.adminq.sq_last_status),
95 				   freq, pin->idx);
96 		return ret;
97 	}
98 	pin->freq = freq;
99 
100 	return 0;
101 }
102 
103 /**
104  * ice_dpll_frequency_set - wrapper for pin callback for set frequency
105  * @pin: pointer to a pin
106  * @pin_priv: private data pointer passed on pin registration
107  * @dpll: pointer to dpll
108  * @dpll_priv: private data pointer passed on dpll registration
109  * @frequency: frequency to be set
110  * @extack: error reporting
111  * @pin_type: type of pin being configured
112  *
113  * Wraps internal set frequency command on a pin.
114  *
115  * Context: Acquires pf->dplls.lock
116  * Return:
117  * * 0 - success
118  * * negative - error pin not found or couldn't set in hw
119  */
120 static int
ice_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,const u32 frequency,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type)121 ice_dpll_frequency_set(const struct dpll_pin *pin, void *pin_priv,
122 		       const struct dpll_device *dpll, void *dpll_priv,
123 		       const u32 frequency,
124 		       struct netlink_ext_ack *extack,
125 		       enum ice_dpll_pin_type pin_type)
126 {
127 	struct ice_dpll_pin *p = pin_priv;
128 	struct ice_dpll *d = dpll_priv;
129 	struct ice_pf *pf = d->pf;
130 	int ret;
131 
132 	if (ice_dpll_is_reset(pf, extack))
133 		return -EBUSY;
134 
135 	mutex_lock(&pf->dplls.lock);
136 	ret = ice_dpll_pin_freq_set(pf, p, pin_type, frequency, extack);
137 	mutex_unlock(&pf->dplls.lock);
138 
139 	return ret;
140 }
141 
142 /**
143  * ice_dpll_input_frequency_set - input pin callback for set frequency
144  * @pin: pointer to a pin
145  * @pin_priv: private data pointer passed on pin registration
146  * @dpll: pointer to dpll
147  * @dpll_priv: private data pointer passed on dpll registration
148  * @frequency: frequency to be set
149  * @extack: error reporting
150  *
151  * Wraps internal set frequency command on a pin.
152  *
153  * Context: Calls a function which acquires pf->dplls.lock
154  * Return:
155  * * 0 - success
156  * * negative - error pin not found or couldn't set in hw
157  */
158 static int
ice_dpll_input_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)159 ice_dpll_input_frequency_set(const struct dpll_pin *pin, void *pin_priv,
160 			     const struct dpll_device *dpll, void *dpll_priv,
161 			     u64 frequency, struct netlink_ext_ack *extack)
162 {
163 	return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency,
164 				      extack, ICE_DPLL_PIN_TYPE_INPUT);
165 }
166 
167 /**
168  * ice_dpll_output_frequency_set - output pin callback for set frequency
169  * @pin: pointer to a pin
170  * @pin_priv: private data pointer passed on pin registration
171  * @dpll: pointer to dpll
172  * @dpll_priv: private data pointer passed on dpll registration
173  * @frequency: frequency to be set
174  * @extack: error reporting
175  *
176  * Wraps internal set frequency command on a pin.
177  *
178  * Context: Calls a function which acquires pf->dplls.lock
179  * Return:
180  * * 0 - success
181  * * negative - error pin not found or couldn't set in hw
182  */
183 static int
ice_dpll_output_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)184 ice_dpll_output_frequency_set(const struct dpll_pin *pin, void *pin_priv,
185 			      const struct dpll_device *dpll, void *dpll_priv,
186 			      u64 frequency, struct netlink_ext_ack *extack)
187 {
188 	return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency,
189 				      extack, ICE_DPLL_PIN_TYPE_OUTPUT);
190 }
191 
192 /**
193  * ice_dpll_frequency_get - wrapper for pin callback for get frequency
194  * @pin: pointer to a pin
195  * @pin_priv: private data pointer passed on pin registration
196  * @dpll: pointer to dpll
197  * @dpll_priv: private data pointer passed on dpll registration
198  * @frequency: on success holds pin's frequency
199  * @extack: error reporting
200  * @pin_type: type of pin being configured
201  *
202  * Wraps internal get frequency command of a pin.
203  *
204  * Context: Acquires pf->dplls.lock
205  * Return:
206  * * 0 - success
207  * * negative - error pin not found or couldn't get from hw
208  */
209 static int
ice_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type)210 ice_dpll_frequency_get(const struct dpll_pin *pin, void *pin_priv,
211 		       const struct dpll_device *dpll, void *dpll_priv,
212 		       u64 *frequency, struct netlink_ext_ack *extack,
213 		       enum ice_dpll_pin_type pin_type)
214 {
215 	struct ice_dpll_pin *p = pin_priv;
216 	struct ice_dpll *d = dpll_priv;
217 	struct ice_pf *pf = d->pf;
218 
219 	mutex_lock(&pf->dplls.lock);
220 	*frequency = p->freq;
221 	mutex_unlock(&pf->dplls.lock);
222 
223 	return 0;
224 }
225 
226 /**
227  * ice_dpll_input_frequency_get - input pin callback for get frequency
228  * @pin: pointer to a pin
229  * @pin_priv: private data pointer passed on pin registration
230  * @dpll: pointer to dpll
231  * @dpll_priv: private data pointer passed on dpll registration
232  * @frequency: on success holds pin's frequency
233  * @extack: error reporting
234  *
235  * Wraps internal get frequency command of a input pin.
236  *
237  * Context: Calls a function which acquires pf->dplls.lock
238  * Return:
239  * * 0 - success
240  * * negative - error pin not found or couldn't get from hw
241  */
242 static int
ice_dpll_input_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)243 ice_dpll_input_frequency_get(const struct dpll_pin *pin, void *pin_priv,
244 			     const struct dpll_device *dpll, void *dpll_priv,
245 			     u64 *frequency, struct netlink_ext_ack *extack)
246 {
247 	return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency,
248 				      extack, ICE_DPLL_PIN_TYPE_INPUT);
249 }
250 
251 /**
252  * ice_dpll_output_frequency_get - output pin callback for get frequency
253  * @pin: pointer to a pin
254  * @pin_priv: private data pointer passed on pin registration
255  * @dpll: pointer to dpll
256  * @dpll_priv: private data pointer passed on dpll registration
257  * @frequency: on success holds pin's frequency
258  * @extack: error reporting
259  *
260  * Wraps internal get frequency command of a pin.
261  *
262  * Context: Calls a function which acquires pf->dplls.lock
263  * Return:
264  * * 0 - success
265  * * negative - error pin not found or couldn't get from hw
266  */
267 static int
ice_dpll_output_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)268 ice_dpll_output_frequency_get(const struct dpll_pin *pin, void *pin_priv,
269 			      const struct dpll_device *dpll, void *dpll_priv,
270 			      u64 *frequency, struct netlink_ext_ack *extack)
271 {
272 	return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency,
273 				      extack, ICE_DPLL_PIN_TYPE_OUTPUT);
274 }
275 
276 /**
277  * ice_dpll_pin_enable - enable a pin on dplls
278  * @hw: board private hw structure
279  * @pin: pointer to a pin
280  * @dpll_idx: dpll index to connect to output pin
281  * @pin_type: type of pin being enabled
282  * @extack: error reporting
283  *
284  * Enable a pin on both dplls. Store current state in pin->flags.
285  *
286  * Context: Called under pf->dplls.lock
287  * Return:
288  * * 0 - OK
289  * * negative - error
290  */
291 static int
ice_dpll_pin_enable(struct ice_hw * hw,struct ice_dpll_pin * pin,u8 dpll_idx,enum ice_dpll_pin_type pin_type,struct netlink_ext_ack * extack)292 ice_dpll_pin_enable(struct ice_hw *hw, struct ice_dpll_pin *pin,
293 		    u8 dpll_idx, enum ice_dpll_pin_type pin_type,
294 		    struct netlink_ext_ack *extack)
295 {
296 	u8 flags = 0;
297 	int ret;
298 
299 	switch (pin_type) {
300 	case ICE_DPLL_PIN_TYPE_INPUT:
301 		if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
302 			flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
303 		flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
304 		ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0);
305 		break;
306 	case ICE_DPLL_PIN_TYPE_OUTPUT:
307 		flags = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_SRC_SEL;
308 		if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
309 			flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
310 		flags |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
311 		ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, dpll_idx,
312 						0, 0);
313 		break;
314 	default:
315 		return -EINVAL;
316 	}
317 	if (ret)
318 		NL_SET_ERR_MSG_FMT(extack,
319 				   "err:%d %s failed to enable %s pin:%u\n",
320 				   ret, ice_aq_str(hw->adminq.sq_last_status),
321 				   pin_type_name[pin_type], pin->idx);
322 
323 	return ret;
324 }
325 
326 /**
327  * ice_dpll_pin_disable - disable a pin on dplls
328  * @hw: board private hw structure
329  * @pin: pointer to a pin
330  * @pin_type: type of pin being disabled
331  * @extack: error reporting
332  *
333  * Disable a pin on both dplls. Store current state in pin->flags.
334  *
335  * Context: Called under pf->dplls.lock
336  * Return:
337  * * 0 - OK
338  * * negative - error
339  */
340 static int
ice_dpll_pin_disable(struct ice_hw * hw,struct ice_dpll_pin * pin,enum ice_dpll_pin_type pin_type,struct netlink_ext_ack * extack)341 ice_dpll_pin_disable(struct ice_hw *hw, struct ice_dpll_pin *pin,
342 		     enum ice_dpll_pin_type pin_type,
343 		     struct netlink_ext_ack *extack)
344 {
345 	u8 flags = 0;
346 	int ret;
347 
348 	switch (pin_type) {
349 	case ICE_DPLL_PIN_TYPE_INPUT:
350 		if (pin->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
351 			flags |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
352 		ret = ice_aq_set_input_pin_cfg(hw, pin->idx, 0, flags, 0, 0);
353 		break;
354 	case ICE_DPLL_PIN_TYPE_OUTPUT:
355 		if (pin->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
356 			flags |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
357 		ret = ice_aq_set_output_pin_cfg(hw, pin->idx, flags, 0, 0, 0);
358 		break;
359 	default:
360 		return -EINVAL;
361 	}
362 	if (ret)
363 		NL_SET_ERR_MSG_FMT(extack,
364 				   "err:%d %s failed to disable %s pin:%u\n",
365 				   ret, ice_aq_str(hw->adminq.sq_last_status),
366 				   pin_type_name[pin_type], pin->idx);
367 
368 	return ret;
369 }
370 
371 /**
372  * ice_dpll_pin_state_update - update pin's state
373  * @pf: private board struct
374  * @pin: structure with pin attributes to be updated
375  * @pin_type: type of pin being updated
376  * @extack: error reporting
377  *
378  * Determine pin current state and frequency, then update struct
379  * holding the pin info. For input pin states are separated for each
380  * dpll, for rclk pins states are separated for each parent.
381  *
382  * Context: Called under pf->dplls.lock
383  * Return:
384  * * 0 - OK
385  * * negative - error
386  */
387 static int
ice_dpll_pin_state_update(struct ice_pf * pf,struct ice_dpll_pin * pin,enum ice_dpll_pin_type pin_type,struct netlink_ext_ack * extack)388 ice_dpll_pin_state_update(struct ice_pf *pf, struct ice_dpll_pin *pin,
389 			  enum ice_dpll_pin_type pin_type,
390 			  struct netlink_ext_ack *extack)
391 {
392 	u8 parent, port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT;
393 	int ret;
394 
395 	switch (pin_type) {
396 	case ICE_DPLL_PIN_TYPE_INPUT:
397 		ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, NULL,
398 					       NULL, &pin->flags[0],
399 					       &pin->freq, &pin->phase_adjust);
400 		if (ret)
401 			goto err;
402 		if (ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN & pin->flags[0]) {
403 			if (pin->pin) {
404 				pin->state[pf->dplls.eec.dpll_idx] =
405 					pin->pin == pf->dplls.eec.active_input ?
406 					DPLL_PIN_STATE_CONNECTED :
407 					DPLL_PIN_STATE_SELECTABLE;
408 				pin->state[pf->dplls.pps.dpll_idx] =
409 					pin->pin == pf->dplls.pps.active_input ?
410 					DPLL_PIN_STATE_CONNECTED :
411 					DPLL_PIN_STATE_SELECTABLE;
412 			} else {
413 				pin->state[pf->dplls.eec.dpll_idx] =
414 					DPLL_PIN_STATE_SELECTABLE;
415 				pin->state[pf->dplls.pps.dpll_idx] =
416 					DPLL_PIN_STATE_SELECTABLE;
417 			}
418 		} else {
419 			pin->state[pf->dplls.eec.dpll_idx] =
420 				DPLL_PIN_STATE_DISCONNECTED;
421 			pin->state[pf->dplls.pps.dpll_idx] =
422 				DPLL_PIN_STATE_DISCONNECTED;
423 		}
424 		break;
425 	case ICE_DPLL_PIN_TYPE_OUTPUT:
426 		ret = ice_aq_get_output_pin_cfg(&pf->hw, pin->idx,
427 						&pin->flags[0], &parent,
428 						&pin->freq, NULL);
429 		if (ret)
430 			goto err;
431 
432 		parent &= ICE_AQC_GET_CGU_OUT_CFG_DPLL_SRC_SEL;
433 		if (ICE_AQC_SET_CGU_OUT_CFG_OUT_EN & pin->flags[0]) {
434 			pin->state[pf->dplls.eec.dpll_idx] =
435 				parent == pf->dplls.eec.dpll_idx ?
436 				DPLL_PIN_STATE_CONNECTED :
437 				DPLL_PIN_STATE_DISCONNECTED;
438 			pin->state[pf->dplls.pps.dpll_idx] =
439 				parent == pf->dplls.pps.dpll_idx ?
440 				DPLL_PIN_STATE_CONNECTED :
441 				DPLL_PIN_STATE_DISCONNECTED;
442 		} else {
443 			pin->state[pf->dplls.eec.dpll_idx] =
444 				DPLL_PIN_STATE_DISCONNECTED;
445 			pin->state[pf->dplls.pps.dpll_idx] =
446 				DPLL_PIN_STATE_DISCONNECTED;
447 		}
448 		break;
449 	case ICE_DPLL_PIN_TYPE_RCLK_INPUT:
450 		for (parent = 0; parent < pf->dplls.rclk.num_parents;
451 		     parent++) {
452 			u8 p = parent;
453 
454 			ret = ice_aq_get_phy_rec_clk_out(&pf->hw, &p,
455 							 &port_num,
456 							 &pin->flags[parent],
457 							 NULL);
458 			if (ret)
459 				goto err;
460 			if (ICE_AQC_GET_PHY_REC_CLK_OUT_OUT_EN &
461 			    pin->flags[parent])
462 				pin->state[parent] = DPLL_PIN_STATE_CONNECTED;
463 			else
464 				pin->state[parent] =
465 					DPLL_PIN_STATE_DISCONNECTED;
466 		}
467 		break;
468 	default:
469 		return -EINVAL;
470 	}
471 
472 	return 0;
473 err:
474 	if (extack)
475 		NL_SET_ERR_MSG_FMT(extack,
476 				   "err:%d %s failed to update %s pin:%u\n",
477 				   ret,
478 				   ice_aq_str(pf->hw.adminq.sq_last_status),
479 				   pin_type_name[pin_type], pin->idx);
480 	else
481 		dev_err_ratelimited(ice_pf_to_dev(pf),
482 				    "err:%d %s failed to update %s pin:%u\n",
483 				    ret,
484 				    ice_aq_str(pf->hw.adminq.sq_last_status),
485 				    pin_type_name[pin_type], pin->idx);
486 	return ret;
487 }
488 
489 /**
490  * ice_dpll_hw_input_prio_set - set input priority value in hardware
491  * @pf: board private structure
492  * @dpll: ice dpll pointer
493  * @pin: ice pin pointer
494  * @prio: priority value being set on a dpll
495  * @extack: error reporting
496  *
497  * Internal wrapper for setting the priority in the hardware.
498  *
499  * Context: Called under pf->dplls.lock
500  * Return:
501  * * 0 - success
502  * * negative - failure
503  */
504 static int
ice_dpll_hw_input_prio_set(struct ice_pf * pf,struct ice_dpll * dpll,struct ice_dpll_pin * pin,const u32 prio,struct netlink_ext_ack * extack)505 ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll,
506 			   struct ice_dpll_pin *pin, const u32 prio,
507 			   struct netlink_ext_ack *extack)
508 {
509 	int ret;
510 
511 	ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx,
512 				      (u8)prio);
513 	if (ret)
514 		NL_SET_ERR_MSG_FMT(extack,
515 				   "err:%d %s failed to set pin prio:%u on pin:%u\n",
516 				   ret,
517 				   ice_aq_str(pf->hw.adminq.sq_last_status),
518 				   prio, pin->idx);
519 	else
520 		dpll->input_prio[pin->idx] = prio;
521 
522 	return ret;
523 }
524 
525 /**
526  * ice_dpll_lock_status_get - get dpll lock status callback
527  * @dpll: registered dpll pointer
528  * @dpll_priv: private data pointer passed on dpll registration
529  * @status: on success holds dpll's lock status
530  * @extack: error reporting
531  *
532  * Dpll subsystem callback, provides dpll's lock status.
533  *
534  * Context: Acquires pf->dplls.lock
535  * Return:
536  * * 0 - success
537  * * negative - failure
538  */
539 static int
ice_dpll_lock_status_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_lock_status * status,struct netlink_ext_ack * extack)540 ice_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv,
541 			 enum dpll_lock_status *status,
542 			 struct netlink_ext_ack *extack)
543 {
544 	struct ice_dpll *d = dpll_priv;
545 	struct ice_pf *pf = d->pf;
546 
547 	mutex_lock(&pf->dplls.lock);
548 	*status = d->dpll_state;
549 	mutex_unlock(&pf->dplls.lock);
550 
551 	return 0;
552 }
553 
554 /**
555  * ice_dpll_mode_get - get dpll's working mode
556  * @dpll: registered dpll pointer
557  * @dpll_priv: private data pointer passed on dpll registration
558  * @mode: on success holds current working mode of dpll
559  * @extack: error reporting
560  *
561  * Dpll subsystem callback. Provides working mode of dpll.
562  *
563  * Context: Acquires pf->dplls.lock
564  * Return:
565  * * 0 - success
566  * * negative - failure
567  */
ice_dpll_mode_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)568 static int ice_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv,
569 			     enum dpll_mode *mode,
570 			     struct netlink_ext_ack *extack)
571 {
572 	struct ice_dpll *d = dpll_priv;
573 	struct ice_pf *pf = d->pf;
574 
575 	mutex_lock(&pf->dplls.lock);
576 	*mode = d->mode;
577 	mutex_unlock(&pf->dplls.lock);
578 
579 	return 0;
580 }
581 
582 /**
583  * ice_dpll_pin_state_set - set pin's state on dpll
584  * @pin: pointer to a pin
585  * @pin_priv: private data pointer passed on pin registration
586  * @dpll: registered dpll pointer
587  * @dpll_priv: private data pointer passed on dpll registration
588  * @enable: if pin shalll be enabled
589  * @extack: error reporting
590  * @pin_type: type of a pin
591  *
592  * Set pin state on a pin.
593  *
594  * Context: Acquires pf->dplls.lock
595  * Return:
596  * * 0 - OK or no change required
597  * * negative - error
598  */
599 static int
ice_dpll_pin_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,bool enable,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type)600 ice_dpll_pin_state_set(const struct dpll_pin *pin, void *pin_priv,
601 		       const struct dpll_device *dpll, void *dpll_priv,
602 		       bool enable, struct netlink_ext_ack *extack,
603 		       enum ice_dpll_pin_type pin_type)
604 {
605 	struct ice_dpll_pin *p = pin_priv;
606 	struct ice_dpll *d = dpll_priv;
607 	struct ice_pf *pf = d->pf;
608 	int ret;
609 
610 	if (ice_dpll_is_reset(pf, extack))
611 		return -EBUSY;
612 
613 	mutex_lock(&pf->dplls.lock);
614 	if (enable)
615 		ret = ice_dpll_pin_enable(&pf->hw, p, d->dpll_idx, pin_type,
616 					  extack);
617 	else
618 		ret = ice_dpll_pin_disable(&pf->hw, p, pin_type, extack);
619 	if (!ret)
620 		ret = ice_dpll_pin_state_update(pf, p, pin_type, extack);
621 	mutex_unlock(&pf->dplls.lock);
622 
623 	return ret;
624 }
625 
626 /**
627  * ice_dpll_output_state_set - enable/disable output pin on dpll device
628  * @pin: pointer to a pin
629  * @pin_priv: private data pointer passed on pin registration
630  * @dpll: dpll being configured
631  * @dpll_priv: private data pointer passed on dpll registration
632  * @state: state of pin to be set
633  * @extack: error reporting
634  *
635  * Dpll subsystem callback. Set given state on output type pin.
636  *
637  * Context: Calls a function which acquires pf->dplls.lock
638  * Return:
639  * * 0 - successfully enabled mode
640  * * negative - failed to enable mode
641  */
642 static int
ice_dpll_output_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack)643 ice_dpll_output_state_set(const struct dpll_pin *pin, void *pin_priv,
644 			  const struct dpll_device *dpll, void *dpll_priv,
645 			  enum dpll_pin_state state,
646 			  struct netlink_ext_ack *extack)
647 {
648 	bool enable = state == DPLL_PIN_STATE_CONNECTED;
649 	struct ice_dpll_pin *p = pin_priv;
650 	struct ice_dpll *d = dpll_priv;
651 
652 	if (!enable && p->state[d->dpll_idx] == DPLL_PIN_STATE_DISCONNECTED)
653 		return 0;
654 
655 	return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable,
656 				      extack, ICE_DPLL_PIN_TYPE_OUTPUT);
657 }
658 
659 /**
660  * ice_dpll_input_state_set - enable/disable input pin on dpll levice
661  * @pin: pointer to a pin
662  * @pin_priv: private data pointer passed on pin registration
663  * @dpll: dpll being configured
664  * @dpll_priv: private data pointer passed on dpll registration
665  * @state: state of pin to be set
666  * @extack: error reporting
667  *
668  * Dpll subsystem callback. Enables given mode on input type pin.
669  *
670  * Context: Calls a function which acquires pf->dplls.lock
671  * Return:
672  * * 0 - successfully enabled mode
673  * * negative - failed to enable mode
674  */
675 static int
ice_dpll_input_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack)676 ice_dpll_input_state_set(const struct dpll_pin *pin, void *pin_priv,
677 			 const struct dpll_device *dpll, void *dpll_priv,
678 			 enum dpll_pin_state state,
679 			 struct netlink_ext_ack *extack)
680 {
681 	bool enable = state == DPLL_PIN_STATE_SELECTABLE;
682 
683 	return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable,
684 				      extack, ICE_DPLL_PIN_TYPE_INPUT);
685 }
686 
687 /**
688  * ice_dpll_pin_state_get - set pin's state on dpll
689  * @pin: pointer to a pin
690  * @pin_priv: private data pointer passed on pin registration
691  * @dpll: registered dpll pointer
692  * @dpll_priv: private data pointer passed on dpll registration
693  * @state: on success holds state of the pin
694  * @extack: error reporting
695  * @pin_type: type of questioned pin
696  *
697  * Determine pin state set it on a pin.
698  *
699  * Context: Acquires pf->dplls.lock
700  * Return:
701  * * 0 - success
702  * * negative - failed to get state
703  */
704 static int
ice_dpll_pin_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type)705 ice_dpll_pin_state_get(const struct dpll_pin *pin, void *pin_priv,
706 		       const struct dpll_device *dpll, void *dpll_priv,
707 		       enum dpll_pin_state *state,
708 		       struct netlink_ext_ack *extack,
709 		       enum ice_dpll_pin_type pin_type)
710 {
711 	struct ice_dpll_pin *p = pin_priv;
712 	struct ice_dpll *d = dpll_priv;
713 	struct ice_pf *pf = d->pf;
714 	int ret;
715 
716 	if (ice_dpll_is_reset(pf, extack))
717 		return -EBUSY;
718 
719 	mutex_lock(&pf->dplls.lock);
720 	ret = ice_dpll_pin_state_update(pf, p, pin_type, extack);
721 	if (ret)
722 		goto unlock;
723 	if (pin_type == ICE_DPLL_PIN_TYPE_INPUT ||
724 	    pin_type == ICE_DPLL_PIN_TYPE_OUTPUT)
725 		*state = p->state[d->dpll_idx];
726 	ret = 0;
727 unlock:
728 	mutex_unlock(&pf->dplls.lock);
729 
730 	return ret;
731 }
732 
733 /**
734  * ice_dpll_output_state_get - get output pin state on dpll device
735  * @pin: pointer to a pin
736  * @pin_priv: private data pointer passed on pin registration
737  * @dpll: registered dpll pointer
738  * @dpll_priv: private data pointer passed on dpll registration
739  * @state: on success holds state of the pin
740  * @extack: error reporting
741  *
742  * Dpll subsystem callback. Check state of a pin.
743  *
744  * Context: Calls a function which acquires pf->dplls.lock
745  * Return:
746  * * 0 - success
747  * * negative - failed to get state
748  */
749 static int
ice_dpll_output_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)750 ice_dpll_output_state_get(const struct dpll_pin *pin, void *pin_priv,
751 			  const struct dpll_device *dpll, void *dpll_priv,
752 			  enum dpll_pin_state *state,
753 			  struct netlink_ext_ack *extack)
754 {
755 	return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state,
756 				      extack, ICE_DPLL_PIN_TYPE_OUTPUT);
757 }
758 
759 /**
760  * ice_dpll_input_state_get - get input pin state on dpll device
761  * @pin: pointer to a pin
762  * @pin_priv: private data pointer passed on pin registration
763  * @dpll: registered dpll pointer
764  * @dpll_priv: private data pointer passed on dpll registration
765  * @state: on success holds state of the pin
766  * @extack: error reporting
767  *
768  * Dpll subsystem callback. Check state of a input pin.
769  *
770  * Context: Calls a function which acquires pf->dplls.lock
771  * Return:
772  * * 0 - success
773  * * negative - failed to get state
774  */
775 static int
ice_dpll_input_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)776 ice_dpll_input_state_get(const struct dpll_pin *pin, void *pin_priv,
777 			 const struct dpll_device *dpll, void *dpll_priv,
778 			 enum dpll_pin_state *state,
779 			 struct netlink_ext_ack *extack)
780 {
781 	return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state,
782 				      extack, ICE_DPLL_PIN_TYPE_INPUT);
783 }
784 
785 /**
786  * ice_dpll_input_prio_get - get dpll's input prio
787  * @pin: pointer to a pin
788  * @pin_priv: private data pointer passed on pin registration
789  * @dpll: registered dpll pointer
790  * @dpll_priv: private data pointer passed on dpll registration
791  * @prio: on success - returns input priority on dpll
792  * @extack: error reporting
793  *
794  * Dpll subsystem callback. Handler for getting priority of a input pin.
795  *
796  * Context: Acquires pf->dplls.lock
797  * Return:
798  * * 0 - success
799  * * negative - failure
800  */
801 static int
ice_dpll_input_prio_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack)802 ice_dpll_input_prio_get(const struct dpll_pin *pin, void *pin_priv,
803 			const struct dpll_device *dpll, void *dpll_priv,
804 			u32 *prio, struct netlink_ext_ack *extack)
805 {
806 	struct ice_dpll_pin *p = pin_priv;
807 	struct ice_dpll *d = dpll_priv;
808 	struct ice_pf *pf = d->pf;
809 
810 	mutex_lock(&pf->dplls.lock);
811 	*prio = d->input_prio[p->idx];
812 	mutex_unlock(&pf->dplls.lock);
813 
814 	return 0;
815 }
816 
817 /**
818  * ice_dpll_input_prio_set - set dpll input prio
819  * @pin: pointer to a pin
820  * @pin_priv: private data pointer passed on pin registration
821  * @dpll: registered dpll pointer
822  * @dpll_priv: private data pointer passed on dpll registration
823  * @prio: input priority to be set on dpll
824  * @extack: error reporting
825  *
826  * Dpll subsystem callback. Handler for setting priority of a input pin.
827  *
828  * Context: Acquires pf->dplls.lock
829  * Return:
830  * * 0 - success
831  * * negative - failure
832  */
833 static int
ice_dpll_input_prio_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack)834 ice_dpll_input_prio_set(const struct dpll_pin *pin, void *pin_priv,
835 			const struct dpll_device *dpll, void *dpll_priv,
836 			u32 prio, struct netlink_ext_ack *extack)
837 {
838 	struct ice_dpll_pin *p = pin_priv;
839 	struct ice_dpll *d = dpll_priv;
840 	struct ice_pf *pf = d->pf;
841 	int ret;
842 
843 	if (ice_dpll_is_reset(pf, extack))
844 		return -EBUSY;
845 
846 	mutex_lock(&pf->dplls.lock);
847 	ret = ice_dpll_hw_input_prio_set(pf, d, p, prio, extack);
848 	mutex_unlock(&pf->dplls.lock);
849 
850 	return ret;
851 }
852 
853 /**
854  * ice_dpll_input_direction - callback for get input pin direction
855  * @pin: pointer to a pin
856  * @pin_priv: private data pointer passed on pin registration
857  * @dpll: registered dpll pointer
858  * @dpll_priv: private data pointer passed on dpll registration
859  * @direction: holds input pin direction
860  * @extack: error reporting
861  *
862  * Dpll subsystem callback. Handler for getting direction of a input pin.
863  *
864  * Return:
865  * * 0 - success
866  */
867 static int
ice_dpll_input_direction(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)868 ice_dpll_input_direction(const struct dpll_pin *pin, void *pin_priv,
869 			 const struct dpll_device *dpll, void *dpll_priv,
870 			 enum dpll_pin_direction *direction,
871 			 struct netlink_ext_ack *extack)
872 {
873 	*direction = DPLL_PIN_DIRECTION_INPUT;
874 
875 	return 0;
876 }
877 
878 /**
879  * ice_dpll_output_direction - callback for get output pin direction
880  * @pin: pointer to a pin
881  * @pin_priv: private data pointer passed on pin registration
882  * @dpll: registered dpll pointer
883  * @dpll_priv: private data pointer passed on dpll registration
884  * @direction: holds output pin direction
885  * @extack: error reporting
886  *
887  * Dpll subsystem callback. Handler for getting direction of an output pin.
888  *
889  * Return:
890  * * 0 - success
891  */
892 static int
ice_dpll_output_direction(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)893 ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv,
894 			  const struct dpll_device *dpll, void *dpll_priv,
895 			  enum dpll_pin_direction *direction,
896 			  struct netlink_ext_ack *extack)
897 {
898 	*direction = DPLL_PIN_DIRECTION_OUTPUT;
899 
900 	return 0;
901 }
902 
903 /**
904  * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
905  * @pin: pointer to a pin
906  * @pin_priv: private data pointer passed on pin registration
907  * @dpll: registered dpll pointer
908  * @dpll_priv: private data pointer passed on dpll registration
909  * @phase_adjust: on success holds pin phase_adjust value
910  * @extack: error reporting
911  *
912  * Dpll subsystem callback. Handler for getting phase adjust value of a pin.
913  *
914  * Context: Acquires pf->dplls.lock
915  * Return:
916  * * 0 - success
917  * * negative - error
918  */
919 static int
ice_dpll_pin_phase_adjust_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack)920 ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv,
921 			      const struct dpll_device *dpll, void *dpll_priv,
922 			      s32 *phase_adjust,
923 			      struct netlink_ext_ack *extack)
924 {
925 	struct ice_dpll_pin *p = pin_priv;
926 	struct ice_pf *pf = p->pf;
927 
928 	mutex_lock(&pf->dplls.lock);
929 	*phase_adjust = p->phase_adjust;
930 	mutex_unlock(&pf->dplls.lock);
931 
932 	return 0;
933 }
934 
935 /**
936  * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
937  * @pin: pointer to a pin
938  * @pin_priv: private data pointer passed on pin registration
939  * @dpll: registered dpll pointer
940  * @dpll_priv: private data pointer passed on dpll registration
941  * @phase_adjust: phase_adjust to be set
942  * @extack: error reporting
943  * @type: type of a pin
944  *
945  * Helper for dpll subsystem callback. Handler for setting phase adjust value
946  * of a pin.
947  *
948  * Context: Acquires pf->dplls.lock
949  * Return:
950  * * 0 - success
951  * * negative - error
952  */
953 static int
ice_dpll_pin_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack,enum ice_dpll_pin_type type)954 ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
955 			      const struct dpll_device *dpll, void *dpll_priv,
956 			      s32 phase_adjust,
957 			      struct netlink_ext_ack *extack,
958 			      enum ice_dpll_pin_type type)
959 {
960 	struct ice_dpll_pin *p = pin_priv;
961 	struct ice_dpll *d = dpll_priv;
962 	struct ice_pf *pf = d->pf;
963 	u8 flag, flags_en = 0;
964 	int ret;
965 
966 	if (ice_dpll_is_reset(pf, extack))
967 		return -EBUSY;
968 
969 	mutex_lock(&pf->dplls.lock);
970 	switch (type) {
971 	case ICE_DPLL_PIN_TYPE_INPUT:
972 		flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY;
973 		if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
974 			flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
975 		if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
976 			flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
977 		ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en,
978 					       0, phase_adjust);
979 		break;
980 	case ICE_DPLL_PIN_TYPE_OUTPUT:
981 		flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE;
982 		if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
983 			flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
984 		if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
985 			flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
986 		ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0,
987 						phase_adjust);
988 		break;
989 	default:
990 		ret = -EINVAL;
991 	}
992 	if (!ret)
993 		p->phase_adjust = phase_adjust;
994 	mutex_unlock(&pf->dplls.lock);
995 	if (ret)
996 		NL_SET_ERR_MSG_FMT(extack,
997 				   "err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u\n",
998 				   ret,
999 				   ice_aq_str(pf->hw.adminq.sq_last_status),
1000 				   phase_adjust, p->idx, d->dpll_idx);
1001 
1002 	return ret;
1003 }
1004 
1005 /**
1006  * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
1007  * @pin: pointer to a pin
1008  * @pin_priv: private data pointer passed on pin registration
1009  * @dpll: registered dpll pointer
1010  * @dpll_priv: private data pointer passed on dpll registration
1011  * @phase_adjust: phase_adjust to be set
1012  * @extack: error reporting
1013  *
1014  * Dpll subsystem callback. Wraps a handler for setting phase adjust on input
1015  * pin.
1016  *
1017  * Context: Calls a function which acquires pf->dplls.lock
1018  * Return:
1019  * * 0 - success
1020  * * negative - error
1021  */
1022 static int
ice_dpll_input_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack)1023 ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
1024 				const struct dpll_device *dpll, void *dpll_priv,
1025 				s32 phase_adjust,
1026 				struct netlink_ext_ack *extack)
1027 {
1028 	return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
1029 					     phase_adjust, extack,
1030 					     ICE_DPLL_PIN_TYPE_INPUT);
1031 }
1032 
1033 /**
1034  * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
1035  * @pin: pointer to a pin
1036  * @pin_priv: private data pointer passed on pin registration
1037  * @dpll: registered dpll pointer
1038  * @dpll_priv: private data pointer passed on dpll registration
1039  * @phase_adjust: phase_adjust to be set
1040  * @extack: error reporting
1041  *
1042  * Dpll subsystem callback. Wraps a handler for setting phase adjust on output
1043  * pin.
1044  *
1045  * Context: Calls a function which acquires pf->dplls.lock
1046  * Return:
1047  * * 0 - success
1048  * * negative - error
1049  */
1050 static int
ice_dpll_output_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack)1051 ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
1052 				 const struct dpll_device *dpll, void *dpll_priv,
1053 				 s32 phase_adjust,
1054 				 struct netlink_ext_ack *extack)
1055 {
1056 	return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
1057 					     phase_adjust, extack,
1058 					     ICE_DPLL_PIN_TYPE_OUTPUT);
1059 }
1060 
1061 #define ICE_DPLL_PHASE_OFFSET_DIVIDER	100
1062 #define ICE_DPLL_PHASE_OFFSET_FACTOR		\
1063 	(DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER)
1064 /**
1065  * ice_dpll_phase_offset_get - callback for get dpll phase shift value
1066  * @pin: pointer to a pin
1067  * @pin_priv: private data pointer passed on pin registration
1068  * @dpll: registered dpll pointer
1069  * @dpll_priv: private data pointer passed on dpll registration
1070  * @phase_offset: on success holds pin phase_offset value
1071  * @extack: error reporting
1072  *
1073  * Dpll subsystem callback. Handler for getting phase shift value between
1074  * dpll's input and output.
1075  *
1076  * Context: Acquires pf->dplls.lock
1077  * Return:
1078  * * 0 - success
1079  * * negative - error
1080  */
1081 static int
ice_dpll_phase_offset_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * phase_offset,struct netlink_ext_ack * extack)1082 ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
1083 			  const struct dpll_device *dpll, void *dpll_priv,
1084 			  s64 *phase_offset, struct netlink_ext_ack *extack)
1085 {
1086 	struct ice_dpll *d = dpll_priv;
1087 	struct ice_pf *pf = d->pf;
1088 
1089 	mutex_lock(&pf->dplls.lock);
1090 	if (d->active_input == pin)
1091 		*phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
1092 	else
1093 		*phase_offset = 0;
1094 	mutex_unlock(&pf->dplls.lock);
1095 
1096 	return 0;
1097 }
1098 
1099 /**
1100  * ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
1101  * @pin: pointer to a pin
1102  * @pin_priv: private data pointer passed on pin registration
1103  * @parent_pin: pin parent pointer
1104  * @parent_pin_priv: parent private data pointer passed on pin registration
1105  * @state: state to be set on pin
1106  * @extack: error reporting
1107  *
1108  * Dpll subsystem callback, set a state of a rclk pin on a parent pin
1109  *
1110  * Context: Acquires pf->dplls.lock
1111  * Return:
1112  * * 0 - success
1113  * * negative - failure
1114  */
1115 static int
ice_dpll_rclk_state_on_pin_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_pin * parent_pin,void * parent_pin_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack)1116 ice_dpll_rclk_state_on_pin_set(const struct dpll_pin *pin, void *pin_priv,
1117 			       const struct dpll_pin *parent_pin,
1118 			       void *parent_pin_priv,
1119 			       enum dpll_pin_state state,
1120 			       struct netlink_ext_ack *extack)
1121 {
1122 	struct ice_dpll_pin *p = pin_priv, *parent = parent_pin_priv;
1123 	bool enable = state == DPLL_PIN_STATE_CONNECTED;
1124 	struct ice_pf *pf = p->pf;
1125 	int ret = -EINVAL;
1126 	u32 hw_idx;
1127 
1128 	if (ice_dpll_is_reset(pf, extack))
1129 		return -EBUSY;
1130 
1131 	mutex_lock(&pf->dplls.lock);
1132 	hw_idx = parent->idx - pf->dplls.base_rclk_idx;
1133 	if (hw_idx >= pf->dplls.num_inputs)
1134 		goto unlock;
1135 
1136 	if ((enable && p->state[hw_idx] == DPLL_PIN_STATE_CONNECTED) ||
1137 	    (!enable && p->state[hw_idx] == DPLL_PIN_STATE_DISCONNECTED)) {
1138 		NL_SET_ERR_MSG_FMT(extack,
1139 				   "pin:%u state:%u on parent:%u already set",
1140 				   p->idx, state, parent->idx);
1141 		goto unlock;
1142 	}
1143 	ret = ice_aq_set_phy_rec_clk_out(&pf->hw, hw_idx, enable,
1144 					 &p->freq);
1145 	if (ret)
1146 		NL_SET_ERR_MSG_FMT(extack,
1147 				   "err:%d %s failed to set pin state:%u for pin:%u on parent:%u\n",
1148 				   ret,
1149 				   ice_aq_str(pf->hw.adminq.sq_last_status),
1150 				   state, p->idx, parent->idx);
1151 unlock:
1152 	mutex_unlock(&pf->dplls.lock);
1153 
1154 	return ret;
1155 }
1156 
1157 /**
1158  * ice_dpll_rclk_state_on_pin_get - get a state of rclk pin
1159  * @pin: pointer to a pin
1160  * @pin_priv: private data pointer passed on pin registration
1161  * @parent_pin: pin parent pointer
1162  * @parent_pin_priv: pin parent priv data pointer passed on pin registration
1163  * @state: on success holds pin state on parent pin
1164  * @extack: error reporting
1165  *
1166  * dpll subsystem callback, get a state of a recovered clock pin.
1167  *
1168  * Context: Acquires pf->dplls.lock
1169  * Return:
1170  * * 0 - success
1171  * * negative - failure
1172  */
1173 static int
ice_dpll_rclk_state_on_pin_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_pin * parent_pin,void * parent_pin_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)1174 ice_dpll_rclk_state_on_pin_get(const struct dpll_pin *pin, void *pin_priv,
1175 			       const struct dpll_pin *parent_pin,
1176 			       void *parent_pin_priv,
1177 			       enum dpll_pin_state *state,
1178 			       struct netlink_ext_ack *extack)
1179 {
1180 	struct ice_dpll_pin *p = pin_priv, *parent = parent_pin_priv;
1181 	struct ice_pf *pf = p->pf;
1182 	int ret = -EINVAL;
1183 	u32 hw_idx;
1184 
1185 	if (ice_dpll_is_reset(pf, extack))
1186 		return -EBUSY;
1187 
1188 	mutex_lock(&pf->dplls.lock);
1189 	hw_idx = parent->idx - pf->dplls.base_rclk_idx;
1190 	if (hw_idx >= pf->dplls.num_inputs)
1191 		goto unlock;
1192 
1193 	ret = ice_dpll_pin_state_update(pf, p, ICE_DPLL_PIN_TYPE_RCLK_INPUT,
1194 					extack);
1195 	if (ret)
1196 		goto unlock;
1197 
1198 	*state = p->state[hw_idx];
1199 	ret = 0;
1200 unlock:
1201 	mutex_unlock(&pf->dplls.lock);
1202 
1203 	return ret;
1204 }
1205 
1206 static const struct dpll_pin_ops ice_dpll_rclk_ops = {
1207 	.state_on_pin_set = ice_dpll_rclk_state_on_pin_set,
1208 	.state_on_pin_get = ice_dpll_rclk_state_on_pin_get,
1209 	.direction_get = ice_dpll_input_direction,
1210 };
1211 
1212 static const struct dpll_pin_ops ice_dpll_input_ops = {
1213 	.frequency_get = ice_dpll_input_frequency_get,
1214 	.frequency_set = ice_dpll_input_frequency_set,
1215 	.state_on_dpll_get = ice_dpll_input_state_get,
1216 	.state_on_dpll_set = ice_dpll_input_state_set,
1217 	.prio_get = ice_dpll_input_prio_get,
1218 	.prio_set = ice_dpll_input_prio_set,
1219 	.direction_get = ice_dpll_input_direction,
1220 	.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
1221 	.phase_adjust_set = ice_dpll_input_phase_adjust_set,
1222 	.phase_offset_get = ice_dpll_phase_offset_get,
1223 };
1224 
1225 static const struct dpll_pin_ops ice_dpll_output_ops = {
1226 	.frequency_get = ice_dpll_output_frequency_get,
1227 	.frequency_set = ice_dpll_output_frequency_set,
1228 	.state_on_dpll_get = ice_dpll_output_state_get,
1229 	.state_on_dpll_set = ice_dpll_output_state_set,
1230 	.direction_get = ice_dpll_output_direction,
1231 	.phase_adjust_get = ice_dpll_pin_phase_adjust_get,
1232 	.phase_adjust_set = ice_dpll_output_phase_adjust_set,
1233 };
1234 
1235 static const struct dpll_device_ops ice_dpll_ops = {
1236 	.lock_status_get = ice_dpll_lock_status_get,
1237 	.mode_get = ice_dpll_mode_get,
1238 };
1239 
1240 /**
1241  * ice_generate_clock_id - generates unique clock_id for registering dpll.
1242  * @pf: board private structure
1243  *
1244  * Generates unique (per board) clock_id for allocation and search of dpll
1245  * devices in Linux dpll subsystem.
1246  *
1247  * Return: generated clock id for the board
1248  */
ice_generate_clock_id(struct ice_pf * pf)1249 static u64 ice_generate_clock_id(struct ice_pf *pf)
1250 {
1251 	return pci_get_dsn(pf->pdev);
1252 }
1253 
1254 /**
1255  * ice_dpll_notify_changes - notify dpll subsystem about changes
1256  * @d: pointer do dpll
1257  *
1258  * Once change detected appropriate event is submitted to the dpll subsystem.
1259  */
ice_dpll_notify_changes(struct ice_dpll * d)1260 static void ice_dpll_notify_changes(struct ice_dpll *d)
1261 {
1262 	bool pin_notified = false;
1263 
1264 	if (d->prev_dpll_state != d->dpll_state) {
1265 		d->prev_dpll_state = d->dpll_state;
1266 		dpll_device_change_ntf(d->dpll);
1267 	}
1268 	if (d->prev_input != d->active_input) {
1269 		if (d->prev_input)
1270 			dpll_pin_change_ntf(d->prev_input);
1271 		d->prev_input = d->active_input;
1272 		if (d->active_input) {
1273 			dpll_pin_change_ntf(d->active_input);
1274 			pin_notified = true;
1275 		}
1276 	}
1277 	if (d->prev_phase_offset != d->phase_offset) {
1278 		d->prev_phase_offset = d->phase_offset;
1279 		if (!pin_notified && d->active_input)
1280 			dpll_pin_change_ntf(d->active_input);
1281 	}
1282 }
1283 
1284 /**
1285  * ice_dpll_update_state - update dpll state
1286  * @pf: pf private structure
1287  * @d: pointer to queried dpll device
1288  * @init: if function called on initialization of ice dpll
1289  *
1290  * Poll current state of dpll from hw and update ice_dpll struct.
1291  *
1292  * Context: Called by kworker under pf->dplls.lock
1293  * Return:
1294  * * 0 - success
1295  * * negative - AQ failure
1296  */
1297 static int
ice_dpll_update_state(struct ice_pf * pf,struct ice_dpll * d,bool init)1298 ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
1299 {
1300 	struct ice_dpll_pin *p = NULL;
1301 	int ret;
1302 
1303 	ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state,
1304 				&d->input_idx, &d->ref_state, &d->eec_mode,
1305 				&d->phase_offset, &d->dpll_state);
1306 
1307 	dev_dbg(ice_pf_to_dev(pf),
1308 		"update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n",
1309 		d->dpll_idx, d->prev_input_idx, d->input_idx,
1310 		d->dpll_state, d->prev_dpll_state, d->mode);
1311 	if (ret) {
1312 		dev_err(ice_pf_to_dev(pf),
1313 			"update dpll=%d state failed, ret=%d %s\n",
1314 			d->dpll_idx, ret,
1315 			ice_aq_str(pf->hw.adminq.sq_last_status));
1316 		return ret;
1317 	}
1318 	if (init) {
1319 		if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED ||
1320 		    d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ)
1321 			d->active_input = pf->dplls.inputs[d->input_idx].pin;
1322 		p = &pf->dplls.inputs[d->input_idx];
1323 		return ice_dpll_pin_state_update(pf, p,
1324 						 ICE_DPLL_PIN_TYPE_INPUT, NULL);
1325 	}
1326 	if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER ||
1327 	    d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) {
1328 		d->active_input = NULL;
1329 		if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID)
1330 			p = &pf->dplls.inputs[d->input_idx];
1331 		d->prev_input_idx = ICE_DPLL_PIN_IDX_INVALID;
1332 		d->input_idx = ICE_DPLL_PIN_IDX_INVALID;
1333 		if (!p)
1334 			return 0;
1335 		ret = ice_dpll_pin_state_update(pf, p,
1336 						ICE_DPLL_PIN_TYPE_INPUT, NULL);
1337 	} else if (d->input_idx != d->prev_input_idx) {
1338 		if (d->prev_input_idx != ICE_DPLL_PIN_IDX_INVALID) {
1339 			p = &pf->dplls.inputs[d->prev_input_idx];
1340 			ice_dpll_pin_state_update(pf, p,
1341 						  ICE_DPLL_PIN_TYPE_INPUT,
1342 						  NULL);
1343 		}
1344 		if (d->input_idx != ICE_DPLL_PIN_IDX_INVALID) {
1345 			p = &pf->dplls.inputs[d->input_idx];
1346 			d->active_input = p->pin;
1347 			ice_dpll_pin_state_update(pf, p,
1348 						  ICE_DPLL_PIN_TYPE_INPUT,
1349 						  NULL);
1350 		}
1351 		d->prev_input_idx = d->input_idx;
1352 	}
1353 
1354 	return ret;
1355 }
1356 
1357 /**
1358  * ice_dpll_periodic_work - DPLLs periodic worker
1359  * @work: pointer to kthread_work structure
1360  *
1361  * DPLLs periodic worker is responsible for polling state of dpll.
1362  * Context: Holds pf->dplls.lock
1363  */
ice_dpll_periodic_work(struct kthread_work * work)1364 static void ice_dpll_periodic_work(struct kthread_work *work)
1365 {
1366 	struct ice_dplls *d = container_of(work, struct ice_dplls, work.work);
1367 	struct ice_pf *pf = container_of(d, struct ice_pf, dplls);
1368 	struct ice_dpll *de = &pf->dplls.eec;
1369 	struct ice_dpll *dp = &pf->dplls.pps;
1370 	int ret = 0;
1371 
1372 	if (ice_is_reset_in_progress(pf->state))
1373 		goto resched;
1374 	mutex_lock(&pf->dplls.lock);
1375 	ret = ice_dpll_update_state(pf, de, false);
1376 	if (!ret)
1377 		ret = ice_dpll_update_state(pf, dp, false);
1378 	if (ret) {
1379 		d->cgu_state_acq_err_num++;
1380 		/* stop rescheduling this worker */
1381 		if (d->cgu_state_acq_err_num >
1382 		    ICE_CGU_STATE_ACQ_ERR_THRESHOLD) {
1383 			dev_err(ice_pf_to_dev(pf),
1384 				"EEC/PPS DPLLs periodic work disabled\n");
1385 			mutex_unlock(&pf->dplls.lock);
1386 			return;
1387 		}
1388 	}
1389 	mutex_unlock(&pf->dplls.lock);
1390 	ice_dpll_notify_changes(de);
1391 	ice_dpll_notify_changes(dp);
1392 
1393 resched:
1394 	/* Run twice a second or reschedule if update failed */
1395 	kthread_queue_delayed_work(d->kworker, &d->work,
1396 				   ret ? msecs_to_jiffies(10) :
1397 				   msecs_to_jiffies(500));
1398 }
1399 
1400 /**
1401  * ice_dpll_release_pins - release pins resources from dpll subsystem
1402  * @pins: pointer to pins array
1403  * @count: number of pins
1404  *
1405  * Release resources of given pins array in the dpll subsystem.
1406  */
ice_dpll_release_pins(struct ice_dpll_pin * pins,int count)1407 static void ice_dpll_release_pins(struct ice_dpll_pin *pins, int count)
1408 {
1409 	int i;
1410 
1411 	for (i = 0; i < count; i++)
1412 		dpll_pin_put(pins[i].pin);
1413 }
1414 
1415 /**
1416  * ice_dpll_get_pins - get pins from dpll subsystem
1417  * @pf: board private structure
1418  * @pins: pointer to pins array
1419  * @start_idx: get starts from this pin idx value
1420  * @count: number of pins
1421  * @clock_id: clock_id of dpll device
1422  *
1423  * Get pins - allocate - in dpll subsystem, store them in pin field of given
1424  * pins array.
1425  *
1426  * Return:
1427  * * 0 - success
1428  * * negative - allocation failure reason
1429  */
1430 static int
ice_dpll_get_pins(struct ice_pf * pf,struct ice_dpll_pin * pins,int start_idx,int count,u64 clock_id)1431 ice_dpll_get_pins(struct ice_pf *pf, struct ice_dpll_pin *pins,
1432 		  int start_idx, int count, u64 clock_id)
1433 {
1434 	int i, ret;
1435 
1436 	for (i = 0; i < count; i++) {
1437 		pins[i].pin = dpll_pin_get(clock_id, i + start_idx, THIS_MODULE,
1438 					   &pins[i].prop);
1439 		if (IS_ERR(pins[i].pin)) {
1440 			ret = PTR_ERR(pins[i].pin);
1441 			goto release_pins;
1442 		}
1443 	}
1444 
1445 	return 0;
1446 
1447 release_pins:
1448 	while (--i >= 0)
1449 		dpll_pin_put(pins[i].pin);
1450 	return ret;
1451 }
1452 
1453 /**
1454  * ice_dpll_unregister_pins - unregister pins from a dpll
1455  * @dpll: dpll device pointer
1456  * @pins: pointer to pins array
1457  * @ops: callback ops registered with the pins
1458  * @count: number of pins
1459  *
1460  * Unregister pins of a given array of pins from given dpll device registered in
1461  * dpll subsystem.
1462  */
1463 static void
ice_dpll_unregister_pins(struct dpll_device * dpll,struct ice_dpll_pin * pins,const struct dpll_pin_ops * ops,int count)1464 ice_dpll_unregister_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins,
1465 			 const struct dpll_pin_ops *ops, int count)
1466 {
1467 	int i;
1468 
1469 	for (i = 0; i < count; i++)
1470 		dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]);
1471 }
1472 
1473 /**
1474  * ice_dpll_register_pins - register pins with a dpll
1475  * @dpll: dpll pointer to register pins with
1476  * @pins: pointer to pins array
1477  * @ops: callback ops registered with the pins
1478  * @count: number of pins
1479  *
1480  * Register pins of a given array with given dpll in dpll subsystem.
1481  *
1482  * Return:
1483  * * 0 - success
1484  * * negative - registration failure reason
1485  */
1486 static int
ice_dpll_register_pins(struct dpll_device * dpll,struct ice_dpll_pin * pins,const struct dpll_pin_ops * ops,int count)1487 ice_dpll_register_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins,
1488 		       const struct dpll_pin_ops *ops, int count)
1489 {
1490 	int ret, i;
1491 
1492 	for (i = 0; i < count; i++) {
1493 		ret = dpll_pin_register(dpll, pins[i].pin, ops, &pins[i]);
1494 		if (ret)
1495 			goto unregister_pins;
1496 	}
1497 
1498 	return 0;
1499 
1500 unregister_pins:
1501 	while (--i >= 0)
1502 		dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]);
1503 	return ret;
1504 }
1505 
1506 /**
1507  * ice_dpll_deinit_direct_pins - deinitialize direct pins
1508  * @cgu: if cgu is present and controlled by this NIC
1509  * @pins: pointer to pins array
1510  * @count: number of pins
1511  * @ops: callback ops registered with the pins
1512  * @first: dpll device pointer
1513  * @second: dpll device pointer
1514  *
1515  * If cgu is owned unregister pins from given dplls.
1516  * Release pins resources to the dpll subsystem.
1517  */
1518 static void
ice_dpll_deinit_direct_pins(bool cgu,struct ice_dpll_pin * pins,int count,const struct dpll_pin_ops * ops,struct dpll_device * first,struct dpll_device * second)1519 ice_dpll_deinit_direct_pins(bool cgu, struct ice_dpll_pin *pins, int count,
1520 			    const struct dpll_pin_ops *ops,
1521 			    struct dpll_device *first,
1522 			    struct dpll_device *second)
1523 {
1524 	if (cgu) {
1525 		ice_dpll_unregister_pins(first, pins, ops, count);
1526 		ice_dpll_unregister_pins(second, pins, ops, count);
1527 	}
1528 	ice_dpll_release_pins(pins, count);
1529 }
1530 
1531 /**
1532  * ice_dpll_init_direct_pins - initialize direct pins
1533  * @pf: board private structure
1534  * @cgu: if cgu is present and controlled by this NIC
1535  * @pins: pointer to pins array
1536  * @start_idx: on which index shall allocation start in dpll subsystem
1537  * @count: number of pins
1538  * @ops: callback ops registered with the pins
1539  * @first: dpll device pointer
1540  * @second: dpll device pointer
1541  *
1542  * Allocate directly connected pins of a given array in dpll subsystem.
1543  * If cgu is owned register allocated pins with given dplls.
1544  *
1545  * Return:
1546  * * 0 - success
1547  * * negative - registration failure reason
1548  */
1549 static int
ice_dpll_init_direct_pins(struct ice_pf * pf,bool cgu,struct ice_dpll_pin * pins,int start_idx,int count,const struct dpll_pin_ops * ops,struct dpll_device * first,struct dpll_device * second)1550 ice_dpll_init_direct_pins(struct ice_pf *pf, bool cgu,
1551 			  struct ice_dpll_pin *pins, int start_idx, int count,
1552 			  const struct dpll_pin_ops *ops,
1553 			  struct dpll_device *first, struct dpll_device *second)
1554 {
1555 	int ret;
1556 
1557 	ret = ice_dpll_get_pins(pf, pins, start_idx, count, pf->dplls.clock_id);
1558 	if (ret)
1559 		return ret;
1560 	if (cgu) {
1561 		ret = ice_dpll_register_pins(first, pins, ops, count);
1562 		if (ret)
1563 			goto release_pins;
1564 		ret = ice_dpll_register_pins(second, pins, ops, count);
1565 		if (ret)
1566 			goto unregister_first;
1567 	}
1568 
1569 	return 0;
1570 
1571 unregister_first:
1572 	ice_dpll_unregister_pins(first, pins, ops, count);
1573 release_pins:
1574 	ice_dpll_release_pins(pins, count);
1575 	return ret;
1576 }
1577 
1578 /**
1579  * ice_dpll_deinit_rclk_pin - release rclk pin resources
1580  * @pf: board private structure
1581  *
1582  * Deregister rclk pin from parent pins and release resources in dpll subsystem.
1583  */
ice_dpll_deinit_rclk_pin(struct ice_pf * pf)1584 static void ice_dpll_deinit_rclk_pin(struct ice_pf *pf)
1585 {
1586 	struct ice_dpll_pin *rclk = &pf->dplls.rclk;
1587 	struct ice_vsi *vsi = ice_get_main_vsi(pf);
1588 	struct dpll_pin *parent;
1589 	int i;
1590 
1591 	for (i = 0; i < rclk->num_parents; i++) {
1592 		parent = pf->dplls.inputs[rclk->parent_idx[i]].pin;
1593 		if (!parent)
1594 			continue;
1595 		dpll_pin_on_pin_unregister(parent, rclk->pin,
1596 					   &ice_dpll_rclk_ops, rclk);
1597 	}
1598 	if (WARN_ON_ONCE(!vsi || !vsi->netdev))
1599 		return;
1600 	dpll_netdev_pin_clear(vsi->netdev);
1601 	dpll_pin_put(rclk->pin);
1602 }
1603 
1604 /**
1605  * ice_dpll_init_rclk_pins - initialize recovered clock pin
1606  * @pf: board private structure
1607  * @pin: pin to register
1608  * @start_idx: on which index shall allocation start in dpll subsystem
1609  * @ops: callback ops registered with the pins
1610  *
1611  * Allocate resource for recovered clock pin in dpll subsystem. Register the
1612  * pin with the parents it has in the info. Register pin with the pf's main vsi
1613  * netdev.
1614  *
1615  * Return:
1616  * * 0 - success
1617  * * negative - registration failure reason
1618  */
1619 static int
ice_dpll_init_rclk_pins(struct ice_pf * pf,struct ice_dpll_pin * pin,int start_idx,const struct dpll_pin_ops * ops)1620 ice_dpll_init_rclk_pins(struct ice_pf *pf, struct ice_dpll_pin *pin,
1621 			int start_idx, const struct dpll_pin_ops *ops)
1622 {
1623 	struct ice_vsi *vsi = ice_get_main_vsi(pf);
1624 	struct dpll_pin *parent;
1625 	int ret, i;
1626 
1627 	ret = ice_dpll_get_pins(pf, pin, start_idx, ICE_DPLL_RCLK_NUM_PER_PF,
1628 				pf->dplls.clock_id);
1629 	if (ret)
1630 		return ret;
1631 	for (i = 0; i < pf->dplls.rclk.num_parents; i++) {
1632 		parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[i]].pin;
1633 		if (!parent) {
1634 			ret = -ENODEV;
1635 			goto unregister_pins;
1636 		}
1637 		ret = dpll_pin_on_pin_register(parent, pf->dplls.rclk.pin,
1638 					       ops, &pf->dplls.rclk);
1639 		if (ret)
1640 			goto unregister_pins;
1641 	}
1642 	if (WARN_ON((!vsi || !vsi->netdev)))
1643 		return -EINVAL;
1644 	dpll_netdev_pin_set(vsi->netdev, pf->dplls.rclk.pin);
1645 
1646 	return 0;
1647 
1648 unregister_pins:
1649 	while (i) {
1650 		parent = pf->dplls.inputs[pf->dplls.rclk.parent_idx[--i]].pin;
1651 		dpll_pin_on_pin_unregister(parent, pf->dplls.rclk.pin,
1652 					   &ice_dpll_rclk_ops, &pf->dplls.rclk);
1653 	}
1654 	ice_dpll_release_pins(pin, ICE_DPLL_RCLK_NUM_PER_PF);
1655 	return ret;
1656 }
1657 
1658 /**
1659  * ice_dpll_deinit_pins - deinitialize direct pins
1660  * @pf: board private structure
1661  * @cgu: if cgu is controlled by this pf
1662  *
1663  * If cgu is owned unregister directly connected pins from the dplls.
1664  * Release resources of directly connected pins from the dpll subsystem.
1665  */
ice_dpll_deinit_pins(struct ice_pf * pf,bool cgu)1666 static void ice_dpll_deinit_pins(struct ice_pf *pf, bool cgu)
1667 {
1668 	struct ice_dpll_pin *outputs = pf->dplls.outputs;
1669 	struct ice_dpll_pin *inputs = pf->dplls.inputs;
1670 	int num_outputs = pf->dplls.num_outputs;
1671 	int num_inputs = pf->dplls.num_inputs;
1672 	struct ice_dplls *d = &pf->dplls;
1673 	struct ice_dpll *de = &d->eec;
1674 	struct ice_dpll *dp = &d->pps;
1675 
1676 	ice_dpll_deinit_rclk_pin(pf);
1677 	if (cgu) {
1678 		ice_dpll_unregister_pins(dp->dpll, inputs, &ice_dpll_input_ops,
1679 					 num_inputs);
1680 		ice_dpll_unregister_pins(de->dpll, inputs, &ice_dpll_input_ops,
1681 					 num_inputs);
1682 	}
1683 	ice_dpll_release_pins(inputs, num_inputs);
1684 	if (cgu) {
1685 		ice_dpll_unregister_pins(dp->dpll, outputs,
1686 					 &ice_dpll_output_ops, num_outputs);
1687 		ice_dpll_unregister_pins(de->dpll, outputs,
1688 					 &ice_dpll_output_ops, num_outputs);
1689 		ice_dpll_release_pins(outputs, num_outputs);
1690 	}
1691 }
1692 
1693 /**
1694  * ice_dpll_init_pins - init pins and register pins with a dplls
1695  * @pf: board private structure
1696  * @cgu: if cgu is present and controlled by this NIC
1697  *
1698  * Initialize directly connected pf's pins within pf's dplls in a Linux dpll
1699  * subsystem.
1700  *
1701  * Return:
1702  * * 0 - success
1703  * * negative - initialization failure reason
1704  */
ice_dpll_init_pins(struct ice_pf * pf,bool cgu)1705 static int ice_dpll_init_pins(struct ice_pf *pf, bool cgu)
1706 {
1707 	u32 rclk_idx;
1708 	int ret;
1709 
1710 	ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.inputs, 0,
1711 					pf->dplls.num_inputs,
1712 					&ice_dpll_input_ops,
1713 					pf->dplls.eec.dpll, pf->dplls.pps.dpll);
1714 	if (ret)
1715 		return ret;
1716 	if (cgu) {
1717 		ret = ice_dpll_init_direct_pins(pf, cgu, pf->dplls.outputs,
1718 						pf->dplls.num_inputs,
1719 						pf->dplls.num_outputs,
1720 						&ice_dpll_output_ops,
1721 						pf->dplls.eec.dpll,
1722 						pf->dplls.pps.dpll);
1723 		if (ret)
1724 			goto deinit_inputs;
1725 	}
1726 	rclk_idx = pf->dplls.num_inputs + pf->dplls.num_outputs + pf->hw.pf_id;
1727 	ret = ice_dpll_init_rclk_pins(pf, &pf->dplls.rclk, rclk_idx,
1728 				      &ice_dpll_rclk_ops);
1729 	if (ret)
1730 		goto deinit_outputs;
1731 
1732 	return 0;
1733 deinit_outputs:
1734 	ice_dpll_deinit_direct_pins(cgu, pf->dplls.outputs,
1735 				    pf->dplls.num_outputs,
1736 				    &ice_dpll_output_ops, pf->dplls.pps.dpll,
1737 				    pf->dplls.eec.dpll);
1738 deinit_inputs:
1739 	ice_dpll_deinit_direct_pins(cgu, pf->dplls.inputs, pf->dplls.num_inputs,
1740 				    &ice_dpll_input_ops, pf->dplls.pps.dpll,
1741 				    pf->dplls.eec.dpll);
1742 	return ret;
1743 }
1744 
1745 /**
1746  * ice_dpll_deinit_dpll - deinitialize dpll device
1747  * @pf: board private structure
1748  * @d: pointer to ice_dpll
1749  * @cgu: if cgu is present and controlled by this NIC
1750  *
1751  * If cgu is owned unregister the dpll from dpll subsystem.
1752  * Release resources of dpll device from dpll subsystem.
1753  */
1754 static void
ice_dpll_deinit_dpll(struct ice_pf * pf,struct ice_dpll * d,bool cgu)1755 ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu)
1756 {
1757 	if (cgu)
1758 		dpll_device_unregister(d->dpll, &ice_dpll_ops, d);
1759 	dpll_device_put(d->dpll);
1760 }
1761 
1762 /**
1763  * ice_dpll_init_dpll - initialize dpll device in dpll subsystem
1764  * @pf: board private structure
1765  * @d: dpll to be initialized
1766  * @cgu: if cgu is present and controlled by this NIC
1767  * @type: type of dpll being initialized
1768  *
1769  * Allocate dpll instance for this board in dpll subsystem, if cgu is controlled
1770  * by this NIC, register dpll with the callback ops.
1771  *
1772  * Return:
1773  * * 0 - success
1774  * * negative - initialization failure reason
1775  */
1776 static int
ice_dpll_init_dpll(struct ice_pf * pf,struct ice_dpll * d,bool cgu,enum dpll_type type)1777 ice_dpll_init_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu,
1778 		   enum dpll_type type)
1779 {
1780 	u64 clock_id = pf->dplls.clock_id;
1781 	int ret;
1782 
1783 	d->dpll = dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE);
1784 	if (IS_ERR(d->dpll)) {
1785 		ret = PTR_ERR(d->dpll);
1786 		dev_err(ice_pf_to_dev(pf),
1787 			"dpll_device_get failed (%p) err=%d\n", d, ret);
1788 		return ret;
1789 	}
1790 	d->pf = pf;
1791 	if (cgu) {
1792 		ice_dpll_update_state(pf, d, true);
1793 		ret = dpll_device_register(d->dpll, type, &ice_dpll_ops, d);
1794 		if (ret) {
1795 			dpll_device_put(d->dpll);
1796 			return ret;
1797 		}
1798 	}
1799 
1800 	return 0;
1801 }
1802 
1803 /**
1804  * ice_dpll_deinit_worker - deinitialize dpll kworker
1805  * @pf: board private structure
1806  *
1807  * Stop dpll's kworker, release it's resources.
1808  */
ice_dpll_deinit_worker(struct ice_pf * pf)1809 static void ice_dpll_deinit_worker(struct ice_pf *pf)
1810 {
1811 	struct ice_dplls *d = &pf->dplls;
1812 
1813 	kthread_cancel_delayed_work_sync(&d->work);
1814 	kthread_destroy_worker(d->kworker);
1815 }
1816 
1817 /**
1818  * ice_dpll_init_worker - Initialize DPLLs periodic worker
1819  * @pf: board private structure
1820  *
1821  * Create and start DPLLs periodic worker.
1822  *
1823  * Context: Shall be called after pf->dplls.lock is initialized.
1824  * Return:
1825  * * 0 - success
1826  * * negative - create worker failure
1827  */
ice_dpll_init_worker(struct ice_pf * pf)1828 static int ice_dpll_init_worker(struct ice_pf *pf)
1829 {
1830 	struct ice_dplls *d = &pf->dplls;
1831 	struct kthread_worker *kworker;
1832 
1833 	kthread_init_delayed_work(&d->work, ice_dpll_periodic_work);
1834 	kworker = kthread_create_worker(0, "ice-dplls-%s",
1835 					dev_name(ice_pf_to_dev(pf)));
1836 	if (IS_ERR(kworker))
1837 		return PTR_ERR(kworker);
1838 	d->kworker = kworker;
1839 	d->cgu_state_acq_err_num = 0;
1840 	kthread_queue_delayed_work(d->kworker, &d->work, 0);
1841 
1842 	return 0;
1843 }
1844 
1845 /**
1846  * ice_dpll_init_info_direct_pins - initializes direct pins info
1847  * @pf: board private structure
1848  * @pin_type: type of pins being initialized
1849  *
1850  * Init information for directly connected pins, cache them in pf's pins
1851  * structures.
1852  *
1853  * Return:
1854  * * 0 - success
1855  * * negative - init failure reason
1856  */
1857 static int
ice_dpll_init_info_direct_pins(struct ice_pf * pf,enum ice_dpll_pin_type pin_type)1858 ice_dpll_init_info_direct_pins(struct ice_pf *pf,
1859 			       enum ice_dpll_pin_type pin_type)
1860 {
1861 	struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps;
1862 	int num_pins, i, ret = -EINVAL;
1863 	struct ice_hw *hw = &pf->hw;
1864 	struct ice_dpll_pin *pins;
1865 	unsigned long caps;
1866 	u8 freq_supp_num;
1867 	bool input;
1868 
1869 	switch (pin_type) {
1870 	case ICE_DPLL_PIN_TYPE_INPUT:
1871 		pins = pf->dplls.inputs;
1872 		num_pins = pf->dplls.num_inputs;
1873 		input = true;
1874 		break;
1875 	case ICE_DPLL_PIN_TYPE_OUTPUT:
1876 		pins = pf->dplls.outputs;
1877 		num_pins = pf->dplls.num_outputs;
1878 		input = false;
1879 		break;
1880 	default:
1881 		return -EINVAL;
1882 	}
1883 
1884 	for (i = 0; i < num_pins; i++) {
1885 		caps = 0;
1886 		pins[i].idx = i;
1887 		pins[i].prop.board_label = ice_cgu_get_pin_name(hw, i, input);
1888 		pins[i].prop.type = ice_cgu_get_pin_type(hw, i, input);
1889 		if (input) {
1890 			ret = ice_aq_get_cgu_ref_prio(hw, de->dpll_idx, i,
1891 						      &de->input_prio[i]);
1892 			if (ret)
1893 				return ret;
1894 			ret = ice_aq_get_cgu_ref_prio(hw, dp->dpll_idx, i,
1895 						      &dp->input_prio[i]);
1896 			if (ret)
1897 				return ret;
1898 			caps |= (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE |
1899 				 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE);
1900 			pins[i].prop.phase_range.min =
1901 				pf->dplls.input_phase_adj_max;
1902 			pins[i].prop.phase_range.max =
1903 				-pf->dplls.input_phase_adj_max;
1904 		} else {
1905 			pins[i].prop.phase_range.min =
1906 				pf->dplls.output_phase_adj_max;
1907 			pins[i].prop.phase_range.max =
1908 				-pf->dplls.output_phase_adj_max;
1909 			ret = ice_cgu_get_output_pin_state_caps(hw, i, &caps);
1910 			if (ret)
1911 				return ret;
1912 		}
1913 		pins[i].prop.capabilities = caps;
1914 		ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
1915 		if (ret)
1916 			return ret;
1917 		pins[i].prop.freq_supported =
1918 			ice_cgu_get_pin_freq_supp(hw, i, input, &freq_supp_num);
1919 		pins[i].prop.freq_supported_num = freq_supp_num;
1920 		pins[i].pf = pf;
1921 	}
1922 
1923 	return ret;
1924 }
1925 
1926 /**
1927  * ice_dpll_init_info_rclk_pin - initializes rclk pin information
1928  * @pf: board private structure
1929  *
1930  * Init information for rclk pin, cache them in pf->dplls.rclk.
1931  *
1932  * Return:
1933  * * 0 - success
1934  * * negative - init failure reason
1935  */
ice_dpll_init_info_rclk_pin(struct ice_pf * pf)1936 static int ice_dpll_init_info_rclk_pin(struct ice_pf *pf)
1937 {
1938 	struct ice_dpll_pin *pin = &pf->dplls.rclk;
1939 
1940 	pin->prop.type = DPLL_PIN_TYPE_SYNCE_ETH_PORT;
1941 	pin->prop.capabilities |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
1942 	pin->pf = pf;
1943 
1944 	return ice_dpll_pin_state_update(pf, pin,
1945 					 ICE_DPLL_PIN_TYPE_RCLK_INPUT, NULL);
1946 }
1947 
1948 /**
1949  * ice_dpll_init_pins_info - init pins info wrapper
1950  * @pf: board private structure
1951  * @pin_type: type of pins being initialized
1952  *
1953  * Wraps functions for pin initialization.
1954  *
1955  * Return:
1956  * * 0 - success
1957  * * negative - init failure reason
1958  */
1959 static int
ice_dpll_init_pins_info(struct ice_pf * pf,enum ice_dpll_pin_type pin_type)1960 ice_dpll_init_pins_info(struct ice_pf *pf, enum ice_dpll_pin_type pin_type)
1961 {
1962 	switch (pin_type) {
1963 	case ICE_DPLL_PIN_TYPE_INPUT:
1964 	case ICE_DPLL_PIN_TYPE_OUTPUT:
1965 		return ice_dpll_init_info_direct_pins(pf, pin_type);
1966 	case ICE_DPLL_PIN_TYPE_RCLK_INPUT:
1967 		return ice_dpll_init_info_rclk_pin(pf);
1968 	default:
1969 		return -EINVAL;
1970 	}
1971 }
1972 
1973 /**
1974  * ice_dpll_deinit_info - release memory allocated for pins info
1975  * @pf: board private structure
1976  *
1977  * Release memory allocated for pins by ice_dpll_init_info function.
1978  */
ice_dpll_deinit_info(struct ice_pf * pf)1979 static void ice_dpll_deinit_info(struct ice_pf *pf)
1980 {
1981 	kfree(pf->dplls.inputs);
1982 	kfree(pf->dplls.outputs);
1983 	kfree(pf->dplls.eec.input_prio);
1984 	kfree(pf->dplls.pps.input_prio);
1985 }
1986 
1987 /**
1988  * ice_dpll_init_info - prepare pf's dpll information structure
1989  * @pf: board private structure
1990  * @cgu: if cgu is present and controlled by this NIC
1991  *
1992  * Acquire (from HW) and set basic dpll information (on pf->dplls struct).
1993  *
1994  * Return:
1995  * * 0 - success
1996  * * negative - init failure reason
1997  */
ice_dpll_init_info(struct ice_pf * pf,bool cgu)1998 static int ice_dpll_init_info(struct ice_pf *pf, bool cgu)
1999 {
2000 	struct ice_aqc_get_cgu_abilities abilities;
2001 	struct ice_dpll *de = &pf->dplls.eec;
2002 	struct ice_dpll *dp = &pf->dplls.pps;
2003 	struct ice_dplls *d = &pf->dplls;
2004 	struct ice_hw *hw = &pf->hw;
2005 	int ret, alloc_size, i;
2006 
2007 	d->clock_id = ice_generate_clock_id(pf);
2008 	ret = ice_aq_get_cgu_abilities(hw, &abilities);
2009 	if (ret) {
2010 		dev_err(ice_pf_to_dev(pf),
2011 			"err:%d %s failed to read cgu abilities\n",
2012 			ret, ice_aq_str(hw->adminq.sq_last_status));
2013 		return ret;
2014 	}
2015 
2016 	de->dpll_idx = abilities.eec_dpll_idx;
2017 	dp->dpll_idx = abilities.pps_dpll_idx;
2018 	d->num_inputs = abilities.num_inputs;
2019 	d->num_outputs = abilities.num_outputs;
2020 	d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj);
2021 	d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj);
2022 
2023 	alloc_size = sizeof(*d->inputs) * d->num_inputs;
2024 	d->inputs = kzalloc(alloc_size, GFP_KERNEL);
2025 	if (!d->inputs)
2026 		return -ENOMEM;
2027 
2028 	alloc_size = sizeof(*de->input_prio) * d->num_inputs;
2029 	de->input_prio = kzalloc(alloc_size, GFP_KERNEL);
2030 	if (!de->input_prio)
2031 		return -ENOMEM;
2032 
2033 	dp->input_prio = kzalloc(alloc_size, GFP_KERNEL);
2034 	if (!dp->input_prio)
2035 		return -ENOMEM;
2036 
2037 	ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_INPUT);
2038 	if (ret)
2039 		goto deinit_info;
2040 
2041 	if (cgu) {
2042 		alloc_size = sizeof(*d->outputs) * d->num_outputs;
2043 		d->outputs = kzalloc(alloc_size, GFP_KERNEL);
2044 		if (!d->outputs) {
2045 			ret = -ENOMEM;
2046 			goto deinit_info;
2047 		}
2048 
2049 		ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_OUTPUT);
2050 		if (ret)
2051 			goto deinit_info;
2052 	}
2053 
2054 	ret = ice_get_cgu_rclk_pin_info(&pf->hw, &d->base_rclk_idx,
2055 					&pf->dplls.rclk.num_parents);
2056 	if (ret)
2057 		return ret;
2058 	for (i = 0; i < pf->dplls.rclk.num_parents; i++)
2059 		pf->dplls.rclk.parent_idx[i] = d->base_rclk_idx + i;
2060 	ret = ice_dpll_init_pins_info(pf, ICE_DPLL_PIN_TYPE_RCLK_INPUT);
2061 	if (ret)
2062 		return ret;
2063 	de->mode = DPLL_MODE_AUTOMATIC;
2064 	dp->mode = DPLL_MODE_AUTOMATIC;
2065 
2066 	dev_dbg(ice_pf_to_dev(pf),
2067 		"%s - success, inputs:%u, outputs:%u rclk-parents:%u\n",
2068 		__func__, d->num_inputs, d->num_outputs, d->rclk.num_parents);
2069 
2070 	return 0;
2071 
2072 deinit_info:
2073 	dev_err(ice_pf_to_dev(pf),
2074 		"%s - fail: d->inputs:%p, de->input_prio:%p, dp->input_prio:%p, d->outputs:%p\n",
2075 		__func__, d->inputs, de->input_prio,
2076 		dp->input_prio, d->outputs);
2077 	ice_dpll_deinit_info(pf);
2078 	return ret;
2079 }
2080 
2081 /**
2082  * ice_dpll_deinit - Disable the driver/HW support for dpll subsystem
2083  * the dpll device.
2084  * @pf: board private structure
2085  *
2086  * Handles the cleanup work required after dpll initialization, freeing
2087  * resources and unregistering the dpll, pin and all resources used for
2088  * handling them.
2089  *
2090  * Context: Destroys pf->dplls.lock mutex. Call only if ICE_FLAG_DPLL was set.
2091  */
ice_dpll_deinit(struct ice_pf * pf)2092 void ice_dpll_deinit(struct ice_pf *pf)
2093 {
2094 	bool cgu = ice_is_feature_supported(pf, ICE_F_CGU);
2095 
2096 	clear_bit(ICE_FLAG_DPLL, pf->flags);
2097 	if (cgu)
2098 		ice_dpll_deinit_worker(pf);
2099 
2100 	ice_dpll_deinit_pins(pf, cgu);
2101 	ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu);
2102 	ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu);
2103 	ice_dpll_deinit_info(pf);
2104 	mutex_destroy(&pf->dplls.lock);
2105 }
2106 
2107 /**
2108  * ice_dpll_init - initialize support for dpll subsystem
2109  * @pf: board private structure
2110  *
2111  * Set up the device dplls, register them and pins connected within Linux dpll
2112  * subsystem. Allow userspace to obtain state of DPLL and handling of DPLL
2113  * configuration requests.
2114  *
2115  * Context: Initializes pf->dplls.lock mutex.
2116  */
ice_dpll_init(struct ice_pf * pf)2117 void ice_dpll_init(struct ice_pf *pf)
2118 {
2119 	bool cgu = ice_is_feature_supported(pf, ICE_F_CGU);
2120 	struct ice_dplls *d = &pf->dplls;
2121 	int err = 0;
2122 
2123 	mutex_init(&d->lock);
2124 	err = ice_dpll_init_info(pf, cgu);
2125 	if (err)
2126 		goto err_exit;
2127 	err = ice_dpll_init_dpll(pf, &pf->dplls.eec, cgu, DPLL_TYPE_EEC);
2128 	if (err)
2129 		goto deinit_info;
2130 	err = ice_dpll_init_dpll(pf, &pf->dplls.pps, cgu, DPLL_TYPE_PPS);
2131 	if (err)
2132 		goto deinit_eec;
2133 	err = ice_dpll_init_pins(pf, cgu);
2134 	if (err)
2135 		goto deinit_pps;
2136 	if (cgu) {
2137 		err = ice_dpll_init_worker(pf);
2138 		if (err)
2139 			goto deinit_pins;
2140 	}
2141 	set_bit(ICE_FLAG_DPLL, pf->flags);
2142 
2143 	return;
2144 
2145 deinit_pins:
2146 	ice_dpll_deinit_pins(pf, cgu);
2147 deinit_pps:
2148 	ice_dpll_deinit_dpll(pf, &pf->dplls.pps, cgu);
2149 deinit_eec:
2150 	ice_dpll_deinit_dpll(pf, &pf->dplls.eec, cgu);
2151 deinit_info:
2152 	ice_dpll_deinit_info(pf);
2153 err_exit:
2154 	mutex_destroy(&d->lock);
2155 	dev_warn(ice_pf_to_dev(pf), "DPLLs init failure err:%d\n", err);
2156 }
2157