1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
4 *
5 * Copyright (C) 2018 Synaptics Incorporated
6 *
7 * Author: Jisheng Zhang <jszhang@kernel.org>
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21 #include <linux/sizes.h>
22
23 #include "sdhci-pltfm.h"
24
25 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
26
27 /* DWCMSHC specific Mode Select value */
28 #define DWCMSHC_CTRL_HS400 0x7
29
30 /* DWC IP vendor area 1 pointer */
31 #define DWCMSHC_P_VENDOR_AREA1 0xe8
32 #define DWCMSHC_AREA1_MASK GENMASK(11, 0)
33 /* Offset inside the vendor area 1 */
34 #define DWCMSHC_HOST_CTRL3 0x8
35 #define DWCMSHC_EMMC_CONTROL 0x2c
36 #define DWCMSHC_CARD_IS_EMMC BIT(0)
37 #define DWCMSHC_ENHANCED_STROBE BIT(8)
38 #define DWCMSHC_EMMC_ATCTRL 0x40
39 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
40 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */
41 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */
42 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */
43 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */
44 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */
45 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */
46 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */
47 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */
48 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */
49 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
50 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */
51 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
52 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */
53 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */
54
55 /* Rockchip specific Registers */
56 #define DWCMSHC_EMMC_DLL_CTRL 0x800
57 #define DWCMSHC_EMMC_DLL_RXCLK 0x804
58 #define DWCMSHC_EMMC_DLL_TXCLK 0x808
59 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
60 #define DECMSHC_EMMC_DLL_CMDOUT 0x810
61 #define DWCMSHC_EMMC_DLL_STATUS0 0x840
62 #define DWCMSHC_EMMC_DLL_START BIT(0)
63 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
64 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
65 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
66 #define DWCMSHC_EMMC_DLL_START_POINT 16
67 #define DWCMSHC_EMMC_DLL_INC 8
68 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
69 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
70 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
71 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
72 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
73 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8
74 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
75 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
76 #define DLL_STRBIN_DELAY_NUM_OFFSET 16
77 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16
78 #define DLL_RXCLK_NO_INVERTER 1
79 #define DLL_RXCLK_INVERTER 0
80 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
81 #define DLL_RXCLK_ORI_GATE BIT(31)
82 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
83 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
84 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
85
86 #define DLL_LOCK_WO_TMOUT(x) \
87 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
88 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
89 #define RK35xx_MAX_CLKS 3
90
91 /* PHY register area pointer */
92 #define DWC_MSHC_PTR_PHY_R 0x300
93
94 /* PHY general configuration */
95 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00)
96 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
97 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */
98 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */
99 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */
100 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */
101
102 /* PHY command/response pad settings */
103 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04)
104
105 /* PHY data pad settings */
106 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06)
107
108 /* PHY clock pad settings */
109 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08)
110
111 /* PHY strobe pad settings */
112 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a)
113
114 /* PHY reset pad settings */
115 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c)
116
117 /* Bitfields are common for all pad settings */
118 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */
119 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */
120
121 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */
122 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */
123 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */
124
125 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */
126 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
127 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */
128 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
129
130 /* PHY CLK delay line settings */
131 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d)
132 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */
133
134 /* PHY CLK delay line delay code */
135 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e)
136 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */
137 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */
138 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */
139
140 /* PHY drift_cclk_rx delay line configuration setting */
141 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21)
142 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */
143 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */
144
145 /* PHY DLL control settings */
146 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24)
147 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */
148 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */
149
150 /* PHY DLL configuration register 1 */
151 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25)
152 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */
153 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */
154 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */
155
156 /* PHY DLL configuration register 2 */
157 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26)
158 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */
159
160 /* PHY DLL master and slave delay line configuration settings */
161 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28)
162 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */
163 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */
164
165 #define FLAG_IO_FIXED_1V8 BIT(0)
166
167 #define BOUNDARY_OK(addr, len) \
168 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
169
170 enum dwcmshc_rk_type {
171 DWCMSHC_RK3568,
172 DWCMSHC_RK3588,
173 };
174
175 struct rk35xx_priv {
176 /* Rockchip specified optional clocks */
177 struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
178 struct reset_control *reset;
179 enum dwcmshc_rk_type devtype;
180 u8 txclk_tapnum;
181 };
182
183 struct dwcmshc_priv {
184 struct clk *bus_clk;
185 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
186 void *priv; /* pointer to SoC private stuff */
187 u16 delay_line;
188 u16 flags;
189 };
190
191 /*
192 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
193 * so that each DMA transfer doesn't exceed the boundary.
194 */
dwcmshc_adma_write_desc(struct sdhci_host * host,void ** desc,dma_addr_t addr,int len,unsigned int cmd)195 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
196 dma_addr_t addr, int len, unsigned int cmd)
197 {
198 int tmplen, offset;
199
200 if (likely(!len || BOUNDARY_OK(addr, len))) {
201 sdhci_adma_write_desc(host, desc, addr, len, cmd);
202 return;
203 }
204
205 offset = addr & (SZ_128M - 1);
206 tmplen = SZ_128M - offset;
207 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
208
209 addr += tmplen;
210 len -= tmplen;
211 sdhci_adma_write_desc(host, desc, addr, len, cmd);
212 }
213
dwcmshc_get_max_clock(struct sdhci_host * host)214 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
215 {
216 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
217
218 if (pltfm_host->clk)
219 return sdhci_pltfm_clk_get_max_clock(host);
220 else
221 return pltfm_host->clock;
222 }
223
rk35xx_get_max_clock(struct sdhci_host * host)224 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
225 {
226 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
227
228 return clk_round_rate(pltfm_host->clk, ULONG_MAX);
229 }
230
dwcmshc_check_auto_cmd23(struct mmc_host * mmc,struct mmc_request * mrq)231 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
232 struct mmc_request *mrq)
233 {
234 struct sdhci_host *host = mmc_priv(mmc);
235
236 /*
237 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
238 * block count register which doesn't support stuff bits of
239 * CMD23 argument on dwcmsch host controller.
240 */
241 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
242 host->flags &= ~SDHCI_AUTO_CMD23;
243 else
244 host->flags |= SDHCI_AUTO_CMD23;
245 }
246
dwcmshc_request(struct mmc_host * mmc,struct mmc_request * mrq)247 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
248 {
249 dwcmshc_check_auto_cmd23(mmc, mrq);
250
251 sdhci_request(mmc, mrq);
252 }
253
dwcmshc_phy_1_8v_init(struct sdhci_host * host)254 static void dwcmshc_phy_1_8v_init(struct sdhci_host *host)
255 {
256 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
257 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
258 u32 val;
259
260 /* deassert phy reset & set tx drive strength */
261 val = PHY_CNFG_RSTN_DEASSERT;
262 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
263 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
264 sdhci_writel(host, val, PHY_CNFG_R);
265
266 /* disable delay line */
267 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
268
269 /* set delay line */
270 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
271 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
272
273 /* enable delay lane */
274 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
275 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
276 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
277
278 /* configure phy pads */
279 val = PHY_PAD_RXSEL_1V8;
280 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
281 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
282 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
283 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
284 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
285 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
286
287 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
288 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
289 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
290
291 val = PHY_PAD_RXSEL_1V8;
292 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
293 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
294 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
295 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
296
297 /* enable data strobe mode */
298 sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL),
299 PHY_DLLDL_CNFG_R);
300
301 /* enable phy dll */
302 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
303 }
304
dwcmshc_phy_3_3v_init(struct sdhci_host * host)305 static void dwcmshc_phy_3_3v_init(struct sdhci_host *host)
306 {
307 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
308 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
309 u32 val;
310
311 /* deassert phy reset & set tx drive strength */
312 val = PHY_CNFG_RSTN_DEASSERT;
313 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);
314 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);
315 sdhci_writel(host, val, PHY_CNFG_R);
316
317 /* disable delay line */
318 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);
319
320 /* set delay line */
321 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);
322 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);
323
324 /* enable delay lane */
325 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);
326 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);
327 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);
328
329 /* configure phy pads */
330 val = PHY_PAD_RXSEL_3V3;
331 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
332 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
333 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
334 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
335 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
336 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
337
338 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
339 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
340 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
341
342 val = PHY_PAD_RXSEL_3V3;
343 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
344 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);
345 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);
346 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
347
348 /* enable phy dll */
349 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
350 }
351
th1520_sdhci_set_phy(struct sdhci_host * host)352 static void th1520_sdhci_set_phy(struct sdhci_host *host)
353 {
354 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
355 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
356 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
357 u16 emmc_ctrl;
358
359 /* Before power on, set PHY configs */
360 if (priv->flags & FLAG_IO_FIXED_1V8)
361 dwcmshc_phy_1_8v_init(host);
362 else
363 dwcmshc_phy_3_3v_init(host);
364
365 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
366 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
367 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC;
368 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
369 }
370
371 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) |
372 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R);
373 }
374
dwcmshc_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)375 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
376 unsigned int timing)
377 {
378 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
379 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
380 u16 ctrl, ctrl_2;
381
382 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
383 /* Select Bus Speed Mode for host */
384 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
385 if ((timing == MMC_TIMING_MMC_HS200) ||
386 (timing == MMC_TIMING_UHS_SDR104))
387 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
388 else if (timing == MMC_TIMING_UHS_SDR12)
389 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
390 else if ((timing == MMC_TIMING_UHS_SDR25) ||
391 (timing == MMC_TIMING_MMC_HS))
392 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
393 else if (timing == MMC_TIMING_UHS_SDR50)
394 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
395 else if ((timing == MMC_TIMING_UHS_DDR50) ||
396 (timing == MMC_TIMING_MMC_DDR52))
397 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
398 else if (timing == MMC_TIMING_MMC_HS400) {
399 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
400 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
401 ctrl |= DWCMSHC_CARD_IS_EMMC;
402 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
403
404 ctrl_2 |= DWCMSHC_CTRL_HS400;
405 }
406
407 if (priv->flags & FLAG_IO_FIXED_1V8)
408 ctrl_2 |= SDHCI_CTRL_VDD_180;
409 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
410 }
411
th1520_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)412 static void th1520_set_uhs_signaling(struct sdhci_host *host,
413 unsigned int timing)
414 {
415 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
416 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
417
418 dwcmshc_set_uhs_signaling(host, timing);
419 if (timing == MMC_TIMING_MMC_HS400)
420 priv->delay_line = PHY_SDCLKDL_DC_HS400;
421 else
422 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);
423 th1520_sdhci_set_phy(host);
424 }
425
dwcmshc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)426 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
427 struct mmc_ios *ios)
428 {
429 u32 vendor;
430 struct sdhci_host *host = mmc_priv(mmc);
431 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
432 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
433 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
434
435 vendor = sdhci_readl(host, reg);
436 if (ios->enhanced_strobe)
437 vendor |= DWCMSHC_ENHANCED_STROBE;
438 else
439 vendor &= ~DWCMSHC_ENHANCED_STROBE;
440
441 sdhci_writel(host, vendor, reg);
442 }
443
dwcmshc_rk3568_set_clock(struct sdhci_host * host,unsigned int clock)444 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
445 {
446 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
447 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
448 struct rk35xx_priv *priv = dwc_priv->priv;
449 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
450 u32 extra, reg;
451 int err;
452
453 host->mmc->actual_clock = 0;
454
455 if (clock == 0) {
456 /* Disable interface clock at initial state. */
457 sdhci_set_clock(host, clock);
458 return;
459 }
460
461 /* Rockchip platform only support 375KHz for identify mode */
462 if (clock <= 400000)
463 clock = 375000;
464
465 err = clk_set_rate(pltfm_host->clk, clock);
466 if (err)
467 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
468
469 sdhci_set_clock(host, clock);
470
471 /* Disable cmd conflict check */
472 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
473 extra = sdhci_readl(host, reg);
474 extra &= ~BIT(0);
475 sdhci_writel(host, extra, reg);
476
477 if (clock <= 52000000) {
478 /*
479 * Disable DLL and reset both of sample and drive clock.
480 * The bypass bit and start bit need to be set if DLL is not locked.
481 */
482 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
483 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
484 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
485 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
486 /*
487 * Before switching to hs400es mode, the driver will enable
488 * enhanced strobe first. PHY needs to configure the parameters
489 * of enhanced strobe first.
490 */
491 extra = DWCMSHC_EMMC_DLL_DLYENA |
492 DLL_STRBIN_DELAY_NUM_SEL |
493 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
494 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
495 return;
496 }
497
498 /* Reset DLL */
499 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
500 udelay(1);
501 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
502
503 /*
504 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but
505 * we must set it in higher speed mode.
506 */
507 extra = DWCMSHC_EMMC_DLL_DLYENA;
508 if (priv->devtype == DWCMSHC_RK3568)
509 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
510 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
511
512 /* Init DLL settings */
513 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
514 0x2 << DWCMSHC_EMMC_DLL_INC |
515 DWCMSHC_EMMC_DLL_START;
516 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
517 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
518 extra, DLL_LOCK_WO_TMOUT(extra), 1,
519 500 * USEC_PER_MSEC);
520 if (err) {
521 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
522 return;
523 }
524
525 extra = 0x1 << 16 | /* tune clock stop en */
526 0x3 << 17 | /* pre-change delay */
527 0x3 << 19; /* post-change delay */
528 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
529
530 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
531 host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
532 txclk_tapnum = priv->txclk_tapnum;
533
534 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
535 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;
536
537 extra = DLL_CMDOUT_SRC_CLK_NEG |
538 DLL_CMDOUT_EN_SRC_CLK_NEG |
539 DWCMSHC_EMMC_DLL_DLYENA |
540 DLL_CMDOUT_TAPNUM_90_DEGREES |
541 DLL_CMDOUT_TAPNUM_FROM_SW;
542 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
543 }
544
545 extra = DWCMSHC_EMMC_DLL_DLYENA |
546 DLL_TXCLK_TAPNUM_FROM_SW |
547 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
548 txclk_tapnum;
549 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
550
551 extra = DWCMSHC_EMMC_DLL_DLYENA |
552 DLL_STRBIN_TAPNUM_DEFAULT |
553 DLL_STRBIN_TAPNUM_FROM_SW;
554 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
555 }
556
rk35xx_sdhci_reset(struct sdhci_host * host,u8 mask)557 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
558 {
559 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
560 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
561 struct rk35xx_priv *priv = dwc_priv->priv;
562
563 if (mask & SDHCI_RESET_ALL && priv->reset) {
564 reset_control_assert(priv->reset);
565 udelay(1);
566 reset_control_deassert(priv->reset);
567 }
568
569 sdhci_reset(host, mask);
570 }
571
th1520_execute_tuning(struct sdhci_host * host,u32 opcode)572 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)
573 {
574 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
575 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
576 u32 val = 0;
577
578 if (host->flags & SDHCI_HS400_TUNING)
579 return 0;
580
581 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL),
582 PHY_ATDL_CNFG_R);
583 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
584
585 /*
586 * configure tuning settings:
587 * - center phase select code driven in block gap interval
588 * - disable reporting of framing errors
589 * - disable software managed tuning
590 * - disable user selection of sampling window edges,
591 * instead tuning calculated edges are used
592 */
593 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN |
594 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL));
595
596 /*
597 * configure tuning settings:
598 * - enable auto-tuning
599 * - enable sampling window threshold
600 * - stop clocks during phase code change
601 * - set max latency in cycles between tx and rx clocks
602 * - set max latency in cycles to switch output phase
603 * - set max sampling window threshold value
604 */
605 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN;
606 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);
607 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);
608 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);
609
610 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
611 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
612
613 /* perform tuning */
614 sdhci_start_tuning(host);
615 host->tuning_err = __sdhci_execute_tuning(host, opcode);
616 if (host->tuning_err) {
617 /* disable auto-tuning upon tuning error */
618 val &= ~AT_CTRL_AT_EN;
619 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
620 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err);
621 return -EIO;
622 }
623 sdhci_end_tuning(host);
624
625 return 0;
626 }
627
th1520_sdhci_reset(struct sdhci_host * host,u8 mask)628 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
629 {
630 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
631 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
632 u16 ctrl_2;
633
634 sdhci_reset(host, mask);
635
636 if (priv->flags & FLAG_IO_FIXED_1V8) {
637 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
638 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) {
639 ctrl_2 |= SDHCI_CTRL_VDD_180;
640 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
641 }
642 }
643 }
644
645 static const struct sdhci_ops sdhci_dwcmshc_ops = {
646 .set_clock = sdhci_set_clock,
647 .set_bus_width = sdhci_set_bus_width,
648 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
649 .get_max_clock = dwcmshc_get_max_clock,
650 .reset = sdhci_reset,
651 .adma_write_desc = dwcmshc_adma_write_desc,
652 };
653
654 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
655 .set_clock = dwcmshc_rk3568_set_clock,
656 .set_bus_width = sdhci_set_bus_width,
657 .set_uhs_signaling = dwcmshc_set_uhs_signaling,
658 .get_max_clock = rk35xx_get_max_clock,
659 .reset = rk35xx_sdhci_reset,
660 .adma_write_desc = dwcmshc_adma_write_desc,
661 };
662
663 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
664 .set_clock = sdhci_set_clock,
665 .set_bus_width = sdhci_set_bus_width,
666 .set_uhs_signaling = th1520_set_uhs_signaling,
667 .get_max_clock = dwcmshc_get_max_clock,
668 .reset = th1520_sdhci_reset,
669 .adma_write_desc = dwcmshc_adma_write_desc,
670 .voltage_switch = dwcmshc_phy_1_8v_init,
671 .platform_execute_tuning = &th1520_execute_tuning,
672 };
673
674 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
675 .ops = &sdhci_dwcmshc_ops,
676 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
677 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
678 };
679
680 #ifdef CONFIG_ACPI
681 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
682 .ops = &sdhci_dwcmshc_ops,
683 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
684 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
685 SDHCI_QUIRK2_ACMD23_BROKEN,
686 };
687 #endif
688
689 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
690 .ops = &sdhci_dwcmshc_rk35xx_ops,
691 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
692 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
693 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
694 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
695 };
696
697 static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {
698 .ops = &sdhci_dwcmshc_th1520_ops,
699 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
700 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
701 };
702
dwcmshc_rk35xx_init(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)703 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
704 {
705 int err;
706 struct rk35xx_priv *priv = dwc_priv->priv;
707
708 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
709 if (IS_ERR(priv->reset)) {
710 err = PTR_ERR(priv->reset);
711 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
712 return err;
713 }
714
715 priv->rockchip_clks[0].id = "axi";
716 priv->rockchip_clks[1].id = "block";
717 priv->rockchip_clks[2].id = "timer";
718 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
719 priv->rockchip_clks);
720 if (err) {
721 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
722 return err;
723 }
724
725 err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
726 if (err) {
727 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
728 return err;
729 }
730
731 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
732 &priv->txclk_tapnum))
733 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
734
735 /* Disable cmd conflict check */
736 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
737 /* Reset previous settings */
738 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
739 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
740
741 return 0;
742 }
743
dwcmshc_rk35xx_postinit(struct sdhci_host * host,struct dwcmshc_priv * dwc_priv)744 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
745 {
746 /*
747 * Don't support highspeed bus mode with low clk speed as we
748 * cannot use DLL for this condition.
749 */
750 if (host->mmc->f_max <= 52000000) {
751 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
752 host->mmc->f_max);
753 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
754 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
755 }
756 }
757
758 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
759 {
760 .compatible = "rockchip,rk3588-dwcmshc",
761 .data = &sdhci_dwcmshc_rk35xx_pdata,
762 },
763 {
764 .compatible = "rockchip,rk3568-dwcmshc",
765 .data = &sdhci_dwcmshc_rk35xx_pdata,
766 },
767 {
768 .compatible = "snps,dwcmshc-sdhci",
769 .data = &sdhci_dwcmshc_pdata,
770 },
771 {
772 .compatible = "thead,th1520-dwcmshc",
773 .data = &sdhci_dwcmshc_th1520_pdata,
774 },
775 {},
776 };
777 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
778
779 #ifdef CONFIG_ACPI
780 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
781 {
782 .id = "MLNXBF30",
783 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
784 },
785 {}
786 };
787 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);
788 #endif
789
dwcmshc_probe(struct platform_device * pdev)790 static int dwcmshc_probe(struct platform_device *pdev)
791 {
792 struct device *dev = &pdev->dev;
793 struct sdhci_pltfm_host *pltfm_host;
794 struct sdhci_host *host;
795 struct dwcmshc_priv *priv;
796 struct rk35xx_priv *rk_priv = NULL;
797 const struct sdhci_pltfm_data *pltfm_data;
798 int err;
799 u32 extra;
800
801 pltfm_data = device_get_match_data(&pdev->dev);
802 if (!pltfm_data) {
803 dev_err(&pdev->dev, "Error: No device match data found\n");
804 return -ENODEV;
805 }
806
807 host = sdhci_pltfm_init(pdev, pltfm_data,
808 sizeof(struct dwcmshc_priv));
809 if (IS_ERR(host))
810 return PTR_ERR(host);
811
812 /*
813 * extra adma table cnt for cross 128M boundary handling.
814 */
815 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
816 if (extra > SDHCI_MAX_SEGS)
817 extra = SDHCI_MAX_SEGS;
818 host->adma_table_cnt += extra;
819
820 pltfm_host = sdhci_priv(host);
821 priv = sdhci_pltfm_priv(pltfm_host);
822
823 if (dev->of_node) {
824 pltfm_host->clk = devm_clk_get(dev, "core");
825 if (IS_ERR(pltfm_host->clk)) {
826 err = PTR_ERR(pltfm_host->clk);
827 dev_err(dev, "failed to get core clk: %d\n", err);
828 goto free_pltfm;
829 }
830 err = clk_prepare_enable(pltfm_host->clk);
831 if (err)
832 goto free_pltfm;
833
834 priv->bus_clk = devm_clk_get(dev, "bus");
835 if (!IS_ERR(priv->bus_clk))
836 clk_prepare_enable(priv->bus_clk);
837 }
838
839 err = mmc_of_parse(host->mmc);
840 if (err)
841 goto err_clk;
842
843 sdhci_get_of_property(pdev);
844
845 priv->vendor_specific_area1 =
846 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
847
848 host->mmc_host_ops.request = dwcmshc_request;
849 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
850
851 if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) {
852 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
853 if (!rk_priv) {
854 err = -ENOMEM;
855 goto err_clk;
856 }
857
858 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
859 rk_priv->devtype = DWCMSHC_RK3588;
860 else
861 rk_priv->devtype = DWCMSHC_RK3568;
862
863 priv->priv = rk_priv;
864
865 err = dwcmshc_rk35xx_init(host, priv);
866 if (err)
867 goto err_clk;
868 }
869
870 if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) {
871 priv->delay_line = PHY_SDCLKDL_DC_DEFAULT;
872
873 if (device_property_read_bool(dev, "mmc-ddr-1_8v") ||
874 device_property_read_bool(dev, "mmc-hs200-1_8v") ||
875 device_property_read_bool(dev, "mmc-hs400-1_8v"))
876 priv->flags |= FLAG_IO_FIXED_1V8;
877 else
878 priv->flags &= ~FLAG_IO_FIXED_1V8;
879
880 /*
881 * start_signal_voltage_switch() will try 3.3V first
882 * then 1.8V. Use SDHCI_SIGNALING_180 rather than
883 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V
884 * in sdhci_start_signal_voltage_switch().
885 */
886 if (priv->flags & FLAG_IO_FIXED_1V8) {
887 host->flags &= ~SDHCI_SIGNALING_330;
888 host->flags |= SDHCI_SIGNALING_180;
889 }
890
891 sdhci_enable_v4_mode(host);
892 }
893
894 #ifdef CONFIG_ACPI
895 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)
896 sdhci_enable_v4_mode(host);
897 #endif
898
899 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
900
901 pm_runtime_get_noresume(dev);
902 pm_runtime_set_active(dev);
903 pm_runtime_enable(dev);
904
905 err = sdhci_setup_host(host);
906 if (err)
907 goto err_rpm;
908
909 if (rk_priv)
910 dwcmshc_rk35xx_postinit(host, priv);
911
912 err = __sdhci_add_host(host);
913 if (err)
914 goto err_setup_host;
915
916 pm_runtime_put(dev);
917
918 return 0;
919
920 err_setup_host:
921 sdhci_cleanup_host(host);
922 err_rpm:
923 pm_runtime_disable(dev);
924 pm_runtime_put_noidle(dev);
925 err_clk:
926 clk_disable_unprepare(pltfm_host->clk);
927 clk_disable_unprepare(priv->bus_clk);
928 if (rk_priv)
929 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
930 rk_priv->rockchip_clks);
931 free_pltfm:
932 sdhci_pltfm_free(pdev);
933 return err;
934 }
935
dwcmshc_remove(struct platform_device * pdev)936 static void dwcmshc_remove(struct platform_device *pdev)
937 {
938 struct sdhci_host *host = platform_get_drvdata(pdev);
939 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
940 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
941 struct rk35xx_priv *rk_priv = priv->priv;
942
943 sdhci_remove_host(host, 0);
944
945 clk_disable_unprepare(pltfm_host->clk);
946 clk_disable_unprepare(priv->bus_clk);
947 if (rk_priv)
948 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
949 rk_priv->rockchip_clks);
950 sdhci_pltfm_free(pdev);
951 }
952
953 #ifdef CONFIG_PM_SLEEP
dwcmshc_suspend(struct device * dev)954 static int dwcmshc_suspend(struct device *dev)
955 {
956 struct sdhci_host *host = dev_get_drvdata(dev);
957 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
958 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
959 struct rk35xx_priv *rk_priv = priv->priv;
960 int ret;
961
962 pm_runtime_resume(dev);
963
964 ret = sdhci_suspend_host(host);
965 if (ret)
966 return ret;
967
968 clk_disable_unprepare(pltfm_host->clk);
969 if (!IS_ERR(priv->bus_clk))
970 clk_disable_unprepare(priv->bus_clk);
971
972 if (rk_priv)
973 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
974 rk_priv->rockchip_clks);
975
976 return ret;
977 }
978
dwcmshc_resume(struct device * dev)979 static int dwcmshc_resume(struct device *dev)
980 {
981 struct sdhci_host *host = dev_get_drvdata(dev);
982 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
983 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
984 struct rk35xx_priv *rk_priv = priv->priv;
985 int ret;
986
987 ret = clk_prepare_enable(pltfm_host->clk);
988 if (ret)
989 return ret;
990
991 if (!IS_ERR(priv->bus_clk)) {
992 ret = clk_prepare_enable(priv->bus_clk);
993 if (ret)
994 goto disable_clk;
995 }
996
997 if (rk_priv) {
998 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
999 rk_priv->rockchip_clks);
1000 if (ret)
1001 goto disable_bus_clk;
1002 }
1003
1004 ret = sdhci_resume_host(host);
1005 if (ret)
1006 goto disable_rockchip_clks;
1007
1008 return 0;
1009
1010 disable_rockchip_clks:
1011 if (rk_priv)
1012 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
1013 rk_priv->rockchip_clks);
1014 disable_bus_clk:
1015 if (!IS_ERR(priv->bus_clk))
1016 clk_disable_unprepare(priv->bus_clk);
1017 disable_clk:
1018 clk_disable_unprepare(pltfm_host->clk);
1019 return ret;
1020 }
1021 #endif
1022
1023 #ifdef CONFIG_PM
1024
dwcmshc_enable_card_clk(struct sdhci_host * host)1025 static void dwcmshc_enable_card_clk(struct sdhci_host *host)
1026 {
1027 u16 ctrl;
1028
1029 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1030 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) {
1031 ctrl |= SDHCI_CLOCK_CARD_EN;
1032 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1033 }
1034 }
1035
dwcmshc_disable_card_clk(struct sdhci_host * host)1036 static void dwcmshc_disable_card_clk(struct sdhci_host *host)
1037 {
1038 u16 ctrl;
1039
1040 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1041 if (ctrl & SDHCI_CLOCK_CARD_EN) {
1042 ctrl &= ~SDHCI_CLOCK_CARD_EN;
1043 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
1044 }
1045 }
1046
dwcmshc_runtime_suspend(struct device * dev)1047 static int dwcmshc_runtime_suspend(struct device *dev)
1048 {
1049 struct sdhci_host *host = dev_get_drvdata(dev);
1050
1051 dwcmshc_disable_card_clk(host);
1052
1053 return 0;
1054 }
1055
dwcmshc_runtime_resume(struct device * dev)1056 static int dwcmshc_runtime_resume(struct device *dev)
1057 {
1058 struct sdhci_host *host = dev_get_drvdata(dev);
1059
1060 dwcmshc_enable_card_clk(host);
1061
1062 return 0;
1063 }
1064
1065 #endif
1066
1067 static const struct dev_pm_ops dwcmshc_pmops = {
1068 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)
1069 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend,
1070 dwcmshc_runtime_resume, NULL)
1071 };
1072
1073 static struct platform_driver sdhci_dwcmshc_driver = {
1074 .driver = {
1075 .name = "sdhci-dwcmshc",
1076 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1077 .of_match_table = sdhci_dwcmshc_dt_ids,
1078 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
1079 .pm = &dwcmshc_pmops,
1080 },
1081 .probe = dwcmshc_probe,
1082 .remove_new = dwcmshc_remove,
1083 };
1084 module_platform_driver(sdhci_dwcmshc_driver);
1085
1086 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
1087 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
1088 MODULE_LICENSE("GPL v2");
1089