1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
4  *
5  * Copyright (C) 2015 Broadcom Corporation
6  */
7 
8 #include <linux/io.h>
9 #include <linux/iopoll.h>
10 #include <linux/mmc/host.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 
16 #include "sdhci-cqhci.h"
17 #include "sdhci-pltfm.h"
18 #include "cqhci.h"
19 
20 #define SDHCI_VENDOR 0x78
21 #define  SDHCI_VENDOR_ENHANCED_STRB 0x1
22 #define  SDHCI_VENDOR_GATE_SDCLK_EN 0x2
23 
24 #define BRCMSTB_MATCH_FLAGS_NO_64BIT		BIT(0)
25 #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT	BIT(1)
26 #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE	BIT(2)
27 
28 #define BRCMSTB_PRIV_FLAGS_HAS_CQE		BIT(0)
29 #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK		BIT(1)
30 
31 #define SDHCI_ARASAN_CQE_BASE_ADDR		0x200
32 
33 struct sdhci_brcmstb_priv {
34 	void __iomem *cfg_regs;
35 	unsigned int flags;
36 	struct clk *base_clk;
37 	u32 base_freq_hz;
38 };
39 
40 struct brcmstb_match_priv {
41 	void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
42 	struct sdhci_ops *ops;
43 	const unsigned int flags;
44 };
45 
enable_clock_gating(struct sdhci_host * host)46 static inline void enable_clock_gating(struct sdhci_host *host)
47 {
48 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
49 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
50 	u32 reg;
51 
52 	if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK))
53 		return;
54 
55 	reg = sdhci_readl(host, SDHCI_VENDOR);
56 	reg |= SDHCI_VENDOR_GATE_SDCLK_EN;
57 	sdhci_writel(host, reg, SDHCI_VENDOR);
58 }
59 
brcmstb_reset(struct sdhci_host * host,u8 mask)60 static void brcmstb_reset(struct sdhci_host *host, u8 mask)
61 {
62 	sdhci_and_cqhci_reset(host, mask);
63 
64 	/* Reset will clear this, so re-enable it */
65 	enable_clock_gating(host);
66 }
67 
brcmstb_sdhci_reset_cmd_data(struct sdhci_host * host,u8 mask)68 static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask)
69 {
70 	u32 new_mask = (mask &  (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24;
71 	int ret;
72 	u32 reg;
73 
74 	/*
75 	 * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall
76 	 * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA
77 	 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register
78 	 */
79 	new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN;
80 	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
81 	sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL);
82 
83 	reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET);
84 
85 	ret = read_poll_timeout_atomic(sdhci_readb, reg, !(reg & mask),
86 				       10, 10000, false,
87 				       host, SDHCI_SOFTWARE_RESET);
88 
89 	if (ret) {
90 		pr_err("%s: Reset 0x%x never completed.\n",
91 		       mmc_hostname(host->mmc), (int)mask);
92 		sdhci_err_stats_inc(host, CTRL_TIMEOUT);
93 		sdhci_dumpregs(host);
94 	}
95 }
96 
brcmstb_reset_74165b0(struct sdhci_host * host,u8 mask)97 static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask)
98 {
99 	/* take care of RESET_ALL as usual */
100 	if (mask & SDHCI_RESET_ALL)
101 		sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL);
102 
103 	/* cmd and/or data treated differently on this core */
104 	if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA))
105 		brcmstb_sdhci_reset_cmd_data(host, mask);
106 
107 	/* Reset will clear this, so re-enable it */
108 	enable_clock_gating(host);
109 }
110 
sdhci_brcmstb_hs400es(struct mmc_host * mmc,struct mmc_ios * ios)111 static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)
112 {
113 	struct sdhci_host *host = mmc_priv(mmc);
114 
115 	u32 reg;
116 
117 	dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",
118 		__func__);
119 	reg = readl(host->ioaddr + SDHCI_VENDOR);
120 	if (ios->enhanced_strobe)
121 		reg |= SDHCI_VENDOR_ENHANCED_STRB;
122 	else
123 		reg &= ~SDHCI_VENDOR_ENHANCED_STRB;
124 	writel(reg, host->ioaddr + SDHCI_VENDOR);
125 }
126 
sdhci_brcmstb_set_clock(struct sdhci_host * host,unsigned int clock)127 static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
128 {
129 	u16 clk;
130 
131 	host->mmc->actual_clock = 0;
132 
133 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
134 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
135 
136 	if (clock == 0)
137 		return;
138 
139 	sdhci_enable_clk(host, clk);
140 }
141 
sdhci_brcmstb_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)142 static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
143 					    unsigned int timing)
144 {
145 	u16 ctrl_2;
146 
147 	dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
148 		__func__, timing);
149 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
150 	/* Select Bus Speed Mode for host */
151 	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
152 	if ((timing == MMC_TIMING_MMC_HS200) ||
153 	    (timing == MMC_TIMING_UHS_SDR104))
154 		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
155 	else if (timing == MMC_TIMING_UHS_SDR12)
156 		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
157 	else if (timing == MMC_TIMING_SD_HS ||
158 		 timing == MMC_TIMING_MMC_HS ||
159 		 timing == MMC_TIMING_UHS_SDR25)
160 		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
161 	else if (timing == MMC_TIMING_UHS_SDR50)
162 		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
163 	else if ((timing == MMC_TIMING_UHS_DDR50) ||
164 		 (timing == MMC_TIMING_MMC_DDR52))
165 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
166 	else if (timing == MMC_TIMING_MMC_HS400)
167 		ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
168 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
169 }
170 
sdhci_brcmstb_dumpregs(struct mmc_host * mmc)171 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
172 {
173 	sdhci_dumpregs(mmc_priv(mmc));
174 }
175 
sdhci_brcmstb_cqe_enable(struct mmc_host * mmc)176 static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)
177 {
178 	struct sdhci_host *host = mmc_priv(mmc);
179 	u32 reg;
180 
181 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
182 	while (reg & SDHCI_DATA_AVAILABLE) {
183 		sdhci_readl(host, SDHCI_BUFFER);
184 		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
185 	}
186 
187 	sdhci_cqe_enable(mmc);
188 }
189 
190 static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {
191 	.enable         = sdhci_brcmstb_cqe_enable,
192 	.disable        = sdhci_cqe_disable,
193 	.dumpregs       = sdhci_brcmstb_dumpregs,
194 };
195 
196 static struct sdhci_ops sdhci_brcmstb_ops = {
197 	.set_clock = sdhci_set_clock,
198 	.set_bus_width = sdhci_set_bus_width,
199 	.reset = sdhci_reset,
200 	.set_uhs_signaling = sdhci_set_uhs_signaling,
201 };
202 
203 static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
204 	.set_clock = sdhci_brcmstb_set_clock,
205 	.set_bus_width = sdhci_set_bus_width,
206 	.reset = brcmstb_reset,
207 	.set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
208 };
209 
210 static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = {
211 	.set_clock = sdhci_brcmstb_set_clock,
212 	.set_bus_width = sdhci_set_bus_width,
213 	.reset = brcmstb_reset_74165b0,
214 	.set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
215 };
216 
217 static struct brcmstb_match_priv match_priv_7425 = {
218 	.flags = BRCMSTB_MATCH_FLAGS_NO_64BIT |
219 	BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
220 	.ops = &sdhci_brcmstb_ops,
221 };
222 
223 static struct brcmstb_match_priv match_priv_7445 = {
224 	.flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
225 	.ops = &sdhci_brcmstb_ops,
226 };
227 
228 static const struct brcmstb_match_priv match_priv_7216 = {
229 	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
230 	.hs400es = sdhci_brcmstb_hs400es,
231 	.ops = &sdhci_brcmstb_ops_7216,
232 };
233 
234 static struct brcmstb_match_priv match_priv_74165b0 = {
235 	.flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
236 	.hs400es = sdhci_brcmstb_hs400es,
237 	.ops = &sdhci_brcmstb_ops_74165b0,
238 };
239 
240 static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {
241 	{ .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
242 	{ .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
243 	{ .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
244 	{ .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 },
245 	{},
246 };
247 
sdhci_brcmstb_cqhci_irq(struct sdhci_host * host,u32 intmask)248 static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
249 {
250 	int cmd_error = 0;
251 	int data_error = 0;
252 
253 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
254 		return intmask;
255 
256 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
257 
258 	return 0;
259 }
260 
sdhci_brcmstb_add_host(struct sdhci_host * host,struct sdhci_brcmstb_priv * priv)261 static int sdhci_brcmstb_add_host(struct sdhci_host *host,
262 				  struct sdhci_brcmstb_priv *priv)
263 {
264 	struct cqhci_host *cq_host;
265 	bool dma64;
266 	int ret;
267 
268 	if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0)
269 		return sdhci_add_host(host);
270 
271 	dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
272 	host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
273 	ret = sdhci_setup_host(host);
274 	if (ret)
275 		return ret;
276 
277 	cq_host = devm_kzalloc(mmc_dev(host->mmc),
278 			       sizeof(*cq_host), GFP_KERNEL);
279 	if (!cq_host) {
280 		ret = -ENOMEM;
281 		goto cleanup;
282 	}
283 
284 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
285 	cq_host->ops = &sdhci_brcmstb_cqhci_ops;
286 
287 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
288 	if (dma64) {
289 		dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
290 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
291 	}
292 
293 	ret = cqhci_init(cq_host, host->mmc, dma64);
294 	if (ret)
295 		goto cleanup;
296 
297 	ret = __sdhci_add_host(host);
298 	if (ret)
299 		goto cleanup;
300 
301 	return 0;
302 
303 cleanup:
304 	sdhci_cleanup_host(host);
305 	return ret;
306 }
307 
sdhci_brcmstb_probe(struct platform_device * pdev)308 static int sdhci_brcmstb_probe(struct platform_device *pdev)
309 {
310 	const struct brcmstb_match_priv *match_priv;
311 	struct sdhci_pltfm_data brcmstb_pdata;
312 	struct sdhci_pltfm_host *pltfm_host;
313 	const struct of_device_id *match;
314 	struct sdhci_brcmstb_priv *priv;
315 	u32 actual_clock_mhz;
316 	struct sdhci_host *host;
317 	struct clk *clk;
318 	struct clk *base_clk = NULL;
319 	int res;
320 
321 	match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);
322 	match_priv = match->data;
323 
324 	dev_dbg(&pdev->dev, "Probe found match for %s\n",  match->compatible);
325 
326 	clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
327 	if (IS_ERR(clk))
328 		return dev_err_probe(&pdev->dev, PTR_ERR(clk),
329 				     "Failed to get and enable clock from Device Tree\n");
330 
331 	memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));
332 	brcmstb_pdata.ops = match_priv->ops;
333 	host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
334 				sizeof(struct sdhci_brcmstb_priv));
335 	if (IS_ERR(host))
336 		return PTR_ERR(host);
337 
338 	pltfm_host = sdhci_priv(host);
339 	priv = sdhci_pltfm_priv(pltfm_host);
340 	if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
341 		priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
342 		match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
343 	}
344 
345 	/* Map in the non-standard CFG registers */
346 	priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
347 	if (IS_ERR(priv->cfg_regs)) {
348 		res = PTR_ERR(priv->cfg_regs);
349 		goto err;
350 	}
351 
352 	sdhci_get_of_property(pdev);
353 	res = mmc_of_parse(host->mmc);
354 	if (res)
355 		goto err;
356 
357 	/*
358 	 * Automatic clock gating does not work for SD cards that may
359 	 * voltage switch so only enable it for non-removable devices.
360 	 */
361 	if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) &&
362 	    (host->mmc->caps & MMC_CAP_NONREMOVABLE))
363 		priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK;
364 
365 	/*
366 	 * If the chip has enhanced strobe and it's enabled, add
367 	 * callback
368 	 */
369 	if (match_priv->hs400es &&
370 	    (host->mmc->caps2 & MMC_CAP2_HS400_ES))
371 		host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
372 
373 	/*
374 	 * Supply the existing CAPS, but clear the UHS modes. This
375 	 * will allow these modes to be specified by device tree
376 	 * properties through mmc_of_parse().
377 	 */
378 	sdhci_read_caps(host);
379 	if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT)
380 		host->caps &= ~SDHCI_CAN_64BIT;
381 	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
382 			 SDHCI_SUPPORT_DDR50);
383 
384 	if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT)
385 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
386 
387 	/* Change the base clock frequency if the DT property exists */
388 	if (device_property_read_u32(&pdev->dev, "clock-frequency",
389 				     &priv->base_freq_hz) != 0)
390 		goto add_host;
391 
392 	base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq");
393 	if (IS_ERR(base_clk)) {
394 		dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n");
395 		goto add_host;
396 	}
397 
398 	res = clk_prepare_enable(base_clk);
399 	if (res)
400 		goto err;
401 
402 	/* set improved clock rate */
403 	clk_set_rate(base_clk, priv->base_freq_hz);
404 	actual_clock_mhz = clk_get_rate(base_clk) / 1000000;
405 
406 	host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
407 	host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT);
408 	/* Disable presets because they are now incorrect */
409 	host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
410 
411 	dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n",
412 		actual_clock_mhz);
413 	priv->base_clk = base_clk;
414 
415 add_host:
416 	res = sdhci_brcmstb_add_host(host, priv);
417 	if (res)
418 		goto err;
419 
420 	pltfm_host->clk = clk;
421 	return res;
422 
423 err:
424 	sdhci_pltfm_free(pdev);
425 	clk_disable_unprepare(base_clk);
426 	return res;
427 }
428 
sdhci_brcmstb_shutdown(struct platform_device * pdev)429 static void sdhci_brcmstb_shutdown(struct platform_device *pdev)
430 {
431 	sdhci_pltfm_suspend(&pdev->dev);
432 }
433 
434 MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
435 
436 #ifdef CONFIG_PM_SLEEP
sdhci_brcmstb_suspend(struct device * dev)437 static int sdhci_brcmstb_suspend(struct device *dev)
438 {
439 	struct sdhci_host *host = dev_get_drvdata(dev);
440 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
441 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
442 
443 	clk_disable_unprepare(priv->base_clk);
444 	return sdhci_pltfm_suspend(dev);
445 }
446 
sdhci_brcmstb_resume(struct device * dev)447 static int sdhci_brcmstb_resume(struct device *dev)
448 {
449 	struct sdhci_host *host = dev_get_drvdata(dev);
450 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
451 	struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
452 	int ret;
453 
454 	ret = sdhci_pltfm_resume(dev);
455 	if (!ret && priv->base_freq_hz) {
456 		ret = clk_prepare_enable(priv->base_clk);
457 		/*
458 		 * Note: using clk_get_rate() below as clk_get_rate()
459 		 * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate()
460 		 * may do implicit get_rate() calls that do not honor
461 		 * CLK_GET_RATE_NOCACHE.
462 		 */
463 		if (!ret &&
464 		    (clk_get_rate(priv->base_clk) != priv->base_freq_hz))
465 			ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
466 	}
467 
468 	return ret;
469 }
470 #endif
471 
472 static const struct dev_pm_ops sdhci_brcmstb_pmops = {
473 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume)
474 };
475 
476 static struct platform_driver sdhci_brcmstb_driver = {
477 	.driver		= {
478 		.name	= "sdhci-brcmstb",
479 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
480 		.pm	= &sdhci_brcmstb_pmops,
481 		.of_match_table = of_match_ptr(sdhci_brcm_of_match),
482 	},
483 	.probe		= sdhci_brcmstb_probe,
484 	.remove_new	= sdhci_pltfm_remove,
485 	.shutdown	= sdhci_brcmstb_shutdown,
486 };
487 
488 module_platform_driver(sdhci_brcmstb_driver);
489 
490 MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
491 MODULE_AUTHOR("Broadcom");
492 MODULE_LICENSE("GPL v2");
493