1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * camss-csid-4-7.c
4 *
5 * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
6 *
7 * Copyright (C) 2020 Linaro Ltd.
8 */
9 #include <linux/completion.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/of.h>
14
15 #include "camss-csid.h"
16 #include "camss-csid-gen2.h"
17 #include "camss.h"
18
19 /* The CSID 2 IP-block is different from the others,
20 * and is of a bare-bones Lite version, with no PIX
21 * interface support. As a result of that it has an
22 * alternate register layout.
23 */
24
25 #define CSID_HW_VERSION 0x0
26 #define HW_VERSION_STEPPING 0
27 #define HW_VERSION_REVISION 16
28 #define HW_VERSION_GENERATION 28
29
30 #define CSID_RST_STROBES 0x10
31 #define RST_STROBES 0
32
33 #define CSID_CSI2_RX_IRQ_STATUS 0x20
34 #define CSID_CSI2_RX_IRQ_MASK 0x24
35 #define CSID_CSI2_RX_IRQ_CLEAR 0x28
36
37 #define CSID_CSI2_RDIN_IRQ_STATUS(rdi) ((csid_is_lite(csid) ? 0x30 : 0x40) \
38 + 0x10 * (rdi))
39 #define CSID_CSI2_RDIN_IRQ_MASK(rdi) ((csid_is_lite(csid) ? 0x34 : 0x44) \
40 + 0x10 * (rdi))
41 #define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) ((csid_is_lite(csid) ? 0x38 : 0x48) \
42 + 0x10 * (rdi))
43 #define CSID_CSI2_RDIN_IRQ_SET(rdi) ((csid_is_lite(csid) ? 0x3C : 0x4C) \
44 + 0x10 * (rdi))
45
46 #define CSID_TOP_IRQ_STATUS 0x70
47 #define TOP_IRQ_STATUS_RESET_DONE 0
48 #define CSID_TOP_IRQ_MASK 0x74
49 #define CSID_TOP_IRQ_CLEAR 0x78
50 #define CSID_TOP_IRQ_SET 0x7C
51 #define CSID_IRQ_CMD 0x80
52 #define IRQ_CMD_CLEAR 0
53 #define IRQ_CMD_SET 4
54
55 #define CSID_CSI2_RX_CFG0 0x100
56 #define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
57 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4
58 #define CSI2_RX_CFG0_DL1_INPUT_SEL 8
59 #define CSI2_RX_CFG0_DL2_INPUT_SEL 12
60 #define CSI2_RX_CFG0_DL3_INPUT_SEL 16
61 #define CSI2_RX_CFG0_PHY_NUM_SEL 20
62 #define CSI2_RX_CFG0_PHY_TYPE_SEL 24
63
64 #define CSID_CSI2_RX_CFG1 0x104
65 #define CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN 0
66 #define CSI2_RX_CFG1_DE_SCRAMBLE_EN 1
67 #define CSI2_RX_CFG1_VC_MODE 2
68 #define CSI2_RX_CFG1_COMPLETE_STREAM_EN 4
69 #define CSI2_RX_CFG1_COMPLETE_STREAM_FRAME_TIMING 5
70 #define CSI2_RX_CFG1_MISR_EN 6
71 #define CSI2_RX_CFG1_CGC_MODE 7
72 #define CGC_MODE_DYNAMIC_GATING 0
73 #define CGC_MODE_ALWAYS_ON 1
74
75 #define CSID_RDI_CFG0(rdi) ((csid_is_lite(csid) ? 0x200 : 0x300) \
76 + 0x100 * (rdi))
77 #define RDI_CFG0_BYTE_CNTR_EN 0
78 #define RDI_CFG0_FORMAT_MEASURE_EN 1
79 #define RDI_CFG0_TIMESTAMP_EN 2
80 #define RDI_CFG0_DROP_H_EN 3
81 #define RDI_CFG0_DROP_V_EN 4
82 #define RDI_CFG0_CROP_H_EN 5
83 #define RDI_CFG0_CROP_V_EN 6
84 #define RDI_CFG0_MISR_EN 7
85 #define RDI_CFG0_CGC_MODE 8
86 #define CGC_MODE_DYNAMIC 0
87 #define CGC_MODE_ALWAYS_ON 1
88 #define RDI_CFG0_PLAIN_ALIGNMENT 9
89 #define PLAIN_ALIGNMENT_LSB 0
90 #define PLAIN_ALIGNMENT_MSB 1
91 #define RDI_CFG0_PLAIN_FORMAT 10
92 #define RDI_CFG0_DECODE_FORMAT 12
93 #define RDI_CFG0_DATA_TYPE 16
94 #define RDI_CFG0_VIRTUAL_CHANNEL 22
95 #define RDI_CFG0_DT_ID 27
96 #define RDI_CFG0_EARLY_EOF_EN 29
97 #define RDI_CFG0_PACKING_FORMAT 30
98 #define RDI_CFG0_ENABLE 31
99
100 #define CSID_RDI_CFG1(rdi) ((csid_is_lite(csid) ? 0x204 : 0x304)\
101 + 0x100 * (rdi))
102 #define RDI_CFG1_TIMESTAMP_STB_SEL 0
103
104 #define CSID_RDI_CTRL(rdi) ((csid_is_lite(csid) ? 0x208 : 0x308)\
105 + 0x100 * (rdi))
106 #define RDI_CTRL_HALT_CMD 0
107 #define HALT_CMD_HALT_AT_FRAME_BOUNDARY 0
108 #define HALT_CMD_RESUME_AT_FRAME_BOUNDARY 1
109 #define RDI_CTRL_HALT_MODE 2
110
111 #define CSID_RDI_FRM_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x20C : 0x30C)\
112 + 0x100 * (rdi))
113 #define CSID_RDI_FRM_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x210 : 0x310)\
114 + 0x100 * (rdi))
115 #define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) ((csid_is_lite(csid) ? 0x214 : 0x314)\
116 + 0x100 * (rdi))
117 #define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) ((csid_is_lite(csid) ? 0x218 : 0x318)\
118 + 0x100 * (rdi))
119 #define CSID_RDI_RPP_PIX_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x224 : 0x324)\
120 + 0x100 * (rdi))
121 #define CSID_RDI_RPP_PIX_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x228 : 0x328)\
122 + 0x100 * (rdi))
123 #define CSID_RDI_RPP_LINE_DROP_PATTERN(rdi) ((csid_is_lite(csid) ? 0x22C : 0x32C)\
124 + 0x100 * (rdi))
125 #define CSID_RDI_RPP_LINE_DROP_PERIOD(rdi) ((csid_is_lite(csid) ? 0x230 : 0x330)\
126 + 0x100 * (rdi))
127
128 #define CSID_TPG_CTRL 0x600
129 #define TPG_CTRL_TEST_EN 0
130 #define TPG_CTRL_FS_PKT_EN 1
131 #define TPG_CTRL_FE_PKT_EN 2
132 #define TPG_CTRL_NUM_ACTIVE_LANES 4
133 #define TPG_CTRL_CYCLES_BETWEEN_PKTS 8
134 #define TPG_CTRL_NUM_TRAIL_BYTES 20
135
136 #define CSID_TPG_VC_CFG0 0x604
137 #define TPG_VC_CFG0_VC_NUM 0
138 #define TPG_VC_CFG0_NUM_ACTIVE_SLOTS 8
139 #define NUM_ACTIVE_SLOTS_0_ENABLED 0
140 #define NUM_ACTIVE_SLOTS_0_1_ENABLED 1
141 #define NUM_ACTIVE_SLOTS_0_1_2_ENABLED 2
142 #define NUM_ACTIVE_SLOTS_0_1_3_ENABLED 3
143 #define TPG_VC_CFG0_LINE_INTERLEAVING_MODE 10
144 #define INTELEAVING_MODE_INTERLEAVED 0
145 #define INTELEAVING_MODE_ONE_SHOT 1
146 #define TPG_VC_CFG0_NUM_FRAMES 16
147
148 #define CSID_TPG_VC_CFG1 0x608
149 #define TPG_VC_CFG1_H_BLANKING_COUNT 0
150 #define TPG_VC_CFG1_V_BLANKING_COUNT 12
151 #define TPG_VC_CFG1_V_BLANK_FRAME_WIDTH_SEL 24
152
153 #define CSID_TPG_LFSR_SEED 0x60C
154
155 #define CSID_TPG_DT_n_CFG_0(n) (0x610 + (n) * 0xC)
156 #define TPG_DT_n_CFG_0_FRAME_HEIGHT 0
157 #define TPG_DT_n_CFG_0_FRAME_WIDTH 16
158
159 #define CSID_TPG_DT_n_CFG_1(n) (0x614 + (n) * 0xC)
160 #define TPG_DT_n_CFG_1_DATA_TYPE 0
161 #define TPG_DT_n_CFG_1_ECC_XOR_MASK 8
162 #define TPG_DT_n_CFG_1_CRC_XOR_MASK 16
163
164 #define CSID_TPG_DT_n_CFG_2(n) (0x618 + (n) * 0xC)
165 #define TPG_DT_n_CFG_2_PAYLOAD_MODE 0
166 #define TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD 4
167 #define TPG_DT_n_CFG_2_ENCODE_FORMAT 16
168
169 #define CSID_TPG_COLOR_BARS_CFG 0x640
170 #define TPG_COLOR_BARS_CFG_UNICOLOR_BAR_EN 0
171 #define TPG_COLOR_BARS_CFG_UNICOLOR_BAR_SEL 4
172 #define TPG_COLOR_BARS_CFG_SPLIT_EN 5
173 #define TPG_COLOR_BARS_CFG_ROTATE_PERIOD 8
174
175 #define CSID_TPG_COLOR_BOX_CFG 0x644
176 #define TPG_COLOR_BOX_CFG_MODE 0
177 #define TPG_COLOR_BOX_PATTERN_SEL 2
178
179 static const struct csid_format csid_formats[] = {
180 {
181 MEDIA_BUS_FMT_UYVY8_1X16,
182 DATA_TYPE_YUV422_8BIT,
183 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
184 8,
185 2,
186 },
187 {
188 MEDIA_BUS_FMT_VYUY8_1X16,
189 DATA_TYPE_YUV422_8BIT,
190 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
191 8,
192 2,
193 },
194 {
195 MEDIA_BUS_FMT_YUYV8_1X16,
196 DATA_TYPE_YUV422_8BIT,
197 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
198 8,
199 2,
200 },
201 {
202 MEDIA_BUS_FMT_YVYU8_1X16,
203 DATA_TYPE_YUV422_8BIT,
204 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
205 8,
206 2,
207 },
208 {
209 MEDIA_BUS_FMT_SBGGR8_1X8,
210 DATA_TYPE_RAW_8BIT,
211 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
212 8,
213 1,
214 },
215 {
216 MEDIA_BUS_FMT_SGBRG8_1X8,
217 DATA_TYPE_RAW_8BIT,
218 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
219 8,
220 1,
221 },
222 {
223 MEDIA_BUS_FMT_SGRBG8_1X8,
224 DATA_TYPE_RAW_8BIT,
225 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
226 8,
227 1,
228 },
229 {
230 MEDIA_BUS_FMT_SRGGB8_1X8,
231 DATA_TYPE_RAW_8BIT,
232 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
233 8,
234 1,
235 },
236 {
237 MEDIA_BUS_FMT_SBGGR10_1X10,
238 DATA_TYPE_RAW_10BIT,
239 DECODE_FORMAT_UNCOMPRESSED_10_BIT,
240 10,
241 1,
242 },
243 {
244 MEDIA_BUS_FMT_SGBRG10_1X10,
245 DATA_TYPE_RAW_10BIT,
246 DECODE_FORMAT_UNCOMPRESSED_10_BIT,
247 10,
248 1,
249 },
250 {
251 MEDIA_BUS_FMT_SGRBG10_1X10,
252 DATA_TYPE_RAW_10BIT,
253 DECODE_FORMAT_UNCOMPRESSED_10_BIT,
254 10,
255 1,
256 },
257 {
258 MEDIA_BUS_FMT_SRGGB10_1X10,
259 DATA_TYPE_RAW_10BIT,
260 DECODE_FORMAT_UNCOMPRESSED_10_BIT,
261 10,
262 1,
263 },
264 {
265 MEDIA_BUS_FMT_Y8_1X8,
266 DATA_TYPE_RAW_8BIT,
267 DECODE_FORMAT_UNCOMPRESSED_8_BIT,
268 8,
269 1,
270 },
271 {
272 MEDIA_BUS_FMT_Y10_1X10,
273 DATA_TYPE_RAW_10BIT,
274 DECODE_FORMAT_UNCOMPRESSED_10_BIT,
275 10,
276 1,
277 },
278 {
279 MEDIA_BUS_FMT_SBGGR12_1X12,
280 DATA_TYPE_RAW_12BIT,
281 DECODE_FORMAT_UNCOMPRESSED_12_BIT,
282 12,
283 1,
284 },
285 {
286 MEDIA_BUS_FMT_SGBRG12_1X12,
287 DATA_TYPE_RAW_12BIT,
288 DECODE_FORMAT_UNCOMPRESSED_12_BIT,
289 12,
290 1,
291 },
292 {
293 MEDIA_BUS_FMT_SGRBG12_1X12,
294 DATA_TYPE_RAW_12BIT,
295 DECODE_FORMAT_UNCOMPRESSED_12_BIT,
296 12,
297 1,
298 },
299 {
300 MEDIA_BUS_FMT_SRGGB12_1X12,
301 DATA_TYPE_RAW_12BIT,
302 DECODE_FORMAT_UNCOMPRESSED_12_BIT,
303 12,
304 1,
305 },
306 {
307 MEDIA_BUS_FMT_SBGGR14_1X14,
308 DATA_TYPE_RAW_14BIT,
309 DECODE_FORMAT_UNCOMPRESSED_14_BIT,
310 14,
311 1,
312 },
313 {
314 MEDIA_BUS_FMT_SGBRG14_1X14,
315 DATA_TYPE_RAW_14BIT,
316 DECODE_FORMAT_UNCOMPRESSED_14_BIT,
317 14,
318 1,
319 },
320 {
321 MEDIA_BUS_FMT_SGRBG14_1X14,
322 DATA_TYPE_RAW_14BIT,
323 DECODE_FORMAT_UNCOMPRESSED_14_BIT,
324 14,
325 1,
326 },
327 {
328 MEDIA_BUS_FMT_SRGGB14_1X14,
329 DATA_TYPE_RAW_14BIT,
330 DECODE_FORMAT_UNCOMPRESSED_14_BIT,
331 14,
332 1,
333 },
334 };
335
__csid_configure_stream(struct csid_device * csid,u8 enable,u8 vc)336 static void __csid_configure_stream(struct csid_device *csid, u8 enable, u8 vc)
337 {
338 struct csid_testgen_config *tg = &csid->testgen;
339 u32 val;
340 u32 phy_sel = 0;
341 u8 lane_cnt = csid->phy.lane_cnt;
342 /* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */
343 struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
344 const struct csid_format *format = csid_get_fmt_entry(csid->formats, csid->nformats,
345 input_format->code);
346
347 if (!lane_cnt)
348 lane_cnt = 4;
349
350 if (!tg->enabled)
351 phy_sel = csid->phy.csiphy_id;
352
353 if (enable) {
354 /*
355 * DT_ID is a two bit bitfield that is concatenated with
356 * the four least significant bits of the five bit VC
357 * bitfield to generate an internal CID value.
358 *
359 * CSID_RDI_CFG0(vc)
360 * DT_ID : 28:27
361 * VC : 26:22
362 * DT : 21:16
363 *
364 * CID : VC 3:0 << 2 | DT_ID 1:0
365 */
366 u8 dt_id = vc & 0x03;
367
368 if (tg->enabled) {
369 /* configure one DT, infinite frames */
370 val = vc << TPG_VC_CFG0_VC_NUM;
371 val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE;
372 val |= 0 << TPG_VC_CFG0_NUM_FRAMES;
373 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);
374
375 val = 0x740 << TPG_VC_CFG1_H_BLANKING_COUNT;
376 val |= 0x3ff << TPG_VC_CFG1_V_BLANKING_COUNT;
377 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);
378
379 writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);
380
381 val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;
382 val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;
383 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
384
385 val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE;
386 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
387
388 val = (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE;
389 val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;
390 val |= format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT;
391 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));
392
393 writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG);
394
395 writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG);
396 }
397
398 val = 1 << RDI_CFG0_BYTE_CNTR_EN;
399 val |= 1 << RDI_CFG0_FORMAT_MEASURE_EN;
400 val |= 1 << RDI_CFG0_TIMESTAMP_EN;
401 /* note: for non-RDI path, this should be format->decode_format */
402 val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
403 val |= format->data_type << RDI_CFG0_DATA_TYPE;
404 val |= vc << RDI_CFG0_VIRTUAL_CHANNEL;
405 val |= dt_id << RDI_CFG0_DT_ID;
406 writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
407
408 /* CSID_TIMESTAMP_STB_POST_IRQ */
409 val = 2 << RDI_CFG1_TIMESTAMP_STB_SEL;
410 writel_relaxed(val, csid->base + CSID_RDI_CFG1(vc));
411
412 val = 1;
413 writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PERIOD(vc));
414
415 val = 0;
416 writel_relaxed(val, csid->base + CSID_RDI_FRM_DROP_PATTERN(vc));
417
418 val = 1;
419 writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc));
420
421 val = 0;
422 writel_relaxed(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc));
423
424 val = 1;
425 writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PERIOD(vc));
426
427 val = 0;
428 writel_relaxed(val, csid->base + CSID_RDI_RPP_PIX_DROP_PATTERN(vc));
429
430 val = 1;
431 writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PERIOD(vc));
432
433 val = 0;
434 writel_relaxed(val, csid->base + CSID_RDI_RPP_LINE_DROP_PATTERN(vc));
435
436 val = 0;
437 writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));
438
439 val = readl_relaxed(csid->base + CSID_RDI_CFG0(vc));
440 val |= 1 << RDI_CFG0_ENABLE;
441 writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
442 }
443
444 if (tg->enabled) {
445 val = enable << TPG_CTRL_TEST_EN;
446 val |= 1 << TPG_CTRL_FS_PKT_EN;
447 val |= 1 << TPG_CTRL_FE_PKT_EN;
448 val |= (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES;
449 val |= 0x64 << TPG_CTRL_CYCLES_BETWEEN_PKTS;
450 val |= 0xA << TPG_CTRL_NUM_TRAIL_BYTES;
451 writel_relaxed(val, csid->base + CSID_TPG_CTRL);
452 }
453
454 val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
455 val |= csid->phy.lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
456 val |= phy_sel << CSI2_RX_CFG0_PHY_NUM_SEL;
457 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG0);
458
459 val = 1 << CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN;
460 if (vc > 3)
461 val |= 1 << CSI2_RX_CFG1_VC_MODE;
462 val |= 1 << CSI2_RX_CFG1_MISR_EN;
463 writel_relaxed(val, csid->base + CSID_CSI2_RX_CFG1);
464
465 if (enable)
466 val = HALT_CMD_RESUME_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
467 else
468 val = HALT_CMD_HALT_AT_FRAME_BOUNDARY << RDI_CTRL_HALT_CMD;
469 writel_relaxed(val, csid->base + CSID_RDI_CTRL(vc));
470 }
471
csid_configure_stream(struct csid_device * csid,u8 enable)472 static void csid_configure_stream(struct csid_device *csid, u8 enable)
473 {
474 u8 i;
475 /* Loop through all enabled VCs and configure stream for each */
476 for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
477 if (csid->phy.en_vc & BIT(i))
478 __csid_configure_stream(csid, enable, i);
479 }
480
csid_configure_testgen_pattern(struct csid_device * csid,s32 val)481 static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val)
482 {
483 if (val > 0 && val <= csid->testgen.nmodes)
484 csid->testgen.mode = val;
485
486 return 0;
487 }
488
489 /*
490 * csid_hw_version - CSID hardware version query
491 * @csid: CSID device
492 *
493 * Return HW version or error
494 */
csid_hw_version(struct csid_device * csid)495 static u32 csid_hw_version(struct csid_device *csid)
496 {
497 u32 hw_version;
498 u32 hw_gen;
499 u32 hw_rev;
500 u32 hw_step;
501
502 hw_version = readl_relaxed(csid->base + CSID_HW_VERSION);
503 hw_gen = (hw_version >> HW_VERSION_GENERATION) & 0xF;
504 hw_rev = (hw_version >> HW_VERSION_REVISION) & 0xFFF;
505 hw_step = (hw_version >> HW_VERSION_STEPPING) & 0xFFFF;
506 dev_dbg(csid->camss->dev, "CSID HW Version = %u.%u.%u\n",
507 hw_gen, hw_rev, hw_step);
508
509 return hw_version;
510 }
511
512 /*
513 * csid_isr - CSID module interrupt service routine
514 * @irq: Interrupt line
515 * @dev: CSID device
516 *
517 * Return IRQ_HANDLED on success
518 */
csid_isr(int irq,void * dev)519 static irqreturn_t csid_isr(int irq, void *dev)
520 {
521 struct csid_device *csid = dev;
522 u32 val;
523 u8 reset_done;
524 int i;
525
526 val = readl_relaxed(csid->base + CSID_TOP_IRQ_STATUS);
527 writel_relaxed(val, csid->base + CSID_TOP_IRQ_CLEAR);
528 reset_done = val & BIT(TOP_IRQ_STATUS_RESET_DONE);
529
530 val = readl_relaxed(csid->base + CSID_CSI2_RX_IRQ_STATUS);
531 writel_relaxed(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR);
532
533 /* Read and clear IRQ status for each enabled RDI channel */
534 for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++)
535 if (csid->phy.en_vc & BIT(i)) {
536 val = readl_relaxed(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
537 writel_relaxed(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
538 }
539
540 val = 1 << IRQ_CMD_CLEAR;
541 writel_relaxed(val, csid->base + CSID_IRQ_CMD);
542
543 if (reset_done)
544 complete(&csid->reset_complete);
545
546 return IRQ_HANDLED;
547 }
548
549 /*
550 * csid_reset - Trigger reset on CSID module and wait to complete
551 * @csid: CSID device
552 *
553 * Return 0 on success or a negative error code otherwise
554 */
csid_reset(struct csid_device * csid)555 static int csid_reset(struct csid_device *csid)
556 {
557 unsigned long time;
558 u32 val;
559
560 reinit_completion(&csid->reset_complete);
561
562 writel_relaxed(1, csid->base + CSID_TOP_IRQ_CLEAR);
563 writel_relaxed(1, csid->base + CSID_IRQ_CMD);
564 writel_relaxed(1, csid->base + CSID_TOP_IRQ_MASK);
565 writel_relaxed(1, csid->base + CSID_IRQ_CMD);
566
567 /* preserve registers */
568 val = 0x1e << RST_STROBES;
569 writel_relaxed(val, csid->base + CSID_RST_STROBES);
570
571 time = wait_for_completion_timeout(&csid->reset_complete,
572 msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
573 if (!time) {
574 dev_err(csid->camss->dev, "CSID reset timeout\n");
575 return -EIO;
576 }
577
578 return 0;
579 }
580
csid_src_pad_code(struct csid_device * csid,u32 sink_code,unsigned int match_format_idx,u32 match_code)581 static u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code,
582 unsigned int match_format_idx, u32 match_code)
583 {
584 switch (sink_code) {
585 case MEDIA_BUS_FMT_SBGGR10_1X10:
586 {
587 u32 src_code[] = {
588 MEDIA_BUS_FMT_SBGGR10_1X10,
589 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
590 };
591
592 return csid_find_code(src_code, ARRAY_SIZE(src_code),
593 match_format_idx, match_code);
594 }
595 case MEDIA_BUS_FMT_Y10_1X10:
596 {
597 u32 src_code[] = {
598 MEDIA_BUS_FMT_Y10_1X10,
599 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
600 };
601
602 return csid_find_code(src_code, ARRAY_SIZE(src_code),
603 match_format_idx, match_code);
604 }
605 default:
606 if (match_format_idx > 0)
607 return 0;
608
609 return sink_code;
610 }
611 }
612
csid_subdev_init(struct csid_device * csid)613 static void csid_subdev_init(struct csid_device *csid)
614 {
615 csid->formats = csid_formats;
616 csid->nformats = ARRAY_SIZE(csid_formats);
617 csid->testgen.modes = csid_testgen_modes;
618 csid->testgen.nmodes = CSID_PAYLOAD_MODE_NUM_SUPPORTED_GEN2;
619 }
620
621 const struct csid_hw_ops csid_ops_gen2 = {
622 .configure_stream = csid_configure_stream,
623 .configure_testgen_pattern = csid_configure_testgen_pattern,
624 .hw_version = csid_hw_version,
625 .isr = csid_isr,
626 .reset = csid_reset,
627 .src_pad_code = csid_src_pad_code,
628 .subdev_init = csid_subdev_init,
629 };
630