1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the Sony IMX415 CMOS Image Sensor.
4 *
5 * Copyright (C) 2023 WolfVision GmbH.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/videodev2.h>
18
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22
23 #define IMX415_PIXEL_ARRAY_TOP 0
24 #define IMX415_PIXEL_ARRAY_LEFT 0
25 #define IMX415_PIXEL_ARRAY_WIDTH 3864
26 #define IMX415_PIXEL_ARRAY_HEIGHT 2192
27 #define IMX415_PIXEL_ARRAY_VBLANK 58
28
29 #define IMX415_NUM_CLK_PARAM_REGS 11
30
31 #define IMX415_REG_8BIT(n) ((1 << 16) | (n))
32 #define IMX415_REG_16BIT(n) ((2 << 16) | (n))
33 #define IMX415_REG_24BIT(n) ((3 << 16) | (n))
34 #define IMX415_REG_SIZE_SHIFT 16
35 #define IMX415_REG_ADDR_MASK 0xffff
36
37 #define IMX415_MODE IMX415_REG_8BIT(0x3000)
38 #define IMX415_MODE_OPERATING (0)
39 #define IMX415_MODE_STANDBY BIT(0)
40 #define IMX415_REGHOLD IMX415_REG_8BIT(0x3001)
41 #define IMX415_REGHOLD_INVALID (0)
42 #define IMX415_REGHOLD_VALID BIT(0)
43 #define IMX415_XMSTA IMX415_REG_8BIT(0x3002)
44 #define IMX415_XMSTA_START (0)
45 #define IMX415_XMSTA_STOP BIT(0)
46 #define IMX415_BCWAIT_TIME IMX415_REG_16BIT(0x3008)
47 #define IMX415_CPWAIT_TIME IMX415_REG_16BIT(0x300A)
48 #define IMX415_WINMODE IMX415_REG_8BIT(0x301C)
49 #define IMX415_ADDMODE IMX415_REG_8BIT(0x3022)
50 #define IMX415_REVERSE IMX415_REG_8BIT(0x3030)
51 #define IMX415_HREVERSE_SHIFT (0)
52 #define IMX415_VREVERSE_SHIFT BIT(0)
53 #define IMX415_ADBIT IMX415_REG_8BIT(0x3031)
54 #define IMX415_MDBIT IMX415_REG_8BIT(0x3032)
55 #define IMX415_SYS_MODE IMX415_REG_8BIT(0x3033)
56 #define IMX415_OUTSEL IMX415_REG_8BIT(0x30C0)
57 #define IMX415_DRV IMX415_REG_8BIT(0x30C1)
58 #define IMX415_VMAX IMX415_REG_24BIT(0x3024)
59 #define IMX415_HMAX IMX415_REG_16BIT(0x3028)
60 #define IMX415_SHR0 IMX415_REG_24BIT(0x3050)
61 #define IMX415_GAIN_PCG_0 IMX415_REG_16BIT(0x3090)
62 #define IMX415_AGAIN_MIN 0
63 #define IMX415_AGAIN_MAX 100
64 #define IMX415_AGAIN_STEP 1
65 #define IMX415_BLKLEVEL IMX415_REG_16BIT(0x30E2)
66 #define IMX415_BLKLEVEL_DEFAULT 50
67 #define IMX415_TPG_EN_DUOUT IMX415_REG_8BIT(0x30E4)
68 #define IMX415_TPG_PATSEL_DUOUT IMX415_REG_8BIT(0x30E6)
69 #define IMX415_TPG_COLORWIDTH IMX415_REG_8BIT(0x30E8)
70 #define IMX415_TESTCLKEN_MIPI IMX415_REG_8BIT(0x3110)
71 #define IMX415_INCKSEL1 IMX415_REG_8BIT(0x3115)
72 #define IMX415_INCKSEL2 IMX415_REG_8BIT(0x3116)
73 #define IMX415_INCKSEL3 IMX415_REG_16BIT(0x3118)
74 #define IMX415_INCKSEL4 IMX415_REG_16BIT(0x311A)
75 #define IMX415_INCKSEL5 IMX415_REG_8BIT(0x311E)
76 #define IMX415_DIG_CLP_MODE IMX415_REG_8BIT(0x32C8)
77 #define IMX415_WRJ_OPEN IMX415_REG_8BIT(0x3390)
78 #define IMX415_SENSOR_INFO IMX415_REG_16BIT(0x3F12)
79 #define IMX415_SENSOR_INFO_MASK 0xFFF
80 #define IMX415_CHIP_ID 0x514
81 #define IMX415_LANEMODE IMX415_REG_16BIT(0x4001)
82 #define IMX415_LANEMODE_2 1
83 #define IMX415_LANEMODE_4 3
84 #define IMX415_TXCLKESC_FREQ IMX415_REG_16BIT(0x4004)
85 #define IMX415_INCKSEL6 IMX415_REG_8BIT(0x400C)
86 #define IMX415_TCLKPOST IMX415_REG_16BIT(0x4018)
87 #define IMX415_TCLKPREPARE IMX415_REG_16BIT(0x401A)
88 #define IMX415_TCLKTRAIL IMX415_REG_16BIT(0x401C)
89 #define IMX415_TCLKZERO IMX415_REG_16BIT(0x401E)
90 #define IMX415_THSPREPARE IMX415_REG_16BIT(0x4020)
91 #define IMX415_THSZERO IMX415_REG_16BIT(0x4022)
92 #define IMX415_THSTRAIL IMX415_REG_16BIT(0x4024)
93 #define IMX415_THSEXIT IMX415_REG_16BIT(0x4026)
94 #define IMX415_TLPX IMX415_REG_16BIT(0x4028)
95 #define IMX415_INCKSEL7 IMX415_REG_8BIT(0x4074)
96
97 struct imx415_reg {
98 u32 address;
99 u32 val;
100 };
101
102 static const char *const imx415_supply_names[] = {
103 "dvdd",
104 "ovdd",
105 "avdd",
106 };
107
108 /*
109 * The IMX415 data sheet uses lane rates but v4l2 uses link frequency to
110 * describe MIPI CSI-2 speed. This driver uses lane rates wherever possible
111 * and converts them to link frequencies by a factor of two when needed.
112 */
113 static const s64 link_freq_menu_items[] = {
114 594000000 / 2, 720000000 / 2, 891000000 / 2,
115 1440000000 / 2, 1485000000 / 2,
116 };
117
118 struct imx415_clk_params {
119 u64 lane_rate;
120 u64 inck;
121 struct imx415_reg regs[IMX415_NUM_CLK_PARAM_REGS];
122 };
123
124 /* INCK Settings - includes all lane rate and INCK dependent registers */
125 static const struct imx415_clk_params imx415_clk_params[] = {
126 {
127 .lane_rate = 594000000,
128 .inck = 27000000,
129 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
130 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
131 .regs[2] = { IMX415_SYS_MODE, 0x7 },
132 .regs[3] = { IMX415_INCKSEL1, 0x00 },
133 .regs[4] = { IMX415_INCKSEL2, 0x23 },
134 .regs[5] = { IMX415_INCKSEL3, 0x084 },
135 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
136 .regs[7] = { IMX415_INCKSEL5, 0x23 },
137 .regs[8] = { IMX415_INCKSEL6, 0x0 },
138 .regs[9] = { IMX415_INCKSEL7, 0x1 },
139 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
140 },
141 {
142 .lane_rate = 720000000,
143 .inck = 24000000,
144 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
145 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
146 .regs[2] = { IMX415_SYS_MODE, 0x9 },
147 .regs[3] = { IMX415_INCKSEL1, 0x00 },
148 .regs[4] = { IMX415_INCKSEL2, 0x23 },
149 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
150 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
151 .regs[7] = { IMX415_INCKSEL5, 0x23 },
152 .regs[8] = { IMX415_INCKSEL6, 0x0 },
153 .regs[9] = { IMX415_INCKSEL7, 0x1 },
154 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
155 },
156 {
157 .lane_rate = 891000000,
158 .inck = 27000000,
159 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
160 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
161 .regs[2] = { IMX415_SYS_MODE, 0x5 },
162 .regs[3] = { IMX415_INCKSEL1, 0x00 },
163 .regs[4] = { IMX415_INCKSEL2, 0x23 },
164 .regs[5] = { IMX415_INCKSEL3, 0x0C6 },
165 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
166 .regs[7] = { IMX415_INCKSEL5, 0x23 },
167 .regs[8] = { IMX415_INCKSEL6, 0x0 },
168 .regs[9] = { IMX415_INCKSEL7, 0x1 },
169 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
170 },
171 {
172 .lane_rate = 1440000000,
173 .inck = 24000000,
174 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
175 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
176 .regs[2] = { IMX415_SYS_MODE, 0x8 },
177 .regs[3] = { IMX415_INCKSEL1, 0x00 },
178 .regs[4] = { IMX415_INCKSEL2, 0x23 },
179 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
180 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
181 .regs[7] = { IMX415_INCKSEL5, 0x23 },
182 .regs[8] = { IMX415_INCKSEL6, 0x1 },
183 .regs[9] = { IMX415_INCKSEL7, 0x0 },
184 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
185 },
186 {
187 .lane_rate = 1485000000,
188 .inck = 27000000,
189 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
190 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
191 .regs[2] = { IMX415_SYS_MODE, 0x8 },
192 .regs[3] = { IMX415_INCKSEL1, 0x00 },
193 .regs[4] = { IMX415_INCKSEL2, 0x23 },
194 .regs[5] = { IMX415_INCKSEL3, 0x0A5 },
195 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
196 .regs[7] = { IMX415_INCKSEL5, 0x23 },
197 .regs[8] = { IMX415_INCKSEL6, 0x1 },
198 .regs[9] = { IMX415_INCKSEL7, 0x0 },
199 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
200 },
201 };
202
203 /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
204 static const struct imx415_reg imx415_mode_2_720[] = {
205 { IMX415_VMAX, 0x08CA },
206 { IMX415_HMAX, 0x07F0 },
207 { IMX415_LANEMODE, IMX415_LANEMODE_2 },
208 { IMX415_TCLKPOST, 0x006F },
209 { IMX415_TCLKPREPARE, 0x002F },
210 { IMX415_TCLKTRAIL, 0x002F },
211 { IMX415_TCLKZERO, 0x00BF },
212 { IMX415_THSPREPARE, 0x002F },
213 { IMX415_THSZERO, 0x0057 },
214 { IMX415_THSTRAIL, 0x002F },
215 { IMX415_THSEXIT, 0x004F },
216 { IMX415_TLPX, 0x0027 },
217 };
218
219 /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
220 static const struct imx415_reg imx415_mode_2_1440[] = {
221 { IMX415_VMAX, 0x08CA },
222 { IMX415_HMAX, 0x042A },
223 { IMX415_LANEMODE, IMX415_LANEMODE_2 },
224 { IMX415_TCLKPOST, 0x009F },
225 { IMX415_TCLKPREPARE, 0x0057 },
226 { IMX415_TCLKTRAIL, 0x0057 },
227 { IMX415_TCLKZERO, 0x0187 },
228 { IMX415_THSPREPARE, 0x005F },
229 { IMX415_THSZERO, 0x00A7 },
230 { IMX415_THSTRAIL, 0x005F },
231 { IMX415_THSEXIT, 0x0097 },
232 { IMX415_TLPX, 0x004F },
233 };
234
235 /* all-pixel 4-lane 891 Mbps 30 Hz mode */
236 static const struct imx415_reg imx415_mode_4_891[] = {
237 { IMX415_VMAX, 0x08CA },
238 { IMX415_HMAX, 0x044C },
239 { IMX415_LANEMODE, IMX415_LANEMODE_4 },
240 { IMX415_TCLKPOST, 0x007F },
241 { IMX415_TCLKPREPARE, 0x0037 },
242 { IMX415_TCLKTRAIL, 0x0037 },
243 { IMX415_TCLKZERO, 0x00F7 },
244 { IMX415_THSPREPARE, 0x003F },
245 { IMX415_THSZERO, 0x006F },
246 { IMX415_THSTRAIL, 0x003F },
247 { IMX415_THSEXIT, 0x005F },
248 { IMX415_TLPX, 0x002F },
249 };
250
251 struct imx415_mode_reg_list {
252 u32 num_of_regs;
253 const struct imx415_reg *regs;
254 };
255
256 /*
257 * Mode : number of lanes, lane rate and frame rate dependent settings
258 *
259 * pixel_rate and hmax_pix are needed to calculate hblank for the v4l2 ctrl
260 * interface. These values can not be found in the data sheet and should be
261 * treated as virtual values. Use following table when adding new modes.
262 *
263 * lane_rate lanes fps hmax_pix pixel_rate
264 *
265 * 594 2 10.000 4400 99000000
266 * 891 2 15.000 4400 148500000
267 * 720 2 15.748 4064 144000000
268 * 1782 2 30.000 4400 297000000
269 * 2079 2 30.000 4400 297000000
270 * 1440 2 30.019 4510 304615385
271 *
272 * 594 4 20.000 5500 247500000
273 * 594 4 25.000 4400 247500000
274 * 720 4 25.000 4400 247500000
275 * 720 4 30.019 4510 304615385
276 * 891 4 30.000 4400 297000000
277 * 1440 4 30.019 4510 304615385
278 * 1440 4 60.038 4510 609230769
279 * 1485 4 60.000 4400 594000000
280 * 1782 4 60.000 4400 594000000
281 * 2079 4 60.000 4400 594000000
282 * 2376 4 90.164 4392 891000000
283 */
284 struct imx415_mode {
285 u64 lane_rate;
286 u32 lanes;
287 u32 hmax_pix;
288 u64 pixel_rate;
289 struct imx415_mode_reg_list reg_list;
290 };
291
292 /* mode configs */
293 static const struct imx415_mode supported_modes[] = {
294 {
295 .lane_rate = 720000000,
296 .lanes = 2,
297 .hmax_pix = 4064,
298 .pixel_rate = 144000000,
299 .reg_list = {
300 .num_of_regs = ARRAY_SIZE(imx415_mode_2_720),
301 .regs = imx415_mode_2_720,
302 },
303 },
304 {
305 .lane_rate = 1440000000,
306 .lanes = 2,
307 .hmax_pix = 4510,
308 .pixel_rate = 304615385,
309 .reg_list = {
310 .num_of_regs = ARRAY_SIZE(imx415_mode_2_1440),
311 .regs = imx415_mode_2_1440,
312 },
313 },
314 {
315 .lane_rate = 891000000,
316 .lanes = 4,
317 .hmax_pix = 4400,
318 .pixel_rate = 297000000,
319 .reg_list = {
320 .num_of_regs = ARRAY_SIZE(imx415_mode_4_891),
321 .regs = imx415_mode_4_891,
322 },
323 },
324 };
325
326 static const struct regmap_config imx415_regmap_config = {
327 .reg_bits = 16,
328 .val_bits = 8,
329 };
330
331 static const char *const imx415_test_pattern_menu[] = {
332 "disabled",
333 "solid black",
334 "solid white",
335 "solid dark gray",
336 "solid light gray",
337 "stripes light/dark grey",
338 "stripes dark/light grey",
339 "stripes black/dark grey",
340 "stripes dark grey/black",
341 "stripes black/white",
342 "stripes white/black",
343 "horizontal color bar",
344 "vertical color bar",
345 };
346
347 struct imx415 {
348 struct device *dev;
349 struct clk *clk;
350 struct regulator_bulk_data supplies[ARRAY_SIZE(imx415_supply_names)];
351 struct gpio_desc *reset;
352 struct regmap *regmap;
353
354 const struct imx415_clk_params *clk_params;
355
356 struct v4l2_subdev subdev;
357 struct media_pad pad;
358
359 struct v4l2_ctrl_handler ctrls;
360 struct v4l2_ctrl *vblank;
361 struct v4l2_ctrl *hflip;
362 struct v4l2_ctrl *vflip;
363
364 unsigned int cur_mode;
365 unsigned int num_data_lanes;
366 };
367
368 /*
369 * This table includes fixed register settings and a bunch of undocumented
370 * registers that have to be set to another value than default.
371 */
372 static const struct imx415_reg imx415_init_table[] = {
373 /* use all-pixel readout mode, no flip */
374 { IMX415_WINMODE, 0x00 },
375 { IMX415_ADDMODE, 0x00 },
376 { IMX415_REVERSE, 0x00 },
377 /* use RAW 10-bit mode */
378 { IMX415_ADBIT, 0x00 },
379 { IMX415_MDBIT, 0x00 },
380 /* output VSYNC on XVS and low on XHS */
381 { IMX415_OUTSEL, 0x22 },
382 { IMX415_DRV, 0x00 },
383
384 /* SONY magic registers */
385 { IMX415_REG_8BIT(0x32D4), 0x21 },
386 { IMX415_REG_8BIT(0x32EC), 0xA1 },
387 { IMX415_REG_8BIT(0x3452), 0x7F },
388 { IMX415_REG_8BIT(0x3453), 0x03 },
389 { IMX415_REG_8BIT(0x358A), 0x04 },
390 { IMX415_REG_8BIT(0x35A1), 0x02 },
391 { IMX415_REG_8BIT(0x36BC), 0x0C },
392 { IMX415_REG_8BIT(0x36CC), 0x53 },
393 { IMX415_REG_8BIT(0x36CD), 0x00 },
394 { IMX415_REG_8BIT(0x36CE), 0x3C },
395 { IMX415_REG_8BIT(0x36D0), 0x8C },
396 { IMX415_REG_8BIT(0x36D1), 0x00 },
397 { IMX415_REG_8BIT(0x36D2), 0x71 },
398 { IMX415_REG_8BIT(0x36D4), 0x3C },
399 { IMX415_REG_8BIT(0x36D6), 0x53 },
400 { IMX415_REG_8BIT(0x36D7), 0x00 },
401 { IMX415_REG_8BIT(0x36D8), 0x71 },
402 { IMX415_REG_8BIT(0x36DA), 0x8C },
403 { IMX415_REG_8BIT(0x36DB), 0x00 },
404 { IMX415_REG_8BIT(0x3724), 0x02 },
405 { IMX415_REG_8BIT(0x3726), 0x02 },
406 { IMX415_REG_8BIT(0x3732), 0x02 },
407 { IMX415_REG_8BIT(0x3734), 0x03 },
408 { IMX415_REG_8BIT(0x3736), 0x03 },
409 { IMX415_REG_8BIT(0x3742), 0x03 },
410 { IMX415_REG_8BIT(0x3862), 0xE0 },
411 { IMX415_REG_8BIT(0x38CC), 0x30 },
412 { IMX415_REG_8BIT(0x38CD), 0x2F },
413 { IMX415_REG_8BIT(0x395C), 0x0C },
414 { IMX415_REG_8BIT(0x3A42), 0xD1 },
415 { IMX415_REG_8BIT(0x3A4C), 0x77 },
416 { IMX415_REG_8BIT(0x3AE0), 0x02 },
417 { IMX415_REG_8BIT(0x3AEC), 0x0C },
418 { IMX415_REG_8BIT(0x3B00), 0x2E },
419 { IMX415_REG_8BIT(0x3B06), 0x29 },
420 { IMX415_REG_8BIT(0x3B98), 0x25 },
421 { IMX415_REG_8BIT(0x3B99), 0x21 },
422 { IMX415_REG_8BIT(0x3B9B), 0x13 },
423 { IMX415_REG_8BIT(0x3B9C), 0x13 },
424 { IMX415_REG_8BIT(0x3B9D), 0x13 },
425 { IMX415_REG_8BIT(0x3B9E), 0x13 },
426 { IMX415_REG_8BIT(0x3BA1), 0x00 },
427 { IMX415_REG_8BIT(0x3BA2), 0x06 },
428 { IMX415_REG_8BIT(0x3BA3), 0x0B },
429 { IMX415_REG_8BIT(0x3BA4), 0x10 },
430 { IMX415_REG_8BIT(0x3BA5), 0x14 },
431 { IMX415_REG_8BIT(0x3BA6), 0x18 },
432 { IMX415_REG_8BIT(0x3BA7), 0x1A },
433 { IMX415_REG_8BIT(0x3BA8), 0x1A },
434 { IMX415_REG_8BIT(0x3BA9), 0x1A },
435 { IMX415_REG_8BIT(0x3BAC), 0xED },
436 { IMX415_REG_8BIT(0x3BAD), 0x01 },
437 { IMX415_REG_8BIT(0x3BAE), 0xF6 },
438 { IMX415_REG_8BIT(0x3BAF), 0x02 },
439 { IMX415_REG_8BIT(0x3BB0), 0xA2 },
440 { IMX415_REG_8BIT(0x3BB1), 0x03 },
441 { IMX415_REG_8BIT(0x3BB2), 0xE0 },
442 { IMX415_REG_8BIT(0x3BB3), 0x03 },
443 { IMX415_REG_8BIT(0x3BB4), 0xE0 },
444 { IMX415_REG_8BIT(0x3BB5), 0x03 },
445 { IMX415_REG_8BIT(0x3BB6), 0xE0 },
446 { IMX415_REG_8BIT(0x3BB7), 0x03 },
447 { IMX415_REG_8BIT(0x3BB8), 0xE0 },
448 { IMX415_REG_8BIT(0x3BBA), 0xE0 },
449 { IMX415_REG_8BIT(0x3BBC), 0xDA },
450 { IMX415_REG_8BIT(0x3BBE), 0x88 },
451 { IMX415_REG_8BIT(0x3BC0), 0x44 },
452 { IMX415_REG_8BIT(0x3BC2), 0x7B },
453 { IMX415_REG_8BIT(0x3BC4), 0xA2 },
454 { IMX415_REG_8BIT(0x3BC8), 0xBD },
455 { IMX415_REG_8BIT(0x3BCA), 0xBD },
456 };
457
to_imx415(struct v4l2_subdev * sd)458 static inline struct imx415 *to_imx415(struct v4l2_subdev *sd)
459 {
460 return container_of(sd, struct imx415, subdev);
461 }
462
imx415_read(struct imx415 * sensor,u32 addr)463 static int imx415_read(struct imx415 *sensor, u32 addr)
464 {
465 u8 data[3] = { 0 };
466 int ret;
467
468 ret = regmap_raw_read(sensor->regmap, addr & IMX415_REG_ADDR_MASK, data,
469 (addr >> IMX415_REG_SIZE_SHIFT) & 3);
470 if (ret < 0)
471 return ret;
472
473 return (data[2] << 16) | (data[1] << 8) | data[0];
474 }
475
imx415_write(struct imx415 * sensor,u32 addr,u32 value)476 static int imx415_write(struct imx415 *sensor, u32 addr, u32 value)
477 {
478 u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 };
479 int ret;
480
481 ret = regmap_raw_write(sensor->regmap, addr & IMX415_REG_ADDR_MASK,
482 data, (addr >> IMX415_REG_SIZE_SHIFT) & 3);
483 if (ret < 0)
484 dev_err_ratelimited(sensor->dev,
485 "%u-bit write to 0x%04x failed: %d\n",
486 ((addr >> IMX415_REG_SIZE_SHIFT) & 3) * 8,
487 addr & IMX415_REG_ADDR_MASK, ret);
488
489 return 0;
490 }
491
imx415_set_testpattern(struct imx415 * sensor,int val)492 static int imx415_set_testpattern(struct imx415 *sensor, int val)
493 {
494 int ret;
495
496 if (val) {
497 ret = imx415_write(sensor, IMX415_BLKLEVEL, 0x00);
498 if (ret)
499 return ret;
500 ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x01);
501 if (ret)
502 return ret;
503 ret = imx415_write(sensor, IMX415_TPG_PATSEL_DUOUT, val - 1);
504 if (ret)
505 return ret;
506 ret = imx415_write(sensor, IMX415_TPG_COLORWIDTH, 0x01);
507 if (ret)
508 return ret;
509 ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x20);
510 if (ret)
511 return ret;
512 ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x00);
513 if (ret)
514 return ret;
515 ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x00);
516 } else {
517 ret = imx415_write(sensor, IMX415_BLKLEVEL,
518 IMX415_BLKLEVEL_DEFAULT);
519 if (ret)
520 return ret;
521 ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x00);
522 if (ret)
523 return ret;
524 ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x00);
525 if (ret)
526 return ret;
527 ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x01);
528 if (ret)
529 return ret;
530 ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x01);
531 }
532 return 0;
533 }
534
imx415_s_ctrl(struct v4l2_ctrl * ctrl)535 static int imx415_s_ctrl(struct v4l2_ctrl *ctrl)
536 {
537 struct imx415 *sensor = container_of(ctrl->handler, struct imx415,
538 ctrls);
539 const struct v4l2_mbus_framefmt *format;
540 struct v4l2_subdev_state *state;
541 unsigned int vmax;
542 unsigned int flip;
543 int ret;
544
545 if (!pm_runtime_get_if_in_use(sensor->dev))
546 return 0;
547
548 state = v4l2_subdev_get_locked_active_state(&sensor->subdev);
549 format = v4l2_subdev_state_get_format(state, 0);
550
551 switch (ctrl->id) {
552 case V4L2_CID_EXPOSURE:
553 /* clamp the exposure value to VMAX. */
554 vmax = format->height + sensor->vblank->cur.val;
555 ctrl->val = min_t(int, ctrl->val, vmax);
556 ret = imx415_write(sensor, IMX415_SHR0, vmax - ctrl->val);
557 break;
558
559 case V4L2_CID_ANALOGUE_GAIN:
560 /* analogue gain in 0.3 dB step size */
561 ret = imx415_write(sensor, IMX415_GAIN_PCG_0, ctrl->val);
562 break;
563
564 case V4L2_CID_HFLIP:
565 case V4L2_CID_VFLIP:
566 flip = (sensor->hflip->val << IMX415_HREVERSE_SHIFT) |
567 (sensor->vflip->val << IMX415_VREVERSE_SHIFT);
568 ret = imx415_write(sensor, IMX415_REVERSE, flip);
569 break;
570
571 case V4L2_CID_TEST_PATTERN:
572 ret = imx415_set_testpattern(sensor, ctrl->val);
573 break;
574
575 default:
576 ret = -EINVAL;
577 break;
578 }
579
580 pm_runtime_put(sensor->dev);
581
582 return ret;
583 }
584
585 static const struct v4l2_ctrl_ops imx415_ctrl_ops = {
586 .s_ctrl = imx415_s_ctrl,
587 };
588
imx415_ctrls_init(struct imx415 * sensor)589 static int imx415_ctrls_init(struct imx415 *sensor)
590 {
591 struct v4l2_fwnode_device_properties props;
592 struct v4l2_ctrl *ctrl;
593 u64 pixel_rate = supported_modes[sensor->cur_mode].pixel_rate;
594 u64 lane_rate = supported_modes[sensor->cur_mode].lane_rate;
595 u32 exposure_max = IMX415_PIXEL_ARRAY_HEIGHT +
596 IMX415_PIXEL_ARRAY_VBLANK - 8;
597 u32 hblank;
598 unsigned int i;
599 int ret;
600
601 ret = v4l2_fwnode_device_parse(sensor->dev, &props);
602 if (ret < 0)
603 return ret;
604
605 v4l2_ctrl_handler_init(&sensor->ctrls, 10);
606
607 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) {
608 if (lane_rate == link_freq_menu_items[i] * 2)
609 break;
610 }
611 if (i == ARRAY_SIZE(link_freq_menu_items)) {
612 return dev_err_probe(sensor->dev, -EINVAL,
613 "lane rate %llu not supported\n",
614 lane_rate);
615 }
616
617 ctrl = v4l2_ctrl_new_int_menu(&sensor->ctrls, &imx415_ctrl_ops,
618 V4L2_CID_LINK_FREQ,
619 ARRAY_SIZE(link_freq_menu_items) - 1, i,
620 link_freq_menu_items);
621
622 if (ctrl)
623 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
624
625 v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, V4L2_CID_EXPOSURE,
626 4, exposure_max, 1, exposure_max);
627
628 v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
629 V4L2_CID_ANALOGUE_GAIN, IMX415_AGAIN_MIN,
630 IMX415_AGAIN_MAX, IMX415_AGAIN_STEP,
631 IMX415_AGAIN_MIN);
632
633 hblank = supported_modes[sensor->cur_mode].hmax_pix -
634 IMX415_PIXEL_ARRAY_WIDTH;
635 ctrl = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
636 V4L2_CID_HBLANK, hblank, hblank, 1, hblank);
637 if (ctrl)
638 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
639
640 sensor->vblank = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
641 V4L2_CID_VBLANK,
642 IMX415_PIXEL_ARRAY_VBLANK,
643 IMX415_PIXEL_ARRAY_VBLANK, 1,
644 IMX415_PIXEL_ARRAY_VBLANK);
645 if (sensor->vblank)
646 sensor->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
647
648 /*
649 * The pixel rate used here is a virtual value and can be used for
650 * calculating the frame rate together with hblank. It may not
651 * necessarily be the physically correct pixel clock.
652 */
653 v4l2_ctrl_new_std(&sensor->ctrls, NULL, V4L2_CID_PIXEL_RATE, pixel_rate,
654 pixel_rate, 1, pixel_rate);
655
656 sensor->hflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
657 V4L2_CID_HFLIP, 0, 1, 1, 0);
658 sensor->vflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
659 V4L2_CID_VFLIP, 0, 1, 1, 0);
660
661 v4l2_ctrl_new_std_menu_items(&sensor->ctrls, &imx415_ctrl_ops,
662 V4L2_CID_TEST_PATTERN,
663 ARRAY_SIZE(imx415_test_pattern_menu) - 1,
664 0, 0, imx415_test_pattern_menu);
665
666 v4l2_ctrl_new_fwnode_properties(&sensor->ctrls, &imx415_ctrl_ops,
667 &props);
668
669 if (sensor->ctrls.error) {
670 dev_err_probe(sensor->dev, sensor->ctrls.error,
671 "failed to add controls\n");
672 v4l2_ctrl_handler_free(&sensor->ctrls);
673 return sensor->ctrls.error;
674 }
675 sensor->subdev.ctrl_handler = &sensor->ctrls;
676
677 return 0;
678 }
679
imx415_set_mode(struct imx415 * sensor,int mode)680 static int imx415_set_mode(struct imx415 *sensor, int mode)
681 {
682 const struct imx415_reg *reg;
683 unsigned int i;
684 int ret = 0;
685
686 if (mode >= ARRAY_SIZE(supported_modes)) {
687 dev_err(sensor->dev, "Mode %d not supported\n", mode);
688 return -EINVAL;
689 }
690
691 for (i = 0; i < supported_modes[mode].reg_list.num_of_regs; ++i) {
692 reg = &supported_modes[mode].reg_list.regs[i];
693 ret = imx415_write(sensor, reg->address, reg->val);
694 if (ret)
695 return ret;
696 }
697
698 for (i = 0; i < IMX415_NUM_CLK_PARAM_REGS; ++i) {
699 reg = &sensor->clk_params->regs[i];
700 ret = imx415_write(sensor, reg->address, reg->val);
701 if (ret)
702 return ret;
703 }
704
705 return 0;
706 }
707
imx415_setup(struct imx415 * sensor,struct v4l2_subdev_state * state)708 static int imx415_setup(struct imx415 *sensor, struct v4l2_subdev_state *state)
709 {
710 unsigned int i;
711 int ret;
712
713 for (i = 0; i < ARRAY_SIZE(imx415_init_table); ++i) {
714 ret = imx415_write(sensor, imx415_init_table[i].address,
715 imx415_init_table[i].val);
716 if (ret)
717 return ret;
718 }
719
720 return imx415_set_mode(sensor, sensor->cur_mode);
721 }
722
imx415_wakeup(struct imx415 * sensor)723 static int imx415_wakeup(struct imx415 *sensor)
724 {
725 int ret;
726
727 ret = imx415_write(sensor, IMX415_MODE, IMX415_MODE_OPERATING);
728 if (ret)
729 return ret;
730
731 /*
732 * According to the datasheet we have to wait at least 63 us after
733 * leaving standby mode. But this doesn't work even after 30 ms.
734 * So probably this should be 63 ms and therefore we wait for 80 ms.
735 */
736 msleep(80);
737
738 return 0;
739 }
740
imx415_stream_on(struct imx415 * sensor)741 static int imx415_stream_on(struct imx415 *sensor)
742 {
743 int ret;
744
745 ret = imx415_wakeup(sensor);
746 if (ret)
747 return ret;
748
749 return imx415_write(sensor, IMX415_XMSTA, IMX415_XMSTA_START);
750 }
751
imx415_stream_off(struct imx415 * sensor)752 static int imx415_stream_off(struct imx415 *sensor)
753 {
754 int ret;
755
756 ret = imx415_write(sensor, IMX415_XMSTA, IMX415_XMSTA_STOP);
757 if (ret)
758 return ret;
759
760 return imx415_write(sensor, IMX415_MODE, IMX415_MODE_STANDBY);
761 }
762
imx415_s_stream(struct v4l2_subdev * sd,int enable)763 static int imx415_s_stream(struct v4l2_subdev *sd, int enable)
764 {
765 struct imx415 *sensor = to_imx415(sd);
766 struct v4l2_subdev_state *state;
767 int ret;
768
769 state = v4l2_subdev_lock_and_get_active_state(sd);
770
771 if (!enable) {
772 ret = imx415_stream_off(sensor);
773
774 pm_runtime_mark_last_busy(sensor->dev);
775 pm_runtime_put_autosuspend(sensor->dev);
776
777 goto unlock;
778 }
779
780 ret = pm_runtime_resume_and_get(sensor->dev);
781 if (ret < 0)
782 goto unlock;
783
784 ret = imx415_setup(sensor, state);
785 if (ret)
786 goto err_pm;
787
788 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls);
789 if (ret < 0)
790 goto err_pm;
791
792 ret = imx415_stream_on(sensor);
793 if (ret)
794 goto err_pm;
795
796 ret = 0;
797
798 unlock:
799 v4l2_subdev_unlock_state(state);
800
801 return ret;
802
803 err_pm:
804 /*
805 * In case of error, turn the power off synchronously as the device
806 * likely has no other chance to recover.
807 */
808 pm_runtime_put_sync(sensor->dev);
809
810 goto unlock;
811 }
812
imx415_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_mbus_code_enum * code)813 static int imx415_enum_mbus_code(struct v4l2_subdev *sd,
814 struct v4l2_subdev_state *state,
815 struct v4l2_subdev_mbus_code_enum *code)
816 {
817 if (code->index != 0)
818 return -EINVAL;
819
820 code->code = MEDIA_BUS_FMT_SGBRG10_1X10;
821
822 return 0;
823 }
824
imx415_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_frame_size_enum * fse)825 static int imx415_enum_frame_size(struct v4l2_subdev *sd,
826 struct v4l2_subdev_state *state,
827 struct v4l2_subdev_frame_size_enum *fse)
828 {
829 const struct v4l2_mbus_framefmt *format;
830
831 format = v4l2_subdev_state_get_format(state, fse->pad);
832
833 if (fse->index > 0 || fse->code != format->code)
834 return -EINVAL;
835
836 fse->min_width = IMX415_PIXEL_ARRAY_WIDTH;
837 fse->max_width = fse->min_width;
838 fse->min_height = IMX415_PIXEL_ARRAY_HEIGHT;
839 fse->max_height = fse->min_height;
840 return 0;
841 }
842
imx415_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * fmt)843 static int imx415_set_format(struct v4l2_subdev *sd,
844 struct v4l2_subdev_state *state,
845 struct v4l2_subdev_format *fmt)
846 {
847 struct v4l2_mbus_framefmt *format;
848
849 format = v4l2_subdev_state_get_format(state, fmt->pad);
850
851 format->width = fmt->format.width;
852 format->height = fmt->format.height;
853 format->code = MEDIA_BUS_FMT_SGBRG10_1X10;
854 format->field = V4L2_FIELD_NONE;
855 format->colorspace = V4L2_COLORSPACE_RAW;
856 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
857 format->quantization = V4L2_QUANTIZATION_DEFAULT;
858 format->xfer_func = V4L2_XFER_FUNC_NONE;
859
860 fmt->format = *format;
861 return 0;
862 }
863
imx415_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)864 static int imx415_get_selection(struct v4l2_subdev *sd,
865 struct v4l2_subdev_state *sd_state,
866 struct v4l2_subdev_selection *sel)
867 {
868 switch (sel->target) {
869 case V4L2_SEL_TGT_CROP:
870 case V4L2_SEL_TGT_CROP_DEFAULT:
871 case V4L2_SEL_TGT_CROP_BOUNDS:
872 sel->r.top = IMX415_PIXEL_ARRAY_TOP;
873 sel->r.left = IMX415_PIXEL_ARRAY_LEFT;
874 sel->r.width = IMX415_PIXEL_ARRAY_WIDTH;
875 sel->r.height = IMX415_PIXEL_ARRAY_HEIGHT;
876
877 return 0;
878 }
879
880 return -EINVAL;
881 }
882
imx415_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)883 static int imx415_init_state(struct v4l2_subdev *sd,
884 struct v4l2_subdev_state *state)
885 {
886 struct v4l2_subdev_format format = {
887 .format = {
888 .width = IMX415_PIXEL_ARRAY_WIDTH,
889 .height = IMX415_PIXEL_ARRAY_HEIGHT,
890 },
891 };
892
893 imx415_set_format(sd, state, &format);
894
895 return 0;
896 }
897
898 static const struct v4l2_subdev_video_ops imx415_subdev_video_ops = {
899 .s_stream = imx415_s_stream,
900 };
901
902 static const struct v4l2_subdev_pad_ops imx415_subdev_pad_ops = {
903 .enum_mbus_code = imx415_enum_mbus_code,
904 .enum_frame_size = imx415_enum_frame_size,
905 .get_fmt = v4l2_subdev_get_fmt,
906 .set_fmt = imx415_set_format,
907 .get_selection = imx415_get_selection,
908 };
909
910 static const struct v4l2_subdev_ops imx415_subdev_ops = {
911 .video = &imx415_subdev_video_ops,
912 .pad = &imx415_subdev_pad_ops,
913 };
914
915 static const struct v4l2_subdev_internal_ops imx415_internal_ops = {
916 .init_state = imx415_init_state,
917 };
918
imx415_subdev_init(struct imx415 * sensor)919 static int imx415_subdev_init(struct imx415 *sensor)
920 {
921 struct i2c_client *client = to_i2c_client(sensor->dev);
922 int ret;
923
924 v4l2_i2c_subdev_init(&sensor->subdev, client, &imx415_subdev_ops);
925 sensor->subdev.internal_ops = &imx415_internal_ops;
926
927 ret = imx415_ctrls_init(sensor);
928 if (ret)
929 return ret;
930
931 sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
932 V4L2_SUBDEV_FL_HAS_EVENTS;
933 sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
934 sensor->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
935 ret = media_entity_pads_init(&sensor->subdev.entity, 1, &sensor->pad);
936 if (ret < 0) {
937 v4l2_ctrl_handler_free(&sensor->ctrls);
938 return ret;
939 }
940
941 sensor->subdev.state_lock = sensor->subdev.ctrl_handler->lock;
942 v4l2_subdev_init_finalize(&sensor->subdev);
943
944 return 0;
945 }
946
imx415_subdev_cleanup(struct imx415 * sensor)947 static void imx415_subdev_cleanup(struct imx415 *sensor)
948 {
949 media_entity_cleanup(&sensor->subdev.entity);
950 v4l2_ctrl_handler_free(&sensor->ctrls);
951 }
952
imx415_power_on(struct imx415 * sensor)953 static int imx415_power_on(struct imx415 *sensor)
954 {
955 int ret;
956
957 ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies),
958 sensor->supplies);
959 if (ret < 0)
960 return ret;
961
962 gpiod_set_value_cansleep(sensor->reset, 0);
963
964 udelay(1);
965
966 ret = clk_prepare_enable(sensor->clk);
967 if (ret < 0)
968 goto err_reset;
969
970 /*
971 * Data sheet states that 20 us are required before communication start,
972 * but this doesn't work in all cases. Use 100 us to be on the safe
973 * side.
974 */
975 usleep_range(100, 200);
976
977 return 0;
978
979 err_reset:
980 gpiod_set_value_cansleep(sensor->reset, 1);
981 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies);
982 return ret;
983 }
984
imx415_power_off(struct imx415 * sensor)985 static void imx415_power_off(struct imx415 *sensor)
986 {
987 clk_disable_unprepare(sensor->clk);
988 gpiod_set_value_cansleep(sensor->reset, 1);
989 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies);
990 }
991
imx415_identify_model(struct imx415 * sensor)992 static int imx415_identify_model(struct imx415 *sensor)
993 {
994 int model, ret;
995
996 /*
997 * While most registers can be read when the sensor is in standby, this
998 * is not the case of the sensor info register :-(
999 */
1000 ret = imx415_wakeup(sensor);
1001 if (ret)
1002 return dev_err_probe(sensor->dev, ret,
1003 "failed to get sensor out of standby\n");
1004
1005 ret = imx415_read(sensor, IMX415_SENSOR_INFO);
1006 if (ret < 0) {
1007 dev_err_probe(sensor->dev, ret,
1008 "failed to read sensor information\n");
1009 goto done;
1010 }
1011
1012 model = ret & IMX415_SENSOR_INFO_MASK;
1013
1014 switch (model) {
1015 case IMX415_CHIP_ID:
1016 dev_info(sensor->dev, "Detected IMX415 image sensor\n");
1017 break;
1018 default:
1019 ret = dev_err_probe(sensor->dev, -ENODEV,
1020 "invalid device model 0x%04x\n", model);
1021 goto done;
1022 }
1023
1024 ret = 0;
1025
1026 done:
1027 imx415_write(sensor, IMX415_MODE, IMX415_MODE_STANDBY);
1028 return ret;
1029 }
1030
imx415_check_inck(unsigned long inck,u64 link_frequency)1031 static int imx415_check_inck(unsigned long inck, u64 link_frequency)
1032 {
1033 unsigned int i;
1034
1035 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {
1036 if ((imx415_clk_params[i].lane_rate == link_frequency * 2) &&
1037 imx415_clk_params[i].inck == inck)
1038 break;
1039 }
1040
1041 if (i == ARRAY_SIZE(imx415_clk_params))
1042 return -EINVAL;
1043 else
1044 return 0;
1045 }
1046
imx415_parse_hw_config(struct imx415 * sensor)1047 static int imx415_parse_hw_config(struct imx415 *sensor)
1048 {
1049 struct v4l2_fwnode_endpoint bus_cfg = {
1050 .bus_type = V4L2_MBUS_CSI2_DPHY,
1051 };
1052 struct fwnode_handle *ep;
1053 u64 lane_rate;
1054 unsigned long inck;
1055 unsigned int i, j;
1056 int ret;
1057
1058 for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i)
1059 sensor->supplies[i].supply = imx415_supply_names[i];
1060
1061 ret = devm_regulator_bulk_get(sensor->dev, ARRAY_SIZE(sensor->supplies),
1062 sensor->supplies);
1063 if (ret)
1064 return dev_err_probe(sensor->dev, ret,
1065 "failed to get supplies\n");
1066
1067 sensor->reset = devm_gpiod_get_optional(sensor->dev, "reset",
1068 GPIOD_OUT_HIGH);
1069 if (IS_ERR(sensor->reset))
1070 return dev_err_probe(sensor->dev, PTR_ERR(sensor->reset),
1071 "failed to get reset GPIO\n");
1072
1073 sensor->clk = devm_clk_get(sensor->dev, "inck");
1074 if (IS_ERR(sensor->clk))
1075 return dev_err_probe(sensor->dev, PTR_ERR(sensor->clk),
1076 "failed to get clock\n");
1077
1078 ep = fwnode_graph_get_next_endpoint(dev_fwnode(sensor->dev), NULL);
1079 if (!ep)
1080 return -ENXIO;
1081
1082 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1083 fwnode_handle_put(ep);
1084 if (ret)
1085 return ret;
1086
1087 switch (bus_cfg.bus.mipi_csi2.num_data_lanes) {
1088 case 2:
1089 case 4:
1090 sensor->num_data_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
1091 break;
1092 default:
1093 ret = dev_err_probe(sensor->dev, -EINVAL,
1094 "invalid number of CSI2 data lanes %d\n",
1095 bus_cfg.bus.mipi_csi2.num_data_lanes);
1096 goto done_endpoint_free;
1097 }
1098
1099 if (!bus_cfg.nr_of_link_frequencies) {
1100 ret = dev_err_probe(sensor->dev, -EINVAL,
1101 "no link frequencies defined");
1102 goto done_endpoint_free;
1103 }
1104
1105 /*
1106 * Check if there exists a sensor mode defined for current INCK,
1107 * number of lanes and given lane rates.
1108 */
1109 inck = clk_get_rate(sensor->clk);
1110 for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) {
1111 if (imx415_check_inck(inck, bus_cfg.link_frequencies[i])) {
1112 dev_dbg(sensor->dev,
1113 "INCK %lu Hz not supported for this link freq",
1114 inck);
1115 continue;
1116 }
1117
1118 for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) {
1119 if (sensor->num_data_lanes != supported_modes[j].lanes)
1120 continue;
1121 if (bus_cfg.link_frequencies[i] * 2 !=
1122 supported_modes[j].lane_rate)
1123 continue;
1124 sensor->cur_mode = j;
1125 break;
1126 }
1127 if (j < ARRAY_SIZE(supported_modes))
1128 break;
1129 }
1130 if (i == bus_cfg.nr_of_link_frequencies) {
1131 ret = dev_err_probe(sensor->dev, -EINVAL,
1132 "no valid sensor mode defined\n");
1133 goto done_endpoint_free;
1134 }
1135
1136 lane_rate = supported_modes[sensor->cur_mode].lane_rate;
1137 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {
1138 if (lane_rate == imx415_clk_params[i].lane_rate &&
1139 inck == imx415_clk_params[i].inck) {
1140 sensor->clk_params = &imx415_clk_params[i];
1141 break;
1142 }
1143 }
1144 if (i == ARRAY_SIZE(imx415_clk_params)) {
1145 ret = dev_err_probe(sensor->dev, -EINVAL,
1146 "Mode %d not supported\n",
1147 sensor->cur_mode);
1148 goto done_endpoint_free;
1149 }
1150
1151 ret = 0;
1152 dev_dbg(sensor->dev, "clock: %lu Hz, lane_rate: %llu bps, lanes: %d\n",
1153 inck, lane_rate, sensor->num_data_lanes);
1154
1155 done_endpoint_free:
1156 v4l2_fwnode_endpoint_free(&bus_cfg);
1157
1158 return ret;
1159 }
1160
imx415_probe(struct i2c_client * client)1161 static int imx415_probe(struct i2c_client *client)
1162 {
1163 struct imx415 *sensor;
1164 int ret;
1165
1166 sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
1167 if (!sensor)
1168 return -ENOMEM;
1169
1170 sensor->dev = &client->dev;
1171
1172 ret = imx415_parse_hw_config(sensor);
1173 if (ret)
1174 return ret;
1175
1176 sensor->regmap = devm_regmap_init_i2c(client, &imx415_regmap_config);
1177 if (IS_ERR(sensor->regmap))
1178 return PTR_ERR(sensor->regmap);
1179
1180 /*
1181 * Enable power management. The driver supports runtime PM, but needs to
1182 * work when runtime PM is disabled in the kernel. To that end, power
1183 * the sensor on manually here, identify it, and fully initialize it.
1184 */
1185 ret = imx415_power_on(sensor);
1186 if (ret)
1187 return ret;
1188
1189 ret = imx415_identify_model(sensor);
1190 if (ret)
1191 goto err_power;
1192
1193 ret = imx415_subdev_init(sensor);
1194 if (ret)
1195 goto err_power;
1196
1197 /*
1198 * Enable runtime PM. As the device has been powered manually, mark it
1199 * as active, and increase the usage count without resuming the device.
1200 */
1201 pm_runtime_set_active(sensor->dev);
1202 pm_runtime_get_noresume(sensor->dev);
1203 pm_runtime_enable(sensor->dev);
1204
1205 ret = v4l2_async_register_subdev_sensor(&sensor->subdev);
1206 if (ret < 0)
1207 goto err_pm;
1208
1209 /*
1210 * Finally, enable autosuspend and decrease the usage count. The device
1211 * will get suspended after the autosuspend delay, turning the power
1212 * off.
1213 */
1214 pm_runtime_set_autosuspend_delay(sensor->dev, 1000);
1215 pm_runtime_use_autosuspend(sensor->dev);
1216 pm_runtime_put_autosuspend(sensor->dev);
1217
1218 return 0;
1219
1220 err_pm:
1221 pm_runtime_disable(sensor->dev);
1222 pm_runtime_put_noidle(sensor->dev);
1223 imx415_subdev_cleanup(sensor);
1224 err_power:
1225 imx415_power_off(sensor);
1226 return ret;
1227 }
1228
imx415_remove(struct i2c_client * client)1229 static void imx415_remove(struct i2c_client *client)
1230 {
1231 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1232 struct imx415 *sensor = to_imx415(subdev);
1233
1234 v4l2_async_unregister_subdev(subdev);
1235
1236 imx415_subdev_cleanup(sensor);
1237
1238 /*
1239 * Disable runtime PM. In case runtime PM is disabled in the kernel,
1240 * make sure to turn power off manually.
1241 */
1242 pm_runtime_disable(sensor->dev);
1243 if (!pm_runtime_status_suspended(sensor->dev))
1244 imx415_power_off(sensor);
1245 pm_runtime_set_suspended(sensor->dev);
1246 }
1247
imx415_runtime_resume(struct device * dev)1248 static int imx415_runtime_resume(struct device *dev)
1249 {
1250 struct i2c_client *client = to_i2c_client(dev);
1251 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1252 struct imx415 *sensor = to_imx415(subdev);
1253
1254 return imx415_power_on(sensor);
1255 }
1256
imx415_runtime_suspend(struct device * dev)1257 static int imx415_runtime_suspend(struct device *dev)
1258 {
1259 struct i2c_client *client = to_i2c_client(dev);
1260 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1261 struct imx415 *sensor = to_imx415(subdev);
1262
1263 imx415_power_off(sensor);
1264
1265 return 0;
1266 }
1267
1268 static DEFINE_RUNTIME_DEV_PM_OPS(imx415_pm_ops, imx415_runtime_suspend,
1269 imx415_runtime_resume, NULL);
1270
1271 static const struct of_device_id imx415_of_match[] = {
1272 { .compatible = "sony,imx415" },
1273 { /* sentinel */ }
1274 };
1275
1276 MODULE_DEVICE_TABLE(of, imx415_of_match);
1277
1278 static struct i2c_driver imx415_driver = {
1279 .probe = imx415_probe,
1280 .remove = imx415_remove,
1281 .driver = {
1282 .name = "imx415",
1283 .of_match_table = imx415_of_match,
1284 .pm = pm_ptr(&imx415_pm_ops),
1285 },
1286 };
1287
1288 module_i2c_driver(imx415_driver);
1289
1290 MODULE_DESCRIPTION("Sony IMX415 image sensor driver");
1291 MODULE_AUTHOR("Gerald Loacker <gerald.loacker@wolfvision.net>");
1292 MODULE_AUTHOR("Michael Riesch <michael.riesch@wolfvision.net>");
1293 MODULE_LICENSE("GPL");
1294