1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Allied Vision Technologies GmbH Alvium camera driver
4 *
5 * Copyright (C) 2023 Tommaso Merciai
6 * Copyright (C) 2023 Martin Hecht
7 * Copyright (C) 2023 Avnet EMG GmbH
8 */
9
10 #include <linux/i2c.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 #include <media/mipi-csi2.h>
16 #include <media/v4l2-async.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-event.h>
20 #include <media/v4l2-fwnode.h>
21 #include <media/v4l2-subdev.h>
22
23 #include "alvium-csi2.h"
24
25 static const struct v4l2_mbus_framefmt alvium_csi2_default_fmt = {
26 .code = MEDIA_BUS_FMT_UYVY8_1X16,
27 .width = 640,
28 .height = 480,
29 .colorspace = V4L2_COLORSPACE_SRGB,
30 .ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(V4L2_COLORSPACE_SRGB),
31 .quantization = V4L2_QUANTIZATION_FULL_RANGE,
32 .xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(V4L2_COLORSPACE_SRGB),
33 .field = V4L2_FIELD_NONE,
34 };
35
36 static const struct alvium_pixfmt alvium_csi2_fmts[] = {
37 {
38 /* UYVY8_2X8 */
39 .id = ALVIUM_FMT_UYVY8_2X8,
40 .code = MEDIA_BUS_FMT_UYVY8_2X8,
41 .colorspace = V4L2_COLORSPACE_SRGB,
42 .fmt_av_bit = ALVIUM_BIT_YUV422_8,
43 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
44 .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,
45 .bay_fmt_regval = -1,
46 .is_raw = 0,
47 }, {
48 /* UYVY8_1X16 */
49 .id = ALVIUM_FMT_UYVY8_1X16,
50 .code = MEDIA_BUS_FMT_UYVY8_1X16,
51 .colorspace = V4L2_COLORSPACE_SRGB,
52 .fmt_av_bit = ALVIUM_BIT_YUV422_8,
53 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
54 .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,
55 .bay_fmt_regval = -1,
56 .is_raw = 0,
57 }, {
58 /* YUYV8_1X16 */
59 .id = ALVIUM_FMT_YUYV8_1X16,
60 .code = MEDIA_BUS_FMT_YUYV8_1X16,
61 .colorspace = V4L2_COLORSPACE_SRGB,
62 .fmt_av_bit = ALVIUM_BIT_YUV422_8,
63 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
64 .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,
65 .bay_fmt_regval = -1,
66 .is_raw = 0,
67 }, {
68 /* YUYV8_2X8 */
69 .id = ALVIUM_FMT_YUYV8_2X8,
70 .code = MEDIA_BUS_FMT_YUYV8_2X8,
71 .colorspace = V4L2_COLORSPACE_SRGB,
72 .fmt_av_bit = ALVIUM_BIT_YUV422_8,
73 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
74 .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_8B,
75 .bay_fmt_regval = -1,
76 .is_raw = 0,
77 }, {
78 /* YUYV10_1X20 */
79 .id = ALVIUM_FMT_YUYV10_1X20,
80 .code = MEDIA_BUS_FMT_YUYV10_1X20,
81 .colorspace = V4L2_COLORSPACE_SRGB,
82 .fmt_av_bit = ALVIUM_BIT_YUV422_10,
83 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
84 .mipi_fmt_regval = MIPI_CSI2_DT_YUV422_10B,
85 .bay_fmt_regval = -1,
86 .is_raw = 0,
87 }, {
88 /* RGB888_1X24 */
89 .id = ALVIUM_FMT_RGB888_1X24,
90 .code = MEDIA_BUS_FMT_RGB888_1X24,
91 .colorspace = V4L2_COLORSPACE_SRGB,
92 .fmt_av_bit = ALVIUM_BIT_RGB888,
93 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
94 .mipi_fmt_regval = MIPI_CSI2_DT_RGB888,
95 .bay_fmt_regval = -1,
96 .is_raw = 0,
97 }, {
98 /* RBG888_1X24 */
99 .id = ALVIUM_FMT_RBG888_1X24,
100 .code = MEDIA_BUS_FMT_RBG888_1X24,
101 .colorspace = V4L2_COLORSPACE_SRGB,
102 .fmt_av_bit = ALVIUM_BIT_RGB888,
103 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
104 .mipi_fmt_regval = MIPI_CSI2_DT_RGB888,
105 .bay_fmt_regval = -1,
106 .is_raw = 0,
107 }, {
108 /* BGR888_1X24 */
109 .id = ALVIUM_FMT_BGR888_1X24,
110 .code = MEDIA_BUS_FMT_BGR888_1X24,
111 .colorspace = V4L2_COLORSPACE_SRGB,
112 .fmt_av_bit = ALVIUM_BIT_RGB888,
113 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
114 .mipi_fmt_regval = MIPI_CSI2_DT_RGB888,
115 .bay_fmt_regval = -1,
116 .is_raw = 0,
117 }, {
118 /* RGB888_3X8 */
119 .id = ALVIUM_FMT_RGB888_3X8,
120 .code = MEDIA_BUS_FMT_RGB888_3X8,
121 .colorspace = V4L2_COLORSPACE_SRGB,
122 .fmt_av_bit = ALVIUM_BIT_RGB888,
123 .bay_av_bit = ALVIUM_BIT_BAY_NONE,
124 .mipi_fmt_regval = MIPI_CSI2_DT_RGB888,
125 .bay_fmt_regval = -1,
126 .is_raw = 0,
127 }, {
128 /* Y8_1X8 */
129 .id = ALVIUM_FMT_Y8_1X8,
130 .code = MEDIA_BUS_FMT_Y8_1X8,
131 .colorspace = V4L2_COLORSPACE_RAW,
132 .fmt_av_bit = ALVIUM_BIT_RAW8,
133 .bay_av_bit = ALVIUM_BIT_BAY_MONO,
134 .mipi_fmt_regval = MIPI_CSI2_DT_RAW8,
135 .bay_fmt_regval = 0x00,
136 .is_raw = 1,
137 }, {
138 /* SGRBG8_1X8 */
139 .id = ALVIUM_FMT_SGRBG8_1X8,
140 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
141 .colorspace = V4L2_COLORSPACE_RAW,
142 .fmt_av_bit = ALVIUM_BIT_RAW8,
143 .bay_av_bit = ALVIUM_BIT_BAY_GR,
144 .mipi_fmt_regval = MIPI_CSI2_DT_RAW8,
145 .bay_fmt_regval = 0x01,
146 .is_raw = 1,
147 }, {
148 /* SRGGB8_1X8 */
149 .id = ALVIUM_FMT_SRGGB8_1X8,
150 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
151 .colorspace = V4L2_COLORSPACE_RAW,
152 .fmt_av_bit = ALVIUM_BIT_RAW8,
153 .bay_av_bit = ALVIUM_BIT_BAY_RG,
154 .mipi_fmt_regval = MIPI_CSI2_DT_RAW8,
155 .bay_fmt_regval = 0x02,
156 .is_raw = 1,
157 }, {
158 /* SGBRG8_1X8 */
159 .id = ALVIUM_FMT_SGBRG8_1X8,
160 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
161 .colorspace = V4L2_COLORSPACE_RAW,
162 .fmt_av_bit = ALVIUM_BIT_RAW8,
163 .bay_av_bit = ALVIUM_BIT_BAY_GB,
164 .mipi_fmt_regval = MIPI_CSI2_DT_RAW8,
165 .bay_fmt_regval = 0x03,
166 .is_raw = 1,
167 }, {
168 /* SBGGR8_1X8 */
169 .id = ALVIUM_FMT_SBGGR8_1X8,
170 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
171 .colorspace = V4L2_COLORSPACE_RAW,
172 .fmt_av_bit = ALVIUM_BIT_RAW8,
173 .bay_av_bit = ALVIUM_BIT_BAY_BG,
174 .mipi_fmt_regval = MIPI_CSI2_DT_RAW8,
175 .bay_fmt_regval = 0x04,
176 .is_raw = 1,
177 }, {
178 /* Y10_1X10 */
179 .id = ALVIUM_FMT_Y10_1X10,
180 .code = MEDIA_BUS_FMT_Y10_1X10,
181 .colorspace = V4L2_COLORSPACE_RAW,
182 .fmt_av_bit = ALVIUM_BIT_RAW10,
183 .bay_av_bit = ALVIUM_BIT_BAY_MONO,
184 .mipi_fmt_regval = MIPI_CSI2_DT_RAW10,
185 .bay_fmt_regval = 0x00,
186 .is_raw = 1,
187 }, {
188 /* SGRBG10_1X10 */
189 .id = ALVIUM_FMT_SGRBG10_1X10,
190 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
191 .colorspace = V4L2_COLORSPACE_RAW,
192 .fmt_av_bit = ALVIUM_BIT_RAW10,
193 .bay_av_bit = ALVIUM_BIT_BAY_GR,
194 .mipi_fmt_regval = MIPI_CSI2_DT_RAW10,
195 .bay_fmt_regval = 0x01,
196 .is_raw = 1,
197 }, {
198 /* SRGGB10_1X10 */
199 .id = ALVIUM_FMT_SRGGB10_1X10,
200 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
201 .colorspace = V4L2_COLORSPACE_RAW,
202 .fmt_av_bit = ALVIUM_BIT_RAW10,
203 .bay_av_bit = ALVIUM_BIT_BAY_RG,
204 .mipi_fmt_regval = MIPI_CSI2_DT_RAW10,
205 .bay_fmt_regval = 0x02,
206 .is_raw = 1,
207 }, {
208 /* SGBRG10_1X10 */
209 .id = ALVIUM_FMT_SGBRG10_1X10,
210 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
211 .colorspace = V4L2_COLORSPACE_RAW,
212 .fmt_av_bit = ALVIUM_BIT_RAW10,
213 .bay_av_bit = ALVIUM_BIT_BAY_GB,
214 .mipi_fmt_regval = MIPI_CSI2_DT_RAW10,
215 .bay_fmt_regval = 0x03,
216 .is_raw = 1,
217 }, {
218 /* SBGGR10_1X10 */
219 .id = ALVIUM_FMT_SBGGR10_1X10,
220 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
221 .colorspace = V4L2_COLORSPACE_RAW,
222 .fmt_av_bit = ALVIUM_BIT_RAW10,
223 .bay_av_bit = ALVIUM_BIT_BAY_BG,
224 .mipi_fmt_regval = MIPI_CSI2_DT_RAW10,
225 .bay_fmt_regval = 0x04,
226 .is_raw = 1,
227 }, {
228 /* Y12_1X12 */
229 .id = ALVIUM_FMT_Y12_1X12,
230 .code = MEDIA_BUS_FMT_Y12_1X12,
231 .colorspace = V4L2_COLORSPACE_RAW,
232 .fmt_av_bit = ALVIUM_BIT_RAW12,
233 .bay_av_bit = ALVIUM_BIT_BAY_MONO,
234 .mipi_fmt_regval = MIPI_CSI2_DT_RAW12,
235 .bay_fmt_regval = 0x00,
236 .is_raw = 1,
237 }, {
238 /* SGRBG12_1X12 */
239 .id = ALVIUM_FMT_SGRBG12_1X12,
240 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
241 .colorspace = V4L2_COLORSPACE_RAW,
242 .fmt_av_bit = ALVIUM_BIT_RAW12,
243 .bay_av_bit = ALVIUM_BIT_BAY_GR,
244 .mipi_fmt_regval = MIPI_CSI2_DT_RAW12,
245 .bay_fmt_regval = 0x01,
246 .is_raw = 1,
247 }, {
248 /* SRGGB12_1X12 */
249 .id = ALVIUM_FMT_SRGGB12_1X12,
250 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
251 .colorspace = V4L2_COLORSPACE_RAW,
252 .fmt_av_bit = ALVIUM_BIT_RAW12,
253 .bay_av_bit = ALVIUM_BIT_BAY_RG,
254 .mipi_fmt_regval = MIPI_CSI2_DT_RAW12,
255 .bay_fmt_regval = 0x02,
256 .is_raw = 1,
257 }, {
258 /* SGBRG12_1X12 */
259 .id = ALVIUM_FMT_SGBRG12_1X12,
260 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
261 .colorspace = V4L2_COLORSPACE_RAW,
262 .fmt_av_bit = ALVIUM_BIT_RAW12,
263 .bay_av_bit = ALVIUM_BIT_BAY_GB,
264 .mipi_fmt_regval = MIPI_CSI2_DT_RAW12,
265 .bay_fmt_regval = 0x03,
266 .is_raw = 1,
267 }, {
268 /* SBGGR12_1X12 */
269 .id = ALVIUM_FMT_SBGGR12_1X12,
270 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
271 .colorspace = V4L2_COLORSPACE_RAW,
272 .fmt_av_bit = ALVIUM_BIT_RAW12,
273 .bay_av_bit = ALVIUM_BIT_BAY_BG,
274 .mipi_fmt_regval = MIPI_CSI2_DT_RAW12,
275 .bay_fmt_regval = 0x04,
276 .is_raw = 1,
277 }, {
278 /* SBGGR14_1X14 */
279 .id = ALVIUM_FMT_SBGGR14_1X14,
280 .code = MEDIA_BUS_FMT_SBGGR14_1X14,
281 .colorspace = V4L2_COLORSPACE_RAW,
282 .fmt_av_bit = ALVIUM_BIT_RAW14,
283 .bay_av_bit = ALVIUM_BIT_BAY_GR,
284 .mipi_fmt_regval = MIPI_CSI2_DT_RAW14,
285 .bay_fmt_regval = 0x01,
286 .is_raw = 1,
287 }, {
288 /* SGBRG14_1X14 */
289 .id = ALVIUM_FMT_SGBRG14_1X14,
290 .code = MEDIA_BUS_FMT_SGBRG14_1X14,
291 .colorspace = V4L2_COLORSPACE_RAW,
292 .fmt_av_bit = ALVIUM_BIT_RAW14,
293 .bay_av_bit = ALVIUM_BIT_BAY_RG,
294 .mipi_fmt_regval = MIPI_CSI2_DT_RAW14,
295 .bay_fmt_regval = 0x02,
296 .is_raw = 1,
297 }, {
298 /* SRGGB14_1X14 */
299 .id = ALVIUM_FMT_SRGGB14_1X14,
300 .code = MEDIA_BUS_FMT_SRGGB14_1X14,
301 .colorspace = V4L2_COLORSPACE_RAW,
302 .fmt_av_bit = ALVIUM_BIT_RAW14,
303 .bay_av_bit = ALVIUM_BIT_BAY_GB,
304 .mipi_fmt_regval = MIPI_CSI2_DT_RAW14,
305 .bay_fmt_regval = 0x03,
306 .is_raw = 1,
307 }, {
308 /* SGRBG14_1X14 */
309 .id = ALVIUM_FMT_SGRBG14_1X14,
310 .code = MEDIA_BUS_FMT_SGRBG14_1X14,
311 .colorspace = V4L2_COLORSPACE_RAW,
312 .fmt_av_bit = ALVIUM_BIT_RAW14,
313 .bay_av_bit = ALVIUM_BIT_BAY_BG,
314 .mipi_fmt_regval = MIPI_CSI2_DT_RAW14,
315 .bay_fmt_regval = 0x04,
316 .is_raw = 1,
317 },
318 { /* sentinel */ }
319 };
320
alvium_read(struct alvium_dev * alvium,u32 reg,u64 * val,int * err)321 static int alvium_read(struct alvium_dev *alvium, u32 reg, u64 *val, int *err)
322 {
323 if (reg & REG_BCRM_V4L2) {
324 reg &= ~REG_BCRM_V4L2;
325 reg += alvium->bcrm_addr;
326 }
327
328 return cci_read(alvium->regmap, reg, val, err);
329 }
330
alvium_write(struct alvium_dev * alvium,u32 reg,u64 val,int * err)331 static int alvium_write(struct alvium_dev *alvium, u32 reg, u64 val, int *err)
332 {
333 if (reg & REG_BCRM_V4L2) {
334 reg &= ~REG_BCRM_V4L2;
335 reg += alvium->bcrm_addr;
336 }
337
338 return cci_write(alvium->regmap, reg, val, err);
339 }
340
alvium_write_hshake(struct alvium_dev * alvium,u32 reg,u64 val)341 static int alvium_write_hshake(struct alvium_dev *alvium, u32 reg, u64 val)
342 {
343 struct device *dev = &alvium->i2c_client->dev;
344 u64 hshake_bit;
345 int ret = 0;
346
347 /* reset handshake bit and write alvium reg */
348 alvium_write(alvium, REG_BCRM_WRITE_HANDSHAKE_RW, 0, &ret);
349 alvium_write(alvium, reg, val, &ret);
350 if (ret) {
351 dev_err(dev, "Fail to write reg\n");
352 return ret;
353 }
354
355 /* poll handshake bit since bit0 = 1 */
356 read_poll_timeout(alvium_read, hshake_bit,
357 ((hshake_bit & BCRM_HANDSHAKE_W_DONE_EN_BIT) == 1),
358 15000, 45000, true,
359 alvium, REG_BCRM_WRITE_HANDSHAKE_RW,
360 &hshake_bit, &ret);
361 if (ret) {
362 dev_err(dev, "poll bit[0] = 1, hshake reg fail\n");
363 return ret;
364 }
365
366 /* reset handshake bit, write 0 to bit0 */
367 alvium_write(alvium, REG_BCRM_WRITE_HANDSHAKE_RW, 0, &ret);
368 if (ret) {
369 dev_err(dev, "Fail to reset hshake reg\n");
370 return ret;
371 }
372
373 /* poll handshake bit since bit0 = 0 */
374 read_poll_timeout(alvium_read, hshake_bit,
375 ((hshake_bit & BCRM_HANDSHAKE_W_DONE_EN_BIT) == 0),
376 15000, 45000, true,
377 alvium, REG_BCRM_WRITE_HANDSHAKE_RW,
378 &hshake_bit, &ret);
379 if (ret) {
380 dev_err(dev, "poll bit[0] = 0, hshake reg fail\n");
381 return ret;
382 }
383
384 return 0;
385 }
386
alvium_get_bcrm_vers(struct alvium_dev * alvium)387 static int alvium_get_bcrm_vers(struct alvium_dev *alvium)
388 {
389 struct device *dev = &alvium->i2c_client->dev;
390 u64 min, maj;
391 int ret = 0;
392
393 ret = alvium_read(alvium, REG_BCRM_MINOR_VERSION_R, &min, &ret);
394 ret = alvium_read(alvium, REG_BCRM_MAJOR_VERSION_R, &maj, &ret);
395 if (ret)
396 return ret;
397
398 dev_info(dev, "bcrm version: %llu.%llu\n", min, maj);
399
400 return 0;
401 }
402
alvium_get_fw_version(struct alvium_dev * alvium)403 static int alvium_get_fw_version(struct alvium_dev *alvium)
404 {
405 struct device *dev = &alvium->i2c_client->dev;
406 u64 spec, maj, min, pat;
407 int ret = 0;
408
409 ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_SPEC_VERSION_R,
410 &spec, &ret);
411 ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_MAJOR_VERSION_R,
412 &maj, &ret);
413 ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_MINOR_VERSION_R,
414 &min, &ret);
415 ret = alvium_read(alvium, REG_BCRM_DEVICE_FW_PATCH_VERSION_R,
416 &pat, &ret);
417 if (ret)
418 return ret;
419
420 dev_info(dev, "fw version: %llu.%llu.%llu.%llu\n", spec, maj, min, pat);
421
422 return 0;
423 }
424
alvium_get_bcrm_addr(struct alvium_dev * alvium)425 static int alvium_get_bcrm_addr(struct alvium_dev *alvium)
426 {
427 u64 val;
428 int ret;
429
430 ret = alvium_read(alvium, REG_BCRM_REG_ADDR_R, &val, NULL);
431 if (ret)
432 return ret;
433
434 alvium->bcrm_addr = val;
435
436 return 0;
437 }
438
alvium_is_alive(struct alvium_dev * alvium)439 static int alvium_is_alive(struct alvium_dev *alvium)
440 {
441 u64 bcrm, hbeat;
442 int ret = 0;
443
444 alvium_read(alvium, REG_BCRM_MINOR_VERSION_R, &bcrm, &ret);
445 alvium_read(alvium, REG_BCRM_HEARTBEAT_RW, &hbeat, &ret);
446 if (ret)
447 return ret;
448
449 return hbeat;
450 }
451
alvium_print_avail_mipi_fmt(struct alvium_dev * alvium)452 static void alvium_print_avail_mipi_fmt(struct alvium_dev *alvium)
453 {
454 struct device *dev = &alvium->i2c_client->dev;
455
456 dev_dbg(dev, "avail mipi_fmt yuv420_8_leg: %u\n",
457 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_LEG]);
458 dev_dbg(dev, "avail mipi_fmt yuv420_8: %u\n",
459 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8]);
460 dev_dbg(dev, "avail mipi_fmt yuv420_10: %u\n",
461 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10]);
462 dev_dbg(dev, "avail mipi_fmt yuv420_8_csps: %u\n",
463 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_CSPS]);
464 dev_dbg(dev, "avail mipi_fmt yuv420_10_csps: %u\n",
465 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10_CSPS]);
466 dev_dbg(dev, "avail mipi_fmt yuv422_8: %u\n",
467 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_8]);
468 dev_dbg(dev, "avail mipi_fmt yuv422_10: %u\n",
469 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_10]);
470 dev_dbg(dev, "avail mipi_fmt rgb888: %u\n",
471 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB888]);
472 dev_dbg(dev, "avail mipi_fmt rgb666: %u\n",
473 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB666]);
474 dev_dbg(dev, "avail mipi_fmt rgb565: %u\n",
475 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB565]);
476 dev_dbg(dev, "avail mipi_fmt rgb555: %u\n",
477 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB555]);
478 dev_dbg(dev, "avail mipi_fmt rgb444: %u\n",
479 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB444]);
480 dev_dbg(dev, "avail mipi_fmt raw6: %u\n",
481 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW6]);
482 dev_dbg(dev, "avail mipi_fmt raw7: %u\n",
483 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW7]);
484 dev_dbg(dev, "avail mipi_fmt raw8: %u\n",
485 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW8]);
486 dev_dbg(dev, "avail mipi_fmt raw10: %u\n",
487 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW10]);
488 dev_dbg(dev, "avail mipi_fmt raw12: %u\n",
489 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW12]);
490 dev_dbg(dev, "avail mipi_fmt raw14: %u\n",
491 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW14]);
492 dev_dbg(dev, "avail mipi_fmt jpeg: %u\n",
493 alvium->is_mipi_fmt_avail[ALVIUM_BIT_JPEG]);
494 }
495
alvium_print_avail_feat(struct alvium_dev * alvium)496 static void alvium_print_avail_feat(struct alvium_dev *alvium)
497 {
498 struct device *dev = &alvium->i2c_client->dev;
499
500 dev_dbg(dev, "feature rev_x: %u\n", alvium->avail_ft.rev_x);
501 dev_dbg(dev, "feature rev_y: %u\n", alvium->avail_ft.rev_y);
502 dev_dbg(dev, "feature int_autop: %u\n", alvium->avail_ft.int_autop);
503 dev_dbg(dev, "feature black_lvl: %u\n", alvium->avail_ft.black_lvl);
504 dev_dbg(dev, "feature gain: %u\n", alvium->avail_ft.gain);
505 dev_dbg(dev, "feature gamma: %u\n", alvium->avail_ft.gamma);
506 dev_dbg(dev, "feature contrast: %u\n", alvium->avail_ft.contrast);
507 dev_dbg(dev, "feature sat: %u\n", alvium->avail_ft.sat);
508 dev_dbg(dev, "feature hue: %u\n", alvium->avail_ft.hue);
509 dev_dbg(dev, "feature whiteb: %u\n", alvium->avail_ft.whiteb);
510 dev_dbg(dev, "feature sharp: %u\n", alvium->avail_ft.sharp);
511 dev_dbg(dev, "feature auto_exp: %u\n", alvium->avail_ft.auto_exp);
512 dev_dbg(dev, "feature auto_gain: %u\n", alvium->avail_ft.auto_gain);
513 dev_dbg(dev, "feature auto_whiteb: %u\n", alvium->avail_ft.auto_whiteb);
514 dev_dbg(dev, "feature dev_temp: %u\n", alvium->avail_ft.dev_temp);
515 dev_dbg(dev, "feature acq_abort: %u\n", alvium->avail_ft.acq_abort);
516 dev_dbg(dev, "feature acq_fr: %u\n", alvium->avail_ft.acq_fr);
517 dev_dbg(dev, "feature fr_trigger: %u\n", alvium->avail_ft.fr_trigger);
518 dev_dbg(dev, "feature exp_acq_line: %u\n",
519 alvium->avail_ft.exp_acq_line);
520 }
521
alvium_print_avail_bayer(struct alvium_dev * alvium)522 static void alvium_print_avail_bayer(struct alvium_dev *alvium)
523 {
524 struct device *dev = &alvium->i2c_client->dev;
525
526 dev_dbg(dev, "avail bayer mono: %u\n",
527 alvium->is_bay_avail[ALVIUM_BIT_BAY_MONO]);
528 dev_dbg(dev, "avail bayer gr: %u\n",
529 alvium->is_bay_avail[ALVIUM_BIT_BAY_GR]);
530 dev_dbg(dev, "avail bayer rg: %u\n",
531 alvium->is_bay_avail[ALVIUM_BIT_BAY_RG]);
532 dev_dbg(dev, "avail bayer gb: %u\n",
533 alvium->is_bay_avail[ALVIUM_BIT_BAY_GB]);
534 dev_dbg(dev, "avail bayer bg: %u\n",
535 alvium->is_bay_avail[ALVIUM_BIT_BAY_BG]);
536 }
537
alvium_get_feat_inq(struct alvium_dev * alvium)538 static int alvium_get_feat_inq(struct alvium_dev *alvium)
539 {
540 struct alvium_avail_feat *f;
541 u64 val;
542 int ret;
543
544 ret = alvium_read(alvium, REG_BCRM_FEATURE_INQUIRY_R, &val, NULL);
545 if (ret)
546 return ret;
547
548 f = (struct alvium_avail_feat *)&val;
549 alvium->avail_ft = *f;
550 alvium_print_avail_feat(alvium);
551
552 return 0;
553 }
554
alvium_get_host_supp_csi_lanes(struct alvium_dev * alvium)555 static int alvium_get_host_supp_csi_lanes(struct alvium_dev *alvium)
556 {
557 u64 val;
558 int ret;
559
560 ret = alvium_read(alvium, REG_BCRM_CSI2_LANE_COUNT_RW, &val, NULL);
561 if (ret)
562 return ret;
563
564 alvium->h_sup_csi_lanes = val;
565
566 return 0;
567 }
568
alvium_set_csi_lanes(struct alvium_dev * alvium)569 static int alvium_set_csi_lanes(struct alvium_dev *alvium)
570 {
571 struct device *dev = &alvium->i2c_client->dev;
572 u64 num_lanes;
573 int ret;
574
575 num_lanes = alvium->ep.bus.mipi_csi2.num_data_lanes;
576
577 if (num_lanes > alvium->h_sup_csi_lanes)
578 return -EINVAL;
579
580 ret = alvium_write_hshake(alvium, REG_BCRM_CSI2_LANE_COUNT_RW,
581 num_lanes);
582 if (ret) {
583 dev_err(dev, "Fail to set csi lanes reg\n");
584 return ret;
585 }
586
587 return 0;
588 }
589
alvium_set_lp2hs_delay(struct alvium_dev * alvium)590 static int alvium_set_lp2hs_delay(struct alvium_dev *alvium)
591 {
592 struct device *dev = &alvium->i2c_client->dev;
593 int ret = 0;
594
595 /*
596 * The purpose of this reg is force a DPhy reset
597 * for the period described by the millisecond on
598 * the reg, before it starts streaming.
599 *
600 * To be clear, with that value bigger than 0 the
601 * Alvium forces a dphy-reset on all lanes for that period.
602 * That means all lanes go up into low power state.
603 *
604 */
605 alvium_write(alvium, REG_BCRM_LP2HS_DELAY_RW,
606 ALVIUM_LP2HS_DELAY_MS, &ret);
607 if (ret) {
608 dev_err(dev, "Fail to set lp2hs delay reg\n");
609 return ret;
610 }
611
612 return 0;
613 }
614
alvium_get_csi_clk_params(struct alvium_dev * alvium)615 static int alvium_get_csi_clk_params(struct alvium_dev *alvium)
616 {
617 u64 min_csi_clk, max_csi_clk;
618 int ret = 0;
619
620 alvium_read(alvium, REG_BCRM_CSI2_CLOCK_MIN_R, &min_csi_clk, &ret);
621 alvium_read(alvium, REG_BCRM_CSI2_CLOCK_MAX_R, &max_csi_clk, &ret);
622 if (ret)
623 return ret;
624
625 alvium->min_csi_clk = min_csi_clk;
626 alvium->max_csi_clk = max_csi_clk;
627
628 return 0;
629 }
630
alvium_set_csi_clk(struct alvium_dev * alvium)631 static int alvium_set_csi_clk(struct alvium_dev *alvium)
632 {
633 struct device *dev = &alvium->i2c_client->dev;
634 u64 csi_clk;
635 int ret;
636
637 csi_clk = clamp(alvium->ep.link_frequencies[0],
638 (u64)alvium->min_csi_clk, (u64)alvium->max_csi_clk);
639
640 if (alvium->ep.link_frequencies[0] != (u64)csi_clk) {
641 dev_warn(dev,
642 "requested csi clock (%llu MHz) out of range [%u, %u] Adjusted to %llu\n",
643 alvium->ep.link_frequencies[0],
644 alvium->min_csi_clk, alvium->max_csi_clk, csi_clk);
645 }
646
647 ret = alvium_write_hshake(alvium, REG_BCRM_CSI2_CLOCK_RW, csi_clk);
648 if (ret) {
649 dev_err(dev, "Fail to set csi clock reg\n");
650 return ret;
651 }
652
653 alvium->link_freq = csi_clk;
654
655 return 0;
656 }
657
alvium_get_img_width_params(struct alvium_dev * alvium)658 static int alvium_get_img_width_params(struct alvium_dev *alvium)
659 {
660 u64 imgw, imgw_min, imgw_max, imgw_inc;
661 int ret = 0;
662
663 alvium_read(alvium, REG_BCRM_IMG_WIDTH_RW, &imgw, &ret);
664 alvium_read(alvium, REG_BCRM_IMG_WIDTH_MIN_R, &imgw_min, &ret);
665 alvium_read(alvium, REG_BCRM_IMG_WIDTH_MAX_R, &imgw_max, &ret);
666 alvium_read(alvium, REG_BCRM_IMG_WIDTH_INC_R, &imgw_inc, &ret);
667 if (ret)
668 return ret;
669
670 alvium->dft_img_width = imgw;
671 alvium->img_min_width = imgw_min;
672 alvium->img_max_width = imgw_max;
673 alvium->img_inc_width = imgw_inc;
674
675 return 0;
676 }
677
alvium_get_img_height_params(struct alvium_dev * alvium)678 static int alvium_get_img_height_params(struct alvium_dev *alvium)
679 {
680 u64 imgh, imgh_min, imgh_max, imgh_inc;
681 int ret = 0;
682
683 alvium_read(alvium, REG_BCRM_IMG_HEIGHT_RW, &imgh, &ret);
684 alvium_read(alvium, REG_BCRM_IMG_HEIGHT_MIN_R, &imgh_min, &ret);
685 alvium_read(alvium, REG_BCRM_IMG_HEIGHT_MAX_R, &imgh_max, &ret);
686 alvium_read(alvium, REG_BCRM_IMG_HEIGHT_INC_R, &imgh_inc, &ret);
687 if (ret)
688 return ret;
689
690 alvium->dft_img_height = imgh;
691 alvium->img_min_height = imgh_min;
692 alvium->img_max_height = imgh_max;
693 alvium->img_inc_height = imgh_inc;
694
695 return 0;
696 }
697
alvium_set_img_width(struct alvium_dev * alvium,u32 width)698 static int alvium_set_img_width(struct alvium_dev *alvium, u32 width)
699 {
700 struct device *dev = &alvium->i2c_client->dev;
701 int ret;
702
703 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_WIDTH_RW, width);
704 if (ret) {
705 dev_err(dev, "Fail to set img width\n");
706 return ret;
707 }
708
709 return 0;
710 }
711
alvium_set_img_height(struct alvium_dev * alvium,u32 height)712 static int alvium_set_img_height(struct alvium_dev *alvium, u32 height)
713 {
714 struct device *dev = &alvium->i2c_client->dev;
715 int ret;
716
717 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_HEIGHT_RW, height);
718 if (ret) {
719 dev_err(dev, "Fail to set img height\n");
720 return ret;
721 }
722
723 return 0;
724 }
725
alvium_set_img_offx(struct alvium_dev * alvium,u32 offx)726 static int alvium_set_img_offx(struct alvium_dev *alvium, u32 offx)
727 {
728 struct device *dev = &alvium->i2c_client->dev;
729 int ret;
730
731 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_OFFSET_X_RW, offx);
732 if (ret) {
733 dev_err(dev, "Fail to set img offx\n");
734 return ret;
735 }
736
737 return 0;
738 }
739
alvium_set_img_offy(struct alvium_dev * alvium,u32 offy)740 static int alvium_set_img_offy(struct alvium_dev *alvium, u32 offy)
741 {
742 struct device *dev = &alvium->i2c_client->dev;
743 int ret;
744
745 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_OFFSET_Y_RW, offy);
746 if (ret) {
747 dev_err(dev, "Fail to set img offy\n");
748 return ret;
749 }
750
751 return 0;
752 }
753
alvium_get_offx_params(struct alvium_dev * alvium)754 static int alvium_get_offx_params(struct alvium_dev *alvium)
755 {
756 u64 min_offx, max_offx, inc_offx;
757 int ret = 0;
758
759 alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_MIN_R, &min_offx, &ret);
760 alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_MAX_R, &max_offx, &ret);
761 alvium_read(alvium, REG_BCRM_IMG_OFFSET_X_INC_R, &inc_offx, &ret);
762 if (ret)
763 return ret;
764
765 alvium->min_offx = min_offx;
766 alvium->max_offx = max_offx;
767 alvium->inc_offx = inc_offx;
768
769 return 0;
770 }
771
alvium_get_offy_params(struct alvium_dev * alvium)772 static int alvium_get_offy_params(struct alvium_dev *alvium)
773 {
774 u64 min_offy, max_offy, inc_offy;
775 int ret = 0;
776
777 alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_MIN_R, &min_offy, &ret);
778 alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_MAX_R, &max_offy, &ret);
779 alvium_read(alvium, REG_BCRM_IMG_OFFSET_Y_INC_R, &inc_offy, &ret);
780 if (ret)
781 return ret;
782
783 alvium->min_offy = min_offy;
784 alvium->max_offy = max_offy;
785 alvium->inc_offy = inc_offy;
786
787 return 0;
788 }
789
alvium_get_gain_params(struct alvium_dev * alvium)790 static int alvium_get_gain_params(struct alvium_dev *alvium)
791 {
792 u64 dft_gain, min_gain, max_gain, inc_gain;
793 int ret = 0;
794
795 alvium_read(alvium, REG_BCRM_GAIN_RW, &dft_gain, &ret);
796 alvium_read(alvium, REG_BCRM_GAIN_MIN_R, &min_gain, &ret);
797 alvium_read(alvium, REG_BCRM_GAIN_MAX_R, &max_gain, &ret);
798 alvium_read(alvium, REG_BCRM_GAIN_INC_R, &inc_gain, &ret);
799 if (ret)
800 return ret;
801
802 alvium->dft_gain = dft_gain;
803 alvium->min_gain = min_gain;
804 alvium->max_gain = max_gain;
805 alvium->inc_gain = inc_gain;
806
807 return 0;
808 }
809
alvium_get_exposure_params(struct alvium_dev * alvium)810 static int alvium_get_exposure_params(struct alvium_dev *alvium)
811 {
812 u64 dft_exp, min_exp, max_exp, inc_exp;
813 int ret = 0;
814
815 alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_RW, &dft_exp, &ret);
816 alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_MIN_R, &min_exp, &ret);
817 alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_MAX_R, &max_exp, &ret);
818 alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_INC_R, &inc_exp, &ret);
819 if (ret)
820 return ret;
821
822 alvium->dft_exp = dft_exp;
823 alvium->min_exp = min_exp;
824 alvium->max_exp = max_exp;
825 alvium->inc_exp = inc_exp;
826
827 return 0;
828 }
829
alvium_get_red_balance_ratio_params(struct alvium_dev * alvium)830 static int alvium_get_red_balance_ratio_params(struct alvium_dev *alvium)
831 {
832 u64 dft_rb, min_rb, max_rb, inc_rb;
833 int ret = 0;
834
835 alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_RW, &dft_rb, &ret);
836 alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_MIN_R, &min_rb, &ret);
837 alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_MAX_R, &max_rb, &ret);
838 alvium_read(alvium, REG_BCRM_RED_BALANCE_RATIO_INC_R, &inc_rb, &ret);
839 if (ret)
840 return ret;
841
842 alvium->dft_rbalance = dft_rb;
843 alvium->min_rbalance = min_rb;
844 alvium->max_rbalance = max_rb;
845 alvium->inc_rbalance = inc_rb;
846
847 return 0;
848 }
849
alvium_get_blue_balance_ratio_params(struct alvium_dev * alvium)850 static int alvium_get_blue_balance_ratio_params(struct alvium_dev *alvium)
851 {
852 u64 dft_bb, min_bb, max_bb, inc_bb;
853 int ret = 0;
854
855 alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_RW, &dft_bb, &ret);
856 alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_MIN_R, &min_bb, &ret);
857 alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_MAX_R, &max_bb, &ret);
858 alvium_read(alvium, REG_BCRM_BLUE_BALANCE_RATIO_INC_R, &inc_bb, &ret);
859 if (ret)
860 return ret;
861
862 alvium->dft_bbalance = dft_bb;
863 alvium->min_bbalance = min_bb;
864 alvium->max_bbalance = max_bb;
865 alvium->inc_bbalance = inc_bb;
866
867 return 0;
868 }
869
alvium_get_hue_params(struct alvium_dev * alvium)870 static int alvium_get_hue_params(struct alvium_dev *alvium)
871 {
872 u64 dft_hue, min_hue, max_hue, inc_hue;
873 int ret = 0;
874
875 alvium_read(alvium, REG_BCRM_HUE_RW, &dft_hue, &ret);
876 alvium_read(alvium, REG_BCRM_HUE_MIN_R, &min_hue, &ret);
877 alvium_read(alvium, REG_BCRM_HUE_MAX_R, &max_hue, &ret);
878 alvium_read(alvium, REG_BCRM_HUE_INC_R, &inc_hue, &ret);
879 if (ret)
880 return ret;
881
882 alvium->dft_hue = (s32)dft_hue;
883 alvium->min_hue = (s32)min_hue;
884 alvium->max_hue = (s32)max_hue;
885 alvium->inc_hue = (s32)inc_hue;
886
887 return 0;
888 }
889
alvium_get_black_lvl_params(struct alvium_dev * alvium)890 static int alvium_get_black_lvl_params(struct alvium_dev *alvium)
891 {
892 u64 dft_blvl, min_blvl, max_blvl, inc_blvl;
893 int ret = 0;
894
895 alvium_read(alvium, REG_BCRM_BLACK_LEVEL_RW, &dft_blvl, &ret);
896 alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MIN_R, &min_blvl, &ret);
897 alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MAX_R, &max_blvl, &ret);
898 alvium_read(alvium, REG_BCRM_BLACK_LEVEL_INC_R, &inc_blvl, &ret);
899 if (ret)
900 return ret;
901
902 alvium->dft_black_lvl = (s32)dft_blvl;
903 alvium->min_black_lvl = (s32)min_blvl;
904 alvium->max_black_lvl = (s32)max_blvl;
905 alvium->inc_black_lvl = (s32)inc_blvl;
906
907 return 0;
908 }
909
alvium_get_gamma_params(struct alvium_dev * alvium)910 static int alvium_get_gamma_params(struct alvium_dev *alvium)
911 {
912 u64 dft_g, min_g, max_g, inc_g;
913 int ret = 0;
914
915 alvium_read(alvium, REG_BCRM_GAMMA_RW, &dft_g, &ret);
916 alvium_read(alvium, REG_BCRM_GAMMA_MIN_R, &min_g, &ret);
917 alvium_read(alvium, REG_BCRM_GAMMA_MAX_R, &max_g, &ret);
918 alvium_read(alvium, REG_BCRM_GAMMA_INC_R, &inc_g, &ret);
919 if (ret)
920 return ret;
921
922 alvium->dft_gamma = dft_g;
923 alvium->min_gamma = min_g;
924 alvium->max_gamma = max_g;
925 alvium->inc_gamma = inc_g;
926
927 return 0;
928 }
929
alvium_get_sharpness_params(struct alvium_dev * alvium)930 static int alvium_get_sharpness_params(struct alvium_dev *alvium)
931 {
932 u64 dft_sh, min_sh, max_sh, inc_sh;
933 int ret = 0;
934
935 alvium_read(alvium, REG_BCRM_SHARPNESS_RW, &dft_sh, &ret);
936 alvium_read(alvium, REG_BCRM_SHARPNESS_MIN_R, &min_sh, &ret);
937 alvium_read(alvium, REG_BCRM_BLACK_LEVEL_MAX_R, &max_sh, &ret);
938 alvium_read(alvium, REG_BCRM_SHARPNESS_INC_R, &inc_sh, &ret);
939 if (ret)
940 return ret;
941
942 alvium->dft_sharp = (s32)dft_sh;
943 alvium->min_sharp = (s32)min_sh;
944 alvium->max_sharp = (s32)max_sh;
945 alvium->inc_sharp = (s32)inc_sh;
946
947 return 0;
948 }
949
alvium_get_contrast_params(struct alvium_dev * alvium)950 static int alvium_get_contrast_params(struct alvium_dev *alvium)
951 {
952 u64 dft_c, min_c, max_c, inc_c;
953 int ret = 0;
954
955 alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_RW, &dft_c, &ret);
956 alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_MIN_R, &min_c, &ret);
957 alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_MAX_R, &max_c, &ret);
958 alvium_read(alvium, REG_BCRM_CONTRAST_VALUE_INC_R, &inc_c, &ret);
959 if (ret)
960 return ret;
961
962 alvium->dft_contrast = dft_c;
963 alvium->min_contrast = min_c;
964 alvium->max_contrast = max_c;
965 alvium->inc_contrast = inc_c;
966
967 return 0;
968 }
969
alvium_get_saturation_params(struct alvium_dev * alvium)970 static int alvium_get_saturation_params(struct alvium_dev *alvium)
971 {
972 u64 dft_sat, min_sat, max_sat, inc_sat;
973 int ret = 0;
974
975 alvium_read(alvium, REG_BCRM_SATURATION_RW, &dft_sat, &ret);
976 alvium_read(alvium, REG_BCRM_SATURATION_MIN_R, &min_sat, &ret);
977 alvium_read(alvium, REG_BCRM_SATURATION_MAX_R, &max_sat, &ret);
978 alvium_read(alvium, REG_BCRM_SATURATION_INC_R, &inc_sat, &ret);
979 if (ret)
980 return ret;
981
982 alvium->dft_sat = dft_sat;
983 alvium->min_sat = min_sat;
984 alvium->max_sat = max_sat;
985 alvium->inc_sat = inc_sat;
986
987 return 0;
988 }
989
alvium_set_bcm_mode(struct alvium_dev * alvium)990 static int alvium_set_bcm_mode(struct alvium_dev *alvium)
991 {
992 int ret = 0;
993
994 alvium_write(alvium, REG_GENCP_CHANGEMODE_W, ALVIUM_BCM_MODE, &ret);
995 alvium->bcrm_mode = ALVIUM_BCM_MODE;
996
997 return ret;
998 }
999
alvium_get_mode(struct alvium_dev * alvium)1000 static int alvium_get_mode(struct alvium_dev *alvium)
1001 {
1002 u64 bcrm_mode;
1003 int ret;
1004
1005 ret = alvium_read(alvium, REG_GENCP_CURRENTMODE_R, &bcrm_mode, NULL);
1006 if (ret)
1007 return ret;
1008
1009 switch (bcrm_mode) {
1010 case ALVIUM_BCM_MODE:
1011 alvium->bcrm_mode = ALVIUM_BCM_MODE;
1012 break;
1013 case ALVIUM_GENCP_MODE:
1014 alvium->bcrm_mode = ALVIUM_GENCP_MODE;
1015 break;
1016 }
1017
1018 return 0;
1019 }
1020
alvium_get_avail_mipi_data_format(struct alvium_dev * alvium)1021 static int alvium_get_avail_mipi_data_format(struct alvium_dev *alvium)
1022 {
1023 struct alvium_avail_mipi_fmt *avail_fmt;
1024 u64 val;
1025 int ret;
1026
1027 ret = alvium_read(alvium, REG_BCRM_IMG_AVAILABLE_MIPI_DATA_FORMATS_R,
1028 &val, NULL);
1029 if (ret)
1030 return ret;
1031
1032 avail_fmt = (struct alvium_avail_mipi_fmt *)&val;
1033
1034 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_LEG] =
1035 avail_fmt->yuv420_8_leg;
1036 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8] =
1037 avail_fmt->yuv420_8;
1038 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10] =
1039 avail_fmt->yuv420_10;
1040 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_8_CSPS] =
1041 avail_fmt->yuv420_8_csps;
1042 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV420_10_CSPS] =
1043 avail_fmt->yuv420_10_csps;
1044 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_8] =
1045 avail_fmt->yuv422_8;
1046 alvium->is_mipi_fmt_avail[ALVIUM_BIT_YUV422_10] =
1047 avail_fmt->yuv422_10;
1048 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB888] =
1049 avail_fmt->rgb888;
1050 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB666] =
1051 avail_fmt->rgb666;
1052 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB565] =
1053 avail_fmt->rgb565;
1054 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB555] =
1055 avail_fmt->rgb555;
1056 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RGB444] =
1057 avail_fmt->rgb444;
1058 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW6] =
1059 avail_fmt->raw6;
1060 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW7] =
1061 avail_fmt->raw7;
1062 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW8] =
1063 avail_fmt->raw8;
1064 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW10] =
1065 avail_fmt->raw10;
1066 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW12] =
1067 avail_fmt->raw12;
1068 alvium->is_mipi_fmt_avail[ALVIUM_BIT_RAW14] =
1069 avail_fmt->raw14;
1070 alvium->is_mipi_fmt_avail[ALVIUM_BIT_JPEG] =
1071 avail_fmt->jpeg;
1072
1073 alvium_print_avail_mipi_fmt(alvium);
1074
1075 return 0;
1076 }
1077
alvium_setup_mipi_fmt(struct alvium_dev * alvium)1078 static int alvium_setup_mipi_fmt(struct alvium_dev *alvium)
1079 {
1080 unsigned int avail_fmt_cnt = 0;
1081 unsigned int fmt = 0;
1082 size_t sz = 0;
1083
1084 /* calculate fmt array size */
1085 for (fmt = 0; fmt < ALVIUM_NUM_SUPP_MIPI_DATA_FMT; fmt++) {
1086 if (!alvium->is_mipi_fmt_avail[alvium_csi2_fmts[fmt].fmt_av_bit])
1087 continue;
1088
1089 if (!alvium_csi2_fmts[fmt].is_raw ||
1090 alvium->is_bay_avail[alvium_csi2_fmts[fmt].bay_av_bit])
1091 sz++;
1092 }
1093
1094 /* init alvium_csi2_fmt array */
1095 alvium->alvium_csi2_fmt_n = sz;
1096 alvium->alvium_csi2_fmt =
1097 kmalloc_array(sz, sizeof(struct alvium_pixfmt), GFP_KERNEL);
1098 if (!alvium->alvium_csi2_fmt)
1099 return -ENOMEM;
1100
1101 /* Create the alvium_csi2 fmt array from formats available */
1102 for (fmt = 0; fmt < ALVIUM_NUM_SUPP_MIPI_DATA_FMT; fmt++) {
1103 if (!alvium->is_mipi_fmt_avail[alvium_csi2_fmts[fmt].fmt_av_bit])
1104 continue;
1105
1106 if (!alvium_csi2_fmts[fmt].is_raw ||
1107 alvium->is_bay_avail[alvium_csi2_fmts[fmt].bay_av_bit]) {
1108 alvium->alvium_csi2_fmt[avail_fmt_cnt] =
1109 alvium_csi2_fmts[fmt];
1110 avail_fmt_cnt++;
1111 }
1112 }
1113
1114 return 0;
1115 }
1116
alvium_set_mipi_fmt(struct alvium_dev * alvium,const struct alvium_pixfmt * pixfmt)1117 static int alvium_set_mipi_fmt(struct alvium_dev *alvium,
1118 const struct alvium_pixfmt *pixfmt)
1119 {
1120 struct device *dev = &alvium->i2c_client->dev;
1121 int ret;
1122
1123 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_MIPI_DATA_FORMAT_RW,
1124 pixfmt->mipi_fmt_regval);
1125 if (ret) {
1126 dev_err(dev, "Fail to set mipi fmt\n");
1127 return ret;
1128 }
1129
1130 return 0;
1131 }
1132
alvium_get_avail_bayer(struct alvium_dev * alvium)1133 static int alvium_get_avail_bayer(struct alvium_dev *alvium)
1134 {
1135 struct alvium_avail_bayer *avail_bay;
1136 u64 val;
1137 int ret;
1138
1139 ret = alvium_read(alvium, REG_BCRM_IMG_BAYER_PATTERN_INQUIRY_R,
1140 &val, NULL);
1141 if (ret)
1142 return ret;
1143
1144 avail_bay = (struct alvium_avail_bayer *)&val;
1145
1146 alvium->is_bay_avail[ALVIUM_BIT_BAY_MONO] = avail_bay->mono;
1147 alvium->is_bay_avail[ALVIUM_BIT_BAY_GR] = avail_bay->gr;
1148 alvium->is_bay_avail[ALVIUM_BIT_BAY_RG] = avail_bay->rg;
1149 alvium->is_bay_avail[ALVIUM_BIT_BAY_GB] = avail_bay->gb;
1150 alvium->is_bay_avail[ALVIUM_BIT_BAY_BG] = avail_bay->bg;
1151
1152 alvium_print_avail_bayer(alvium);
1153
1154 return 0;
1155 }
1156
alvium_set_bayer_pattern(struct alvium_dev * alvium,const struct alvium_pixfmt * pixfmt)1157 static int alvium_set_bayer_pattern(struct alvium_dev *alvium,
1158 const struct alvium_pixfmt *pixfmt)
1159 {
1160 struct device *dev = &alvium->i2c_client->dev;
1161 int ret;
1162
1163 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_BAYER_PATTERN_RW,
1164 pixfmt->bay_fmt_regval);
1165 if (ret) {
1166 dev_err(dev, "Fail to set bayer pattern\n");
1167 return ret;
1168 }
1169
1170 return 0;
1171 }
1172
alvium_get_frame_interval(struct alvium_dev * alvium)1173 static int alvium_get_frame_interval(struct alvium_dev *alvium)
1174 {
1175 u64 dft_fr, min_fr, max_fr;
1176 int ret = 0;
1177
1178 alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_RW,
1179 &dft_fr, &ret);
1180 alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_MIN_R,
1181 &min_fr, &ret);
1182 alvium_read(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_MAX_R,
1183 &max_fr, &ret);
1184 if (ret)
1185 return ret;
1186
1187 alvium->dft_fr = dft_fr;
1188 alvium->min_fr = min_fr;
1189 alvium->max_fr = max_fr;
1190
1191 return 0;
1192 }
1193
alvium_set_frame_rate(struct alvium_dev * alvium)1194 static int alvium_set_frame_rate(struct alvium_dev *alvium)
1195 {
1196 struct device *dev = &alvium->i2c_client->dev;
1197 int ret;
1198
1199 ret = alvium_write_hshake(alvium, REG_BCRM_ACQUISITION_FRAME_RATE_RW,
1200 alvium->fr);
1201 if (ret) {
1202 dev_err(dev, "Fail to set frame rate lanes reg\n");
1203 return ret;
1204 }
1205
1206 dev_dbg(dev, "set frame rate: %llu us\n", alvium->fr);
1207
1208 return 0;
1209 }
1210
alvium_set_stream_mipi(struct alvium_dev * alvium,bool on)1211 static int alvium_set_stream_mipi(struct alvium_dev *alvium, bool on)
1212 {
1213 struct device *dev = &alvium->i2c_client->dev;
1214 int ret;
1215
1216 ret = alvium_write_hshake(alvium, on ? REG_BCRM_ACQUISITION_START_RW :
1217 REG_BCRM_ACQUISITION_STOP_RW, 0x01);
1218 if (ret) {
1219 dev_err(dev, "Fail set_stream_mipi\n");
1220 return ret;
1221 }
1222
1223 return 0;
1224 }
1225
alvium_get_gain(struct alvium_dev * alvium)1226 static int alvium_get_gain(struct alvium_dev *alvium)
1227 {
1228 u64 gain;
1229 int ret;
1230
1231 /* The unit is millibel (1 mB = 0.01 dB) */
1232 ret = alvium_read(alvium, REG_BCRM_GAIN_RW, &gain, NULL);
1233 if (ret)
1234 return ret;
1235
1236 return gain;
1237 }
1238
alvium_set_ctrl_gain(struct alvium_dev * alvium,int gain)1239 static int alvium_set_ctrl_gain(struct alvium_dev *alvium, int gain)
1240 {
1241 struct device *dev = &alvium->i2c_client->dev;
1242 int ret;
1243
1244 /* The unit is millibel (1 mB = 0.01 dB) */
1245 ret = alvium_write_hshake(alvium, REG_BCRM_GAIN_RW, (u64)gain);
1246 if (ret) {
1247 dev_err(dev, "Fail to set gain value reg\n");
1248 return ret;
1249 }
1250
1251 return 0;
1252 }
1253
alvium_set_ctrl_auto_gain(struct alvium_dev * alvium,bool on)1254 static int alvium_set_ctrl_auto_gain(struct alvium_dev *alvium, bool on)
1255 {
1256 struct device *dev = &alvium->i2c_client->dev;
1257 int ret;
1258
1259 ret = alvium_write_hshake(alvium, REG_BCRM_GAIN_AUTO_RW,
1260 on ? 0x02 : 0x00);
1261 if (ret) {
1262 dev_err(dev, "Fail to set autogain reg\n");
1263 return ret;
1264 }
1265
1266 return 0;
1267 }
1268
alvium_get_exposure(struct alvium_dev * alvium)1269 static int alvium_get_exposure(struct alvium_dev *alvium)
1270 {
1271 u64 exp;
1272 int ret;
1273
1274 /* Exposure time in ns */
1275 ret = alvium_read(alvium, REG_BCRM_EXPOSURE_TIME_RW, &exp, NULL);
1276 if (ret)
1277 return ret;
1278
1279 return exp;
1280 }
1281
alvium_set_ctrl_auto_exposure(struct alvium_dev * alvium,bool on)1282 static int alvium_set_ctrl_auto_exposure(struct alvium_dev *alvium, bool on)
1283 {
1284 struct device *dev = &alvium->i2c_client->dev;
1285 int ret;
1286
1287 ret = alvium_write_hshake(alvium, REG_BCRM_WHITE_BALANCE_AUTO_RW,
1288 on ? 0x02 : 0x00);
1289 if (ret) {
1290 dev_err(dev, "Fail to set autoexposure reg\n");
1291 return ret;
1292 }
1293
1294 return 0;
1295 }
1296
alvium_set_ctrl_exposure(struct alvium_dev * alvium,int exposure_ns)1297 static int alvium_set_ctrl_exposure(struct alvium_dev *alvium, int exposure_ns)
1298 {
1299 struct device *dev = &alvium->i2c_client->dev;
1300 int ret;
1301
1302 ret = alvium_write_hshake(alvium, REG_BCRM_EXPOSURE_TIME_RW,
1303 (u64)exposure_ns);
1304 if (ret) {
1305 dev_err(dev, "Fail to set exposure value reg\n");
1306 return ret;
1307 }
1308
1309 return 0;
1310 }
1311
alvium_set_ctrl_blue_balance_ratio(struct alvium_dev * alvium,int blue)1312 static int alvium_set_ctrl_blue_balance_ratio(struct alvium_dev *alvium,
1313 int blue)
1314 {
1315 struct device *dev = &alvium->i2c_client->dev;
1316 int ret;
1317
1318 ret = alvium_write_hshake(alvium, REG_BCRM_BLUE_BALANCE_RATIO_RW,
1319 (u64)blue);
1320 if (ret) {
1321 dev_err(dev, "Fail to set blue ratio value reg\n");
1322 return ret;
1323 }
1324
1325 return 0;
1326 }
1327
alvium_set_ctrl_red_balance_ratio(struct alvium_dev * alvium,int red)1328 static int alvium_set_ctrl_red_balance_ratio(struct alvium_dev *alvium, int red)
1329 {
1330 struct device *dev = &alvium->i2c_client->dev;
1331 int ret;
1332
1333 ret = alvium_write_hshake(alvium, REG_BCRM_RED_BALANCE_RATIO_RW,
1334 (u64)red);
1335 if (ret) {
1336 dev_err(dev, "Fail to set red ratio value reg\n");
1337 return ret;
1338 }
1339
1340 return 0;
1341 }
1342
alvium_set_ctrl_awb(struct alvium_dev * alvium,bool on)1343 static int alvium_set_ctrl_awb(struct alvium_dev *alvium, bool on)
1344 {
1345 struct device *dev = &alvium->i2c_client->dev;
1346 int ret;
1347
1348 ret = alvium_write_hshake(alvium, REG_BCRM_WHITE_BALANCE_AUTO_RW,
1349 on ? 0x02 : 0x00);
1350 if (ret) {
1351 dev_err(dev, "Fail to set awb reg\n");
1352 return ret;
1353 }
1354
1355 return 0;
1356 }
1357
alvium_set_ctrl_hue(struct alvium_dev * alvium,int val)1358 static int alvium_set_ctrl_hue(struct alvium_dev *alvium, int val)
1359 {
1360 struct device *dev = &alvium->i2c_client->dev;
1361 int ret;
1362
1363 ret = alvium_write_hshake(alvium, REG_BCRM_HUE_RW, (u64)val);
1364 if (ret) {
1365 dev_err(dev, "Fail to set hue value reg\n");
1366 return ret;
1367 }
1368
1369 return 0;
1370 }
1371
alvium_set_ctrl_contrast(struct alvium_dev * alvium,int val)1372 static int alvium_set_ctrl_contrast(struct alvium_dev *alvium, int val)
1373 {
1374 struct device *dev = &alvium->i2c_client->dev;
1375 int ret;
1376
1377 ret = alvium_write_hshake(alvium, REG_BCRM_CONTRAST_VALUE_RW, (u64)val);
1378 if (ret) {
1379 dev_err(dev, "Fail to set contrast value reg\n");
1380 return ret;
1381 }
1382
1383 return 0;
1384 }
1385
alvium_set_ctrl_saturation(struct alvium_dev * alvium,int val)1386 static int alvium_set_ctrl_saturation(struct alvium_dev *alvium, int val)
1387 {
1388 struct device *dev = &alvium->i2c_client->dev;
1389 int ret;
1390
1391 ret = alvium_write_hshake(alvium, REG_BCRM_SATURATION_RW, (u64)val);
1392 if (ret) {
1393 dev_err(dev, "Fail to set contrast value reg\n");
1394 return ret;
1395 }
1396
1397 return 0;
1398 }
1399
alvium_set_ctrl_gamma(struct alvium_dev * alvium,int val)1400 static int alvium_set_ctrl_gamma(struct alvium_dev *alvium, int val)
1401 {
1402 struct device *dev = &alvium->i2c_client->dev;
1403 int ret;
1404
1405 ret = alvium_write_hshake(alvium, REG_BCRM_GAMMA_RW, (u64)val);
1406 if (ret) {
1407 dev_err(dev, "Fail to set gamma value reg\n");
1408 return ret;
1409 }
1410
1411 return 0;
1412 }
1413
alvium_set_ctrl_sharpness(struct alvium_dev * alvium,int val)1414 static int alvium_set_ctrl_sharpness(struct alvium_dev *alvium, int val)
1415 {
1416 struct device *dev = &alvium->i2c_client->dev;
1417 int ret;
1418
1419 ret = alvium_write_hshake(alvium, REG_BCRM_SHARPNESS_RW, (u64)val);
1420 if (ret) {
1421 dev_err(dev, "Fail to set sharpness value reg\n");
1422 return ret;
1423 }
1424
1425 return 0;
1426 }
1427
alvium_set_ctrl_hflip(struct alvium_dev * alvium,int val)1428 static int alvium_set_ctrl_hflip(struct alvium_dev *alvium, int val)
1429 {
1430 struct device *dev = &alvium->i2c_client->dev;
1431 int ret;
1432
1433 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_REVERSE_X_RW, (u64)val);
1434 if (ret) {
1435 dev_err(dev, "Fail to set reverse_x value reg\n");
1436 return ret;
1437 }
1438
1439 return 0;
1440 }
1441
alvium_set_ctrl_vflip(struct alvium_dev * alvium,int val)1442 static int alvium_set_ctrl_vflip(struct alvium_dev *alvium, int val)
1443 {
1444 struct device *dev = &alvium->i2c_client->dev;
1445 int ret;
1446
1447 ret = alvium_write_hshake(alvium, REG_BCRM_IMG_REVERSE_Y_RW, (u64)val);
1448 if (ret) {
1449 dev_err(dev, "Fail to set reverse_y value reg\n");
1450 return ret;
1451 }
1452
1453 return 0;
1454 }
1455
alvium_get_hw_features_params(struct alvium_dev * alvium)1456 static int alvium_get_hw_features_params(struct alvium_dev *alvium)
1457 {
1458 struct device *dev = &alvium->i2c_client->dev;
1459 int ret;
1460
1461 ret = alvium_get_csi_clk_params(alvium);
1462 if (ret) {
1463 dev_err(dev, "Fail to read min/max csi clock regs\n");
1464 return ret;
1465 }
1466
1467 ret = alvium_get_img_width_params(alvium);
1468 if (ret) {
1469 dev_err(dev, "Fail to read img width regs\n");
1470 return ret;
1471 }
1472
1473 ret = alvium_get_img_height_params(alvium);
1474 if (ret) {
1475 dev_err(dev, "Fail to read img heigth regs\n");
1476 return ret;
1477 }
1478
1479 ret = alvium_get_offx_params(alvium);
1480 if (ret) {
1481 dev_err(dev, "Fail to read offx regs\n");
1482 return ret;
1483 }
1484
1485 ret = alvium_get_offy_params(alvium);
1486 if (ret) {
1487 dev_err(dev, "Fail to read offy regs\n");
1488 return ret;
1489 }
1490
1491 ret = alvium_get_gain_params(alvium);
1492 if (ret) {
1493 dev_err(dev, "Fail to read gain regs\n");
1494 return ret;
1495 }
1496
1497 ret = alvium_get_exposure_params(alvium);
1498 if (ret) {
1499 dev_err(dev, "Fail to read min/max exp regs\n");
1500 return ret;
1501 }
1502
1503 ret = alvium_get_red_balance_ratio_params(alvium);
1504 if (ret) {
1505 dev_err(dev, "Fail to read red balance ratio regs\n");
1506 return ret;
1507 }
1508
1509 ret = alvium_get_blue_balance_ratio_params(alvium);
1510 if (ret) {
1511 dev_err(dev, "Fail to read blue balance ratio regs\n");
1512 return ret;
1513 }
1514
1515 ret = alvium_get_hue_params(alvium);
1516 if (ret) {
1517 dev_err(dev, "Fail to read hue regs\n");
1518 return ret;
1519 }
1520
1521 ret = alvium_get_contrast_params(alvium);
1522 if (ret) {
1523 dev_err(dev, "Fail to read contrast regs\n");
1524 return ret;
1525 }
1526
1527 ret = alvium_get_saturation_params(alvium);
1528 if (ret) {
1529 dev_err(dev, "Fail to read saturation regs\n");
1530 return ret;
1531 }
1532
1533 ret = alvium_get_black_lvl_params(alvium);
1534 if (ret) {
1535 dev_err(dev, "Fail to read black lvl regs\n");
1536 return ret;
1537 }
1538
1539 ret = alvium_get_gamma_params(alvium);
1540 if (ret) {
1541 dev_err(dev, "Fail to read gamma regs\n");
1542 return ret;
1543 }
1544
1545 ret = alvium_get_sharpness_params(alvium);
1546 if (ret) {
1547 dev_err(dev, "Fail to read sharpness regs\n");
1548 return ret;
1549 }
1550
1551 return 0;
1552 }
1553
alvium_get_hw_info(struct alvium_dev * alvium)1554 static int alvium_get_hw_info(struct alvium_dev *alvium)
1555 {
1556 struct device *dev = &alvium->i2c_client->dev;
1557 int ret;
1558
1559 ret = alvium_get_bcrm_vers(alvium);
1560 if (ret) {
1561 dev_err(dev, "Fail to read bcrm version reg\n");
1562 return ret;
1563 }
1564
1565 ret = alvium_get_bcrm_addr(alvium);
1566 if (ret) {
1567 dev_err(dev, "Fail to bcrm address reg\n");
1568 return ret;
1569 }
1570
1571 ret = alvium_get_fw_version(alvium);
1572 if (ret) {
1573 dev_err(dev, "Fail to read fw version reg\n");
1574 return ret;
1575 }
1576
1577 ret = alvium_get_host_supp_csi_lanes(alvium);
1578 if (ret) {
1579 dev_err(dev, "Fail to read host supported csi lanes reg\n");
1580 return ret;
1581 }
1582
1583 ret = alvium_get_feat_inq(alvium);
1584 if (ret) {
1585 dev_err(dev, "Fail to read bcrm feature inquiry reg\n");
1586 return ret;
1587 }
1588
1589 ret = alvium_get_hw_features_params(alvium);
1590 if (ret) {
1591 dev_err(dev, "Fail to read features params regs\n");
1592 return ret;
1593 }
1594
1595 ret = alvium_get_avail_mipi_data_format(alvium);
1596 if (ret) {
1597 dev_err(dev, "Fail to read available mipi data formats reg\n");
1598 return ret;
1599 }
1600
1601 ret = alvium_get_avail_bayer(alvium);
1602 if (ret) {
1603 dev_err(dev, "Fail to read available Bayer patterns reg\n");
1604 return ret;
1605 }
1606
1607 ret = alvium_get_mode(alvium);
1608 if (ret) {
1609 dev_err(dev, "Fail to get current mode reg\n");
1610 return ret;
1611 }
1612
1613 return 0;
1614 }
1615
alvium_hw_init(struct alvium_dev * alvium)1616 static int alvium_hw_init(struct alvium_dev *alvium)
1617 {
1618 struct device *dev = &alvium->i2c_client->dev;
1619 int ret;
1620
1621 /* Set Alvium BCM mode*/
1622 ret = alvium_set_bcm_mode(alvium);
1623 if (ret) {
1624 dev_err(dev, "Fail to set BCM mode\n");
1625 return ret;
1626 }
1627
1628 ret = alvium_set_csi_lanes(alvium);
1629 if (ret) {
1630 dev_err(dev, "Fail to set csi lanes\n");
1631 return ret;
1632 }
1633
1634 ret = alvium_set_csi_clk(alvium);
1635 if (ret) {
1636 dev_err(dev, "Fail to set csi clk\n");
1637 return ret;
1638 }
1639
1640 ret = alvium_set_lp2hs_delay(alvium);
1641 if (ret) {
1642 dev_err(dev, "Fail to set lp2hs reg\n");
1643 return ret;
1644 }
1645
1646 return 0;
1647 }
1648
1649 /* --------------- Subdev Operations --------------- */
1650
alvium_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)1651 static int alvium_g_frame_interval(struct v4l2_subdev *sd,
1652 struct v4l2_subdev_state *sd_state,
1653 struct v4l2_subdev_frame_interval *fi)
1654 {
1655 struct alvium_dev *alvium = sd_to_alvium(sd);
1656
1657 /*
1658 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1659 * subdev active state API.
1660 */
1661 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1662 return -EINVAL;
1663
1664 fi->interval = alvium->frame_interval;
1665
1666 return 0;
1667 }
1668
alvium_set_frame_interval(struct alvium_dev * alvium,struct v4l2_subdev_frame_interval * fi)1669 static int alvium_set_frame_interval(struct alvium_dev *alvium,
1670 struct v4l2_subdev_frame_interval *fi)
1671 {
1672 struct device *dev = &alvium->i2c_client->dev;
1673 u64 req_fr, min_fr, max_fr;
1674 int ret;
1675
1676 if (fi->interval.denominator == 0)
1677 return -EINVAL;
1678
1679 ret = alvium_get_frame_interval(alvium);
1680 if (ret) {
1681 dev_err(dev, "Fail to get frame interval\n");
1682 return ret;
1683 }
1684
1685 min_fr = alvium->min_fr;
1686 max_fr = alvium->max_fr;
1687
1688 dev_dbg(dev, "fi->interval.numerator = %d\n",
1689 fi->interval.numerator);
1690 dev_dbg(dev, "fi->interval.denominator = %d\n",
1691 fi->interval.denominator);
1692
1693 req_fr = (u64)((fi->interval.denominator * USEC_PER_SEC) /
1694 fi->interval.numerator);
1695
1696 if (req_fr >= max_fr && req_fr <= min_fr)
1697 req_fr = alvium->dft_fr;
1698
1699 alvium->fr = req_fr;
1700 alvium->frame_interval.numerator = fi->interval.numerator;
1701 alvium->frame_interval.denominator = fi->interval.denominator;
1702
1703 return 0;
1704 }
1705
alvium_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_interval * fi)1706 static int alvium_s_frame_interval(struct v4l2_subdev *sd,
1707 struct v4l2_subdev_state *sd_state,
1708 struct v4l2_subdev_frame_interval *fi)
1709 {
1710 struct alvium_dev *alvium = sd_to_alvium(sd);
1711 int ret;
1712
1713 /*
1714 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2
1715 * subdev active state API.
1716 */
1717 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1718 return -EINVAL;
1719
1720 if (alvium->streaming)
1721 return -EBUSY;
1722
1723 ret = alvium_set_frame_interval(alvium, fi);
1724 if (!ret)
1725 ret = alvium_set_frame_rate(alvium);
1726
1727 return ret;
1728 }
1729
alvium_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1730 static int alvium_enum_mbus_code(struct v4l2_subdev *sd,
1731 struct v4l2_subdev_state *sd_state,
1732 struct v4l2_subdev_mbus_code_enum *code)
1733 {
1734 struct alvium_dev *alvium = sd_to_alvium(sd);
1735
1736 if (code->index >= alvium->alvium_csi2_fmt_n)
1737 return -EINVAL;
1738
1739 code->code = alvium->alvium_csi2_fmt[code->index].code;
1740
1741 return 0;
1742 }
1743
1744 static const struct alvium_pixfmt *
alvium_code_to_pixfmt(struct alvium_dev * alvium,u32 code)1745 alvium_code_to_pixfmt(struct alvium_dev *alvium, u32 code)
1746 {
1747 unsigned int i;
1748
1749 for (i = 0; alvium->alvium_csi2_fmt[i].code; ++i)
1750 if (alvium->alvium_csi2_fmt[i].code == code)
1751 return &alvium->alvium_csi2_fmt[i];
1752
1753 return &alvium->alvium_csi2_fmt[0];
1754 }
1755
alvium_set_mode(struct alvium_dev * alvium,struct v4l2_subdev_state * state)1756 static int alvium_set_mode(struct alvium_dev *alvium,
1757 struct v4l2_subdev_state *state)
1758 {
1759 struct v4l2_mbus_framefmt *fmt;
1760 struct v4l2_rect *crop;
1761 int ret;
1762
1763 crop = v4l2_subdev_state_get_crop(state, 0);
1764 fmt = v4l2_subdev_state_get_format(state, 0);
1765
1766 v4l_bound_align_image(&fmt->width, alvium->img_min_width,
1767 alvium->img_max_width, 0,
1768 &fmt->height, alvium->img_min_height,
1769 alvium->img_max_height, 0, 0);
1770
1771 /* alvium don't accept negative crop left/top */
1772 crop->left = clamp((u32)max(0, crop->left), alvium->min_offx,
1773 (u32)(alvium->img_max_width - fmt->width));
1774 crop->top = clamp((u32)max(0, crop->top), alvium->min_offy,
1775 (u32)(alvium->img_max_height - fmt->height));
1776
1777 ret = alvium_set_img_width(alvium, fmt->width);
1778 if (ret)
1779 return ret;
1780
1781 ret = alvium_set_img_height(alvium, fmt->height);
1782 if (ret)
1783 return ret;
1784
1785 ret = alvium_set_img_offx(alvium, crop->left);
1786 if (ret)
1787 return ret;
1788
1789 ret = alvium_set_img_offy(alvium, crop->top);
1790 if (ret)
1791 return ret;
1792
1793 return 0;
1794 }
1795
alvium_set_framefmt(struct alvium_dev * alvium,struct v4l2_mbus_framefmt * format)1796 static int alvium_set_framefmt(struct alvium_dev *alvium,
1797 struct v4l2_mbus_framefmt *format)
1798 {
1799 struct device *dev = &alvium->i2c_client->dev;
1800 const struct alvium_pixfmt *alvium_csi2_fmt;
1801 int ret = 0;
1802
1803 alvium_csi2_fmt = alvium_code_to_pixfmt(alvium, format->code);
1804
1805 ret = alvium_set_mipi_fmt(alvium, alvium_csi2_fmt);
1806 if (ret)
1807 return ret;
1808
1809 if (alvium_csi2_fmt->is_raw) {
1810 ret = alvium_set_bayer_pattern(alvium, alvium_csi2_fmt);
1811 if (ret)
1812 return ret;
1813 }
1814
1815 dev_dbg(dev, "start: %s, mipi_fmt_regval regval = 0x%llx",
1816 __func__, alvium_csi2_fmt->mipi_fmt_regval);
1817
1818 return ret;
1819 }
1820
alvium_s_stream(struct v4l2_subdev * sd,int enable)1821 static int alvium_s_stream(struct v4l2_subdev *sd, int enable)
1822 {
1823 struct alvium_dev *alvium = sd_to_alvium(sd);
1824 struct i2c_client *client = v4l2_get_subdevdata(&alvium->sd);
1825 struct v4l2_mbus_framefmt *fmt;
1826 struct v4l2_subdev_state *state;
1827 int ret = 0;
1828
1829 state = v4l2_subdev_lock_and_get_active_state(sd);
1830
1831 if (enable) {
1832 ret = pm_runtime_resume_and_get(&client->dev);
1833 if (ret < 0)
1834 goto out;
1835
1836 ret = __v4l2_ctrl_handler_setup(&alvium->ctrls.handler);
1837 if (ret)
1838 goto out;
1839
1840 ret = alvium_set_mode(alvium, state);
1841 if (ret)
1842 goto out;
1843
1844 fmt = v4l2_subdev_state_get_format(state, 0);
1845 ret = alvium_set_framefmt(alvium, fmt);
1846 if (ret)
1847 goto out;
1848
1849 ret = alvium_set_stream_mipi(alvium, enable);
1850 if (ret)
1851 goto out;
1852
1853 } else {
1854 alvium_set_stream_mipi(alvium, enable);
1855 pm_runtime_mark_last_busy(&client->dev);
1856 pm_runtime_put_autosuspend(&client->dev);
1857 }
1858
1859 alvium->streaming = !!enable;
1860 v4l2_subdev_unlock_state(state);
1861
1862 return 0;
1863
1864 out:
1865 pm_runtime_put(&client->dev);
1866 v4l2_subdev_unlock_state(state);
1867 return ret;
1868 }
1869
alvium_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)1870 static int alvium_init_state(struct v4l2_subdev *sd,
1871 struct v4l2_subdev_state *state)
1872 {
1873 struct alvium_dev *alvium = sd_to_alvium(sd);
1874 struct alvium_mode *mode = &alvium->mode;
1875 struct v4l2_subdev_format sd_fmt = {
1876 .which = V4L2_SUBDEV_FORMAT_TRY,
1877 .format = alvium_csi2_default_fmt,
1878 };
1879 struct v4l2_subdev_crop sd_crop = {
1880 .which = V4L2_SUBDEV_FORMAT_TRY,
1881 .rect = {
1882 .left = mode->crop.left,
1883 .top = mode->crop.top,
1884 .width = mode->crop.width,
1885 .height = mode->crop.height,
1886 },
1887 };
1888
1889 *v4l2_subdev_state_get_crop(state, 0) = sd_crop.rect;
1890 *v4l2_subdev_state_get_format(state, 0) = sd_fmt.format;
1891
1892 return 0;
1893 }
1894
alvium_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)1895 static int alvium_set_fmt(struct v4l2_subdev *sd,
1896 struct v4l2_subdev_state *sd_state,
1897 struct v4l2_subdev_format *format)
1898 {
1899 struct alvium_dev *alvium = sd_to_alvium(sd);
1900 const struct alvium_pixfmt *alvium_csi2_fmt;
1901 struct v4l2_mbus_framefmt *fmt;
1902 struct v4l2_rect *crop;
1903
1904 fmt = v4l2_subdev_state_get_format(sd_state, 0);
1905 crop = v4l2_subdev_state_get_crop(sd_state, 0);
1906
1907 v4l_bound_align_image(&format->format.width, alvium->img_min_width,
1908 alvium->img_max_width, 0,
1909 &format->format.height, alvium->img_min_height,
1910 alvium->img_max_height, 0, 0);
1911
1912 /* Adjust left and top to prevent roll over sensor area */
1913 crop->left = clamp((u32)crop->left, (u32)0,
1914 (alvium->img_max_width - fmt->width));
1915 crop->top = clamp((u32)crop->top, (u32)0,
1916 (alvium->img_max_height - fmt->height));
1917
1918 /* Set also the crop width and height when set a new fmt */
1919 crop->width = fmt->width;
1920 crop->height = fmt->height;
1921
1922 alvium_csi2_fmt = alvium_code_to_pixfmt(alvium, format->format.code);
1923 fmt->code = alvium_csi2_fmt->code;
1924
1925 *fmt = format->format;
1926
1927 return 0;
1928 }
1929
alvium_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1930 static int alvium_set_selection(struct v4l2_subdev *sd,
1931 struct v4l2_subdev_state *sd_state,
1932 struct v4l2_subdev_selection *sel)
1933 {
1934 struct alvium_dev *alvium = sd_to_alvium(sd);
1935 struct v4l2_mbus_framefmt *fmt;
1936 struct v4l2_rect *crop;
1937
1938 if (sel->target != V4L2_SEL_TGT_CROP)
1939 return -EINVAL;
1940
1941 crop = v4l2_subdev_state_get_crop(sd_state, 0);
1942 fmt = v4l2_subdev_state_get_format(sd_state, 0);
1943
1944 /*
1945 * Alvium can only shift the origin of the img
1946 * then we accept only value with the same value of the actual fmt
1947 */
1948 if (sel->r.width != fmt->width)
1949 sel->r.width = fmt->width;
1950
1951 if (sel->r.height != fmt->height)
1952 sel->r.height = fmt->height;
1953
1954 /* alvium don't accept negative crop left/top */
1955 crop->left = clamp((u32)max(0, sel->r.left), alvium->min_offx,
1956 alvium->img_max_width - sel->r.width);
1957 crop->top = clamp((u32)max(0, sel->r.top), alvium->min_offy,
1958 alvium->img_max_height - sel->r.height);
1959
1960 sel->r = *crop;
1961
1962 return 0;
1963 }
1964
alvium_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)1965 static int alvium_get_selection(struct v4l2_subdev *sd,
1966 struct v4l2_subdev_state *sd_state,
1967 struct v4l2_subdev_selection *sel)
1968 {
1969 struct alvium_dev *alvium = sd_to_alvium(sd);
1970
1971 switch (sel->target) {
1972 /* Current cropping area */
1973 case V4L2_SEL_TGT_CROP:
1974 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);
1975 break;
1976 /* Cropping bounds */
1977 case V4L2_SEL_TGT_NATIVE_SIZE:
1978 sel->r.top = 0;
1979 sel->r.left = 0;
1980 sel->r.width = alvium->img_max_width;
1981 sel->r.height = alvium->img_max_height;
1982 break;
1983 /* Default cropping area */
1984 case V4L2_SEL_TGT_CROP_BOUNDS:
1985 case V4L2_SEL_TGT_CROP_DEFAULT:
1986 sel->r.top = alvium->min_offy;
1987 sel->r.left = alvium->min_offx;
1988 sel->r.width = alvium->img_max_width;
1989 sel->r.height = alvium->img_max_height;
1990 break;
1991 default:
1992 return -EINVAL;
1993 }
1994
1995 return 0;
1996 }
1997
alvium_g_volatile_ctrl(struct v4l2_ctrl * ctrl)1998 static int alvium_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1999 {
2000 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
2001 struct alvium_dev *alvium = sd_to_alvium(sd);
2002 int val;
2003
2004 switch (ctrl->id) {
2005 case V4L2_CID_GAIN:
2006 val = alvium_get_gain(alvium);
2007 if (val < 0)
2008 return val;
2009 alvium->ctrls.gain->val = val;
2010 break;
2011 case V4L2_CID_EXPOSURE:
2012 val = alvium_get_exposure(alvium);
2013 if (val < 0)
2014 return val;
2015 alvium->ctrls.exposure->val = val;
2016 break;
2017 }
2018
2019 return 0;
2020 }
2021
alvium_s_ctrl(struct v4l2_ctrl * ctrl)2022 static int alvium_s_ctrl(struct v4l2_ctrl *ctrl)
2023 {
2024 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
2025 struct alvium_dev *alvium = sd_to_alvium(sd);
2026 struct i2c_client *client = v4l2_get_subdevdata(&alvium->sd);
2027 int ret;
2028
2029 /*
2030 * Applying V4L2 control value only happens
2031 * when power is up for streaming
2032 */
2033 if (!pm_runtime_get_if_in_use(&client->dev))
2034 return 0;
2035
2036 switch (ctrl->id) {
2037 case V4L2_CID_GAIN:
2038 ret = alvium_set_ctrl_gain(alvium, ctrl->val);
2039 break;
2040 case V4L2_CID_AUTOGAIN:
2041 ret = alvium_set_ctrl_auto_gain(alvium, ctrl->val);
2042 break;
2043 case V4L2_CID_EXPOSURE:
2044 ret = alvium_set_ctrl_exposure(alvium, ctrl->val);
2045 break;
2046 case V4L2_CID_EXPOSURE_AUTO:
2047 ret = alvium_set_ctrl_auto_exposure(alvium, ctrl->val);
2048 break;
2049 case V4L2_CID_RED_BALANCE:
2050 ret = alvium_set_ctrl_red_balance_ratio(alvium, ctrl->val);
2051 break;
2052 case V4L2_CID_BLUE_BALANCE:
2053 ret = alvium_set_ctrl_blue_balance_ratio(alvium, ctrl->val);
2054 break;
2055 case V4L2_CID_AUTO_WHITE_BALANCE:
2056 ret = alvium_set_ctrl_awb(alvium, ctrl->val);
2057 break;
2058 case V4L2_CID_HUE:
2059 ret = alvium_set_ctrl_hue(alvium, ctrl->val);
2060 break;
2061 case V4L2_CID_CONTRAST:
2062 ret = alvium_set_ctrl_contrast(alvium, ctrl->val);
2063 break;
2064 case V4L2_CID_SATURATION:
2065 ret = alvium_set_ctrl_saturation(alvium, ctrl->val);
2066 break;
2067 case V4L2_CID_GAMMA:
2068 ret = alvium_set_ctrl_gamma(alvium, ctrl->val);
2069 break;
2070 case V4L2_CID_SHARPNESS:
2071 ret = alvium_set_ctrl_sharpness(alvium, ctrl->val);
2072 break;
2073 case V4L2_CID_HFLIP:
2074 ret = alvium_set_ctrl_hflip(alvium, ctrl->val);
2075 break;
2076 case V4L2_CID_VFLIP:
2077 ret = alvium_set_ctrl_vflip(alvium, ctrl->val);
2078 break;
2079 default:
2080 ret = -EINVAL;
2081 break;
2082 }
2083
2084 pm_runtime_put(&client->dev);
2085
2086 return ret;
2087 }
2088
2089 static const struct v4l2_ctrl_ops alvium_ctrl_ops = {
2090 .g_volatile_ctrl = alvium_g_volatile_ctrl,
2091 .s_ctrl = alvium_s_ctrl,
2092 };
2093
alvium_ctrl_init(struct alvium_dev * alvium)2094 static int alvium_ctrl_init(struct alvium_dev *alvium)
2095 {
2096 const struct v4l2_ctrl_ops *ops = &alvium_ctrl_ops;
2097 struct alvium_ctrls *ctrls = &alvium->ctrls;
2098 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
2099 struct v4l2_fwnode_device_properties props;
2100 int ret;
2101
2102 v4l2_ctrl_handler_init(hdl, 32);
2103
2104 /* Pixel rate is fixed */
2105 ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops,
2106 V4L2_CID_PIXEL_RATE, 0,
2107 ALVIUM_DEFAULT_PIXEL_RATE_MHZ, 1,
2108 ALVIUM_DEFAULT_PIXEL_RATE_MHZ);
2109 ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2110
2111 /* Link freq is fixed */
2112 ctrls->link_freq = v4l2_ctrl_new_int_menu(hdl, ops,
2113 V4L2_CID_LINK_FREQ,
2114 0, 0, &alvium->link_freq);
2115 ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2116
2117 /* Auto/manual white balance */
2118 if (alvium->avail_ft.auto_whiteb) {
2119 ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
2120 V4L2_CID_AUTO_WHITE_BALANCE,
2121 0, 1, 1, 1);
2122 v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
2123 }
2124
2125 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops,
2126 V4L2_CID_BLUE_BALANCE,
2127 alvium->min_bbalance,
2128 alvium->max_bbalance,
2129 alvium->inc_bbalance,
2130 alvium->dft_bbalance);
2131 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops,
2132 V4L2_CID_RED_BALANCE,
2133 alvium->min_rbalance,
2134 alvium->max_rbalance,
2135 alvium->inc_rbalance,
2136 alvium->dft_rbalance);
2137
2138 /* Auto/manual exposure */
2139 if (alvium->avail_ft.auto_exp) {
2140 ctrls->auto_exp =
2141 v4l2_ctrl_new_std_menu(hdl, ops,
2142 V4L2_CID_EXPOSURE_AUTO,
2143 V4L2_EXPOSURE_MANUAL, 0,
2144 V4L2_EXPOSURE_AUTO);
2145 v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
2146 }
2147
2148 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops,
2149 V4L2_CID_EXPOSURE,
2150 alvium->min_exp,
2151 alvium->max_exp,
2152 alvium->inc_exp,
2153 alvium->dft_exp);
2154 ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
2155
2156 /* Auto/manual gain */
2157 if (alvium->avail_ft.auto_gain) {
2158 ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops,
2159 V4L2_CID_AUTOGAIN,
2160 0, 1, 1, 1);
2161 v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
2162 }
2163
2164 if (alvium->avail_ft.gain) {
2165 ctrls->gain = v4l2_ctrl_new_std(hdl, ops,
2166 V4L2_CID_GAIN,
2167 alvium->min_gain,
2168 alvium->max_gain,
2169 alvium->inc_gain,
2170 alvium->dft_gain);
2171 ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
2172 }
2173
2174 if (alvium->avail_ft.sat)
2175 ctrls->saturation = v4l2_ctrl_new_std(hdl, ops,
2176 V4L2_CID_SATURATION,
2177 alvium->min_sat,
2178 alvium->max_sat,
2179 alvium->inc_sat,
2180 alvium->dft_sat);
2181
2182 if (alvium->avail_ft.hue)
2183 ctrls->hue = v4l2_ctrl_new_std(hdl, ops,
2184 V4L2_CID_HUE,
2185 alvium->min_hue,
2186 alvium->max_hue,
2187 alvium->inc_hue,
2188 alvium->dft_hue);
2189
2190 if (alvium->avail_ft.contrast)
2191 ctrls->contrast = v4l2_ctrl_new_std(hdl, ops,
2192 V4L2_CID_CONTRAST,
2193 alvium->min_contrast,
2194 alvium->max_contrast,
2195 alvium->inc_contrast,
2196 alvium->dft_contrast);
2197
2198 if (alvium->avail_ft.gamma)
2199 ctrls->gamma = v4l2_ctrl_new_std(hdl, ops,
2200 V4L2_CID_GAMMA,
2201 alvium->min_gamma,
2202 alvium->max_gamma,
2203 alvium->inc_gamma,
2204 alvium->dft_gamma);
2205
2206 if (alvium->avail_ft.sharp)
2207 ctrls->sharpness = v4l2_ctrl_new_std(hdl, ops,
2208 V4L2_CID_SHARPNESS,
2209 alvium->min_sharp,
2210 alvium->max_sharp,
2211 alvium->inc_sharp,
2212 alvium->dft_sharp);
2213
2214 if (alvium->avail_ft.rev_x)
2215 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops,
2216 V4L2_CID_HFLIP,
2217 0, 1, 1, 0);
2218
2219 if (alvium->avail_ft.rev_y)
2220 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
2221 V4L2_CID_VFLIP,
2222 0, 1, 1, 0);
2223
2224 if (hdl->error) {
2225 ret = hdl->error;
2226 goto free_ctrls;
2227 }
2228
2229 ret = v4l2_fwnode_device_parse(&alvium->i2c_client->dev, &props);
2230 if (ret)
2231 goto free_ctrls;
2232
2233 ret = v4l2_ctrl_new_fwnode_properties(hdl, ops, &props);
2234 if (ret)
2235 goto free_ctrls;
2236
2237 alvium->sd.ctrl_handler = hdl;
2238 return 0;
2239
2240 free_ctrls:
2241 v4l2_ctrl_handler_free(hdl);
2242 return ret;
2243 }
2244
2245 static const struct v4l2_subdev_core_ops alvium_core_ops = {
2246 .log_status = v4l2_ctrl_subdev_log_status,
2247 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
2248 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2249 };
2250
2251 static const struct v4l2_subdev_video_ops alvium_video_ops = {
2252 .s_stream = alvium_s_stream,
2253 };
2254
2255 static const struct v4l2_subdev_pad_ops alvium_pad_ops = {
2256 .enum_mbus_code = alvium_enum_mbus_code,
2257 .get_fmt = v4l2_subdev_get_fmt,
2258 .set_fmt = alvium_set_fmt,
2259 .get_selection = alvium_get_selection,
2260 .set_selection = alvium_set_selection,
2261 .get_frame_interval = alvium_g_frame_interval,
2262 .set_frame_interval = alvium_s_frame_interval,
2263 };
2264
2265 static const struct v4l2_subdev_internal_ops alvium_internal_ops = {
2266 .init_state = alvium_init_state,
2267 };
2268
2269 static const struct v4l2_subdev_ops alvium_subdev_ops = {
2270 .core = &alvium_core_ops,
2271 .pad = &alvium_pad_ops,
2272 .video = &alvium_video_ops,
2273 };
2274
alvium_subdev_init(struct alvium_dev * alvium)2275 static int alvium_subdev_init(struct alvium_dev *alvium)
2276 {
2277 struct i2c_client *client = alvium->i2c_client;
2278 struct device *dev = &alvium->i2c_client->dev;
2279 struct v4l2_subdev *sd = &alvium->sd;
2280 int ret;
2281
2282 /* Setup initial frame interval*/
2283 alvium->frame_interval.numerator = 1;
2284 alvium->frame_interval.denominator = ALVIUM_DEFAULT_FR_HZ;
2285 alvium->fr = ALVIUM_DEFAULT_FR_HZ;
2286
2287 /* Setup the initial mode */
2288 alvium->mode.fmt = alvium_csi2_default_fmt;
2289 alvium->mode.width = alvium_csi2_default_fmt.width;
2290 alvium->mode.height = alvium_csi2_default_fmt.height;
2291 alvium->mode.crop.left = alvium->min_offx;
2292 alvium->mode.crop.top = alvium->min_offy;
2293 alvium->mode.crop.width = alvium_csi2_default_fmt.width;
2294 alvium->mode.crop.height = alvium_csi2_default_fmt.height;
2295
2296 /* init alvium sd */
2297 v4l2_i2c_subdev_init(sd, client, &alvium_subdev_ops);
2298
2299 sd->internal_ops = &alvium_internal_ops;
2300 sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
2301 alvium->pad.flags = MEDIA_PAD_FL_SOURCE;
2302 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2303
2304 ret = media_entity_pads_init(&sd->entity, 1, &alvium->pad);
2305 if (ret) {
2306 dev_err(dev, "Could not register media entity\n");
2307 return ret;
2308 }
2309
2310 ret = alvium_ctrl_init(alvium);
2311 if (ret) {
2312 dev_err(dev, "Control initialization error %d\n", ret);
2313 goto entity_cleanup;
2314 }
2315
2316 alvium->sd.state_lock = alvium->ctrls.handler.lock;
2317
2318 ret = v4l2_subdev_init_finalize(sd);
2319 if (ret < 0) {
2320 dev_err(dev, "subdev initialization error %d\n", ret);
2321 goto err_ctrls;
2322 }
2323
2324 return 0;
2325
2326 err_ctrls:
2327 v4l2_ctrl_handler_free(&alvium->ctrls.handler);
2328 entity_cleanup:
2329 media_entity_cleanup(&alvium->sd.entity);
2330 return ret;
2331 }
2332
alvium_subdev_cleanup(struct alvium_dev * alvium)2333 static void alvium_subdev_cleanup(struct alvium_dev *alvium)
2334 {
2335 v4l2_fwnode_endpoint_free(&alvium->ep);
2336 v4l2_subdev_cleanup(&alvium->sd);
2337 media_entity_cleanup(&alvium->sd.entity);
2338 v4l2_ctrl_handler_free(&alvium->ctrls.handler);
2339 }
2340
alvium_get_dt_data(struct alvium_dev * alvium)2341 static int alvium_get_dt_data(struct alvium_dev *alvium)
2342 {
2343 struct device *dev = &alvium->i2c_client->dev;
2344 struct fwnode_handle *fwnode = dev_fwnode(dev);
2345 struct fwnode_handle *endpoint;
2346
2347 if (!fwnode)
2348 return -EINVAL;
2349
2350 /* Only CSI2 is supported for now: */
2351 alvium->ep.bus_type = V4L2_MBUS_CSI2_DPHY;
2352
2353 endpoint = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, 0);
2354 if (!endpoint) {
2355 dev_err(dev, "endpoint node not found\n");
2356 return -EINVAL;
2357 }
2358
2359 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &alvium->ep)) {
2360 dev_err(dev, "could not parse endpoint\n");
2361 goto error_out;
2362 }
2363
2364 if (!alvium->ep.nr_of_link_frequencies) {
2365 dev_err(dev, "no link frequencies defined");
2366 goto error_out;
2367 }
2368
2369 return 0;
2370
2371 error_out:
2372 v4l2_fwnode_endpoint_free(&alvium->ep);
2373 fwnode_handle_put(endpoint);
2374
2375 return -EINVAL;
2376 }
2377
alvium_set_power(struct alvium_dev * alvium,bool on)2378 static int alvium_set_power(struct alvium_dev *alvium, bool on)
2379 {
2380 int ret;
2381
2382 if (!on)
2383 return regulator_disable(alvium->reg_vcc);
2384
2385 ret = regulator_enable(alvium->reg_vcc);
2386 if (ret)
2387 return ret;
2388
2389 /* alvium boot time 7s */
2390 msleep(7000);
2391 return 0;
2392 }
2393
alvium_runtime_resume(struct device * dev)2394 static int alvium_runtime_resume(struct device *dev)
2395 {
2396 struct v4l2_subdev *sd = dev_get_drvdata(dev);
2397 struct alvium_dev *alvium = sd_to_alvium(sd);
2398 int ret;
2399
2400 ret = alvium_set_power(alvium, true);
2401 if (ret)
2402 return ret;
2403
2404 ret = alvium_hw_init(alvium);
2405 if (ret) {
2406 alvium_set_power(alvium, false);
2407 return ret;
2408 }
2409
2410 return 0;
2411 }
2412
alvium_runtime_suspend(struct device * dev)2413 static int alvium_runtime_suspend(struct device *dev)
2414 {
2415 struct v4l2_subdev *sd = dev_get_drvdata(dev);
2416 struct alvium_dev *alvium = sd_to_alvium(sd);
2417
2418 alvium_set_power(alvium, false);
2419
2420 return 0;
2421 }
2422
2423 static const struct dev_pm_ops alvium_pm_ops = {
2424 RUNTIME_PM_OPS(alvium_runtime_suspend, alvium_runtime_resume, NULL)
2425 };
2426
alvium_probe(struct i2c_client * client)2427 static int alvium_probe(struct i2c_client *client)
2428 {
2429 struct device *dev = &client->dev;
2430 struct alvium_dev *alvium;
2431 int ret;
2432
2433 alvium = devm_kzalloc(dev, sizeof(*alvium), GFP_KERNEL);
2434 if (!alvium)
2435 return -ENOMEM;
2436
2437 alvium->i2c_client = client;
2438
2439 alvium->regmap = devm_cci_regmap_init_i2c(client, 16);
2440 if (IS_ERR(alvium->regmap))
2441 return PTR_ERR(alvium->regmap);
2442
2443 ret = alvium_get_dt_data(alvium);
2444 if (ret)
2445 return ret;
2446
2447 alvium->reg_vcc = devm_regulator_get_optional(dev, "vcc-ext-in");
2448 if (IS_ERR(alvium->reg_vcc))
2449 return dev_err_probe(dev, PTR_ERR(alvium->reg_vcc),
2450 "no vcc-ext-in regulator provided\n");
2451
2452 ret = alvium_set_power(alvium, true);
2453 if (ret)
2454 goto err_powerdown;
2455
2456 if (!alvium_is_alive(alvium)) {
2457 ret = -ENODEV;
2458 dev_err_probe(dev, ret, "Device detection failed\n");
2459 goto err_powerdown;
2460 }
2461
2462 ret = alvium_get_hw_info(alvium);
2463 if (ret) {
2464 dev_err_probe(dev, ret, "get_hw_info fail\n");
2465 goto err_powerdown;
2466 }
2467
2468 ret = alvium_hw_init(alvium);
2469 if (ret) {
2470 dev_err_probe(dev, ret, "hw_init fail\n");
2471 goto err_powerdown;
2472 }
2473
2474 ret = alvium_setup_mipi_fmt(alvium);
2475 if (ret) {
2476 dev_err_probe(dev, ret, "setup_mipi_fmt fail\n");
2477 goto err_powerdown;
2478 }
2479
2480 /*
2481 * Enable runtime PM without autosuspend:
2482 *
2483 * Don't use pm autosuspend (alvium have ~7s boot time).
2484 * Alvium has been powered manually:
2485 * - mark it as active
2486 * - increase the usage count without resuming the device.
2487 */
2488 pm_runtime_set_active(dev);
2489 pm_runtime_get_noresume(dev);
2490 pm_runtime_enable(dev);
2491
2492 /* Initialize the V4L2 subdev. */
2493 ret = alvium_subdev_init(alvium);
2494 if (ret)
2495 goto err_pm;
2496
2497 ret = v4l2_async_register_subdev(&alvium->sd);
2498 if (ret < 0) {
2499 dev_err_probe(dev, ret, "Could not register v4l2 device\n");
2500 goto err_subdev;
2501 }
2502
2503 return 0;
2504
2505 err_subdev:
2506 alvium_subdev_cleanup(alvium);
2507 err_pm:
2508 pm_runtime_disable(dev);
2509 pm_runtime_put_noidle(dev);
2510 kfree(alvium->alvium_csi2_fmt);
2511 err_powerdown:
2512 alvium_set_power(alvium, false);
2513
2514 return ret;
2515 }
2516
alvium_remove(struct i2c_client * client)2517 static void alvium_remove(struct i2c_client *client)
2518 {
2519 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2520 struct alvium_dev *alvium = sd_to_alvium(sd);
2521 struct device *dev = &alvium->i2c_client->dev;
2522
2523 v4l2_async_unregister_subdev(sd);
2524 alvium_subdev_cleanup(alvium);
2525 kfree(alvium->alvium_csi2_fmt);
2526 /*
2527 * Disable runtime PM. In case runtime PM is disabled in the kernel,
2528 * make sure to turn power off manually.
2529 */
2530 pm_runtime_disable(dev);
2531 if (!pm_runtime_status_suspended(dev))
2532 alvium_set_power(alvium, false);
2533 pm_runtime_set_suspended(dev);
2534 }
2535
2536 static const struct of_device_id alvium_of_ids[] = {
2537 { .compatible = "alliedvision,alvium-csi2", },
2538 { }
2539 };
2540 MODULE_DEVICE_TABLE(of, alvium_of_ids);
2541
2542 static struct i2c_driver alvium_i2c_driver = {
2543 .driver = {
2544 .name = "alvium-csi2",
2545 .pm = pm_ptr(&alvium_pm_ops),
2546 .of_match_table = alvium_of_ids,
2547 },
2548 .probe = alvium_probe,
2549 .remove = alvium_remove,
2550 };
2551
2552 module_i2c_driver(alvium_i2c_driver);
2553
2554 MODULE_DESCRIPTION("Allied Vision's Alvium Camera Driver");
2555 MODULE_AUTHOR("Tommaso Merciai <tomm.merciai@gmail.com>");
2556 MODULE_AUTHOR("Martin Hecht <martin.hecht@avnet.eu>");
2557 MODULE_AUTHOR("Avnet Silica Software & Services EMEA");
2558 MODULE_LICENSE("GPL");
2559