1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <linux/dma-mapping.h>
31 #include <drm/ttm/ttm_tt.h>
32
33 #include "nouveau_drv.h"
34 #include "nouveau_chan.h"
35 #include "nouveau_fence.h"
36
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
40 #include "nouveau_mem.h"
41 #include "nouveau_vmm.h"
42
43 #include <nvif/class.h>
44 #include <nvif/if500b.h>
45 #include <nvif/if900b.h>
46
47 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
49 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
50
51 /*
52 * NV10-NV40 tiling helpers
53 */
54
55 static void
nv10_bo_update_tile_region(struct drm_device * dev,struct nouveau_drm_tile * reg,u32 addr,u32 size,u32 pitch,u32 flags)56 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
57 u32 addr, u32 size, u32 pitch, u32 flags)
58 {
59 struct nouveau_drm *drm = nouveau_drm(dev);
60 int i = reg - drm->tile.reg;
61 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
62 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63
64 nouveau_fence_unref(®->fence);
65
66 if (tile->pitch)
67 nvkm_fb_tile_fini(fb, i, tile);
68
69 if (pitch)
70 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71
72 nvkm_fb_tile_prog(fb, i, tile);
73 }
74
75 static struct nouveau_drm_tile *
nv10_bo_get_tile_region(struct drm_device * dev,int i)76 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 {
78 struct nouveau_drm *drm = nouveau_drm(dev);
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80
81 spin_lock(&drm->tile.lock);
82
83 if (!tile->used &&
84 (!tile->fence || nouveau_fence_done(tile->fence)))
85 tile->used = true;
86 else
87 tile = NULL;
88
89 spin_unlock(&drm->tile.lock);
90 return tile;
91 }
92
93 static void
nv10_bo_put_tile_region(struct drm_device * dev,struct nouveau_drm_tile * tile,struct dma_fence * fence)94 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
95 struct dma_fence *fence)
96 {
97 struct nouveau_drm *drm = nouveau_drm(dev);
98
99 if (tile) {
100 spin_lock(&drm->tile.lock);
101 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 tile->used = false;
103 spin_unlock(&drm->tile.lock);
104 }
105 }
106
107 static struct nouveau_drm_tile *
nv10_bo_set_tiling(struct drm_device * dev,u32 addr,u32 size,u32 pitch,u32 zeta)108 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
109 u32 size, u32 pitch, u32 zeta)
110 {
111 struct nouveau_drm *drm = nouveau_drm(dev);
112 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
113 struct nouveau_drm_tile *tile, *found = NULL;
114 int i;
115
116 for (i = 0; i < fb->tile.regions; i++) {
117 tile = nv10_bo_get_tile_region(dev, i);
118
119 if (pitch && !found) {
120 found = tile;
121 continue;
122
123 } else if (tile && fb->tile.region[i].pitch) {
124 /* Kill an unused tile region. */
125 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
126 }
127
128 nv10_bo_put_tile_region(dev, tile, NULL);
129 }
130
131 if (found)
132 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
133 return found;
134 }
135
136 static void
nouveau_bo_del_ttm(struct ttm_buffer_object * bo)137 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138 {
139 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
140 struct drm_device *dev = drm->dev;
141 struct nouveau_bo *nvbo = nouveau_bo(bo);
142
143 WARN_ON(nvbo->bo.pin_count > 0);
144 nouveau_bo_del_io_reserve_lru(bo);
145 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
146
147 /*
148 * If nouveau_bo_new() allocated this buffer, the GEM object was never
149 * initialized, so don't attempt to release it.
150 */
151 if (bo->base.dev) {
152 /* Gem objects not being shared with other VMs get their
153 * dma_resv from a root GEM object.
154 */
155 if (nvbo->no_share)
156 drm_gem_object_put(nvbo->r_obj);
157
158 drm_gem_object_release(&bo->base);
159 } else {
160 dma_resv_fini(&bo->base._resv);
161 }
162
163 kfree(nvbo);
164 }
165
166 static inline u64
roundup_64(u64 x,u32 y)167 roundup_64(u64 x, u32 y)
168 {
169 x += y - 1;
170 do_div(x, y);
171 return x * y;
172 }
173
174 static void
nouveau_bo_fixup_align(struct nouveau_bo * nvbo,int * align,u64 * size)175 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
176 {
177 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
178 struct nvif_device *device = &drm->client.device;
179
180 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
181 if (nvbo->mode) {
182 if (device->info.chipset >= 0x40) {
183 *align = 65536;
184 *size = roundup_64(*size, 64 * nvbo->mode);
185
186 } else if (device->info.chipset >= 0x30) {
187 *align = 32768;
188 *size = roundup_64(*size, 64 * nvbo->mode);
189
190 } else if (device->info.chipset >= 0x20) {
191 *align = 16384;
192 *size = roundup_64(*size, 64 * nvbo->mode);
193
194 } else if (device->info.chipset >= 0x10) {
195 *align = 16384;
196 *size = roundup_64(*size, 32 * nvbo->mode);
197 }
198 }
199 } else {
200 *size = roundup_64(*size, (1 << nvbo->page));
201 *align = max((1 << nvbo->page), *align);
202 }
203
204 *size = roundup_64(*size, PAGE_SIZE);
205 }
206
207 struct nouveau_bo *
nouveau_bo_alloc(struct nouveau_cli * cli,u64 * size,int * align,u32 domain,u32 tile_mode,u32 tile_flags,bool internal)208 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
209 u32 tile_mode, u32 tile_flags, bool internal)
210 {
211 struct nouveau_drm *drm = cli->drm;
212 struct nouveau_bo *nvbo;
213 struct nvif_mmu *mmu = &cli->mmu;
214 struct nvif_vmm *vmm = &nouveau_cli_vmm(cli)->vmm;
215 int i, pi = -1;
216
217 if (!*size) {
218 NV_WARN(drm, "skipped size %016llx\n", *size);
219 return ERR_PTR(-EINVAL);
220 }
221
222 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
223 if (!nvbo)
224 return ERR_PTR(-ENOMEM);
225
226 INIT_LIST_HEAD(&nvbo->head);
227 INIT_LIST_HEAD(&nvbo->entry);
228 INIT_LIST_HEAD(&nvbo->vma_list);
229 nvbo->bo.bdev = &drm->ttm.bdev;
230
231 /* This is confusing, and doesn't actually mean we want an uncached
232 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
233 * into in nouveau_gem_new().
234 */
235 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
236 /* Determine if we can get a cache-coherent map, forcing
237 * uncached mapping if we can't.
238 */
239 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
240 nvbo->force_coherent = true;
241 }
242
243 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
244 if (!nouveau_cli_uvmm(cli) || internal) {
245 /* for BO noVM allocs, don't assign kinds */
246 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
247 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
248 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
249 kfree(nvbo);
250 return ERR_PTR(-EINVAL);
251 }
252
253 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
254 } else if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
255 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
256 nvbo->comp = (tile_flags & 0x00030000) >> 16;
257 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
258 kfree(nvbo);
259 return ERR_PTR(-EINVAL);
260 }
261 } else {
262 nvbo->zeta = (tile_flags & 0x00000007);
263 }
264 nvbo->mode = tile_mode;
265
266 /* Determine the desirable target GPU page size for the buffer. */
267 for (i = 0; i < vmm->page_nr; i++) {
268 /* Because we cannot currently allow VMM maps to fail
269 * during buffer migration, we need to determine page
270 * size for the buffer up-front, and pre-allocate its
271 * page tables.
272 *
273 * Skip page sizes that can't support needed domains.
274 */
275 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
276 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
277 continue;
278 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
279 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
280 continue;
281
282 /* Select this page size if it's the first that supports
283 * the potential memory domains, or when it's compatible
284 * with the requested compression settings.
285 */
286 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
287 pi = i;
288
289 /* Stop once the buffer is larger than the current page size. */
290 if (*size >= 1ULL << vmm->page[i].shift)
291 break;
292 }
293
294 if (WARN_ON(pi < 0)) {
295 kfree(nvbo);
296 return ERR_PTR(-EINVAL);
297 }
298
299 /* Disable compression if suitable settings couldn't be found. */
300 if (nvbo->comp && !vmm->page[pi].comp) {
301 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
302 nvbo->kind = mmu->kind[nvbo->kind];
303 nvbo->comp = 0;
304 }
305 nvbo->page = vmm->page[pi].shift;
306 } else {
307 /* reject other tile flags when in VM mode. */
308 if (tile_mode)
309 return ERR_PTR(-EINVAL);
310 if (tile_flags & ~NOUVEAU_GEM_TILE_NONCONTIG)
311 return ERR_PTR(-EINVAL);
312
313 /* Determine the desirable target GPU page size for the buffer. */
314 for (i = 0; i < vmm->page_nr; i++) {
315 /* Because we cannot currently allow VMM maps to fail
316 * during buffer migration, we need to determine page
317 * size for the buffer up-front, and pre-allocate its
318 * page tables.
319 *
320 * Skip page sizes that can't support needed domains.
321 */
322 if ((domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
323 continue;
324 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
325 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
326 continue;
327
328 /* pick the last one as it will be smallest. */
329 pi = i;
330
331 /* Stop once the buffer is larger than the current page size. */
332 if (*size >= 1ULL << vmm->page[i].shift)
333 break;
334 }
335 if (WARN_ON(pi < 0)) {
336 kfree(nvbo);
337 return ERR_PTR(-EINVAL);
338 }
339 nvbo->page = vmm->page[pi].shift;
340 }
341
342 nouveau_bo_fixup_align(nvbo, align, size);
343
344 return nvbo;
345 }
346
347 int
nouveau_bo_init(struct nouveau_bo * nvbo,u64 size,int align,u32 domain,struct sg_table * sg,struct dma_resv * robj)348 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
349 struct sg_table *sg, struct dma_resv *robj)
350 {
351 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
352 int ret;
353 struct ttm_operation_ctx ctx = {
354 .interruptible = false,
355 .no_wait_gpu = false,
356 .resv = robj,
357 };
358
359 nouveau_bo_placement_set(nvbo, domain, 0);
360 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
361
362 ret = ttm_bo_init_reserved(nvbo->bo.bdev, &nvbo->bo, type,
363 &nvbo->placement, align >> PAGE_SHIFT, &ctx,
364 sg, robj, nouveau_bo_del_ttm);
365 if (ret) {
366 /* ttm will call nouveau_bo_del_ttm if it fails.. */
367 return ret;
368 }
369
370 if (!robj)
371 ttm_bo_unreserve(&nvbo->bo);
372
373 return 0;
374 }
375
376 int
nouveau_bo_new(struct nouveau_cli * cli,u64 size,int align,uint32_t domain,uint32_t tile_mode,uint32_t tile_flags,struct sg_table * sg,struct dma_resv * robj,struct nouveau_bo ** pnvbo)377 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
378 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
379 struct sg_table *sg, struct dma_resv *robj,
380 struct nouveau_bo **pnvbo)
381 {
382 struct nouveau_bo *nvbo;
383 int ret;
384
385 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
386 tile_flags, true);
387 if (IS_ERR(nvbo))
388 return PTR_ERR(nvbo);
389
390 nvbo->bo.base.size = size;
391 dma_resv_init(&nvbo->bo.base._resv);
392 drm_vma_node_reset(&nvbo->bo.base.vma_node);
393
394 /* This must be called before ttm_bo_init_reserved(). Subsequent
395 * bo_move() callbacks might already iterate the GEMs GPUVA list.
396 */
397 drm_gem_gpuva_init(&nvbo->bo.base);
398
399 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
400 if (ret)
401 return ret;
402
403 *pnvbo = nvbo;
404 return 0;
405 }
406
407 static void
set_placement_list(struct ttm_place * pl,unsigned * n,uint32_t domain)408 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
409 {
410 *n = 0;
411
412 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
413 pl[*n].mem_type = TTM_PL_VRAM;
414 pl[*n].flags = 0;
415 (*n)++;
416 }
417 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
418 pl[*n].mem_type = TTM_PL_TT;
419 pl[*n].flags = 0;
420 (*n)++;
421 }
422 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
423 pl[*n].mem_type = TTM_PL_SYSTEM;
424 pl[(*n)++].flags = 0;
425 }
426 }
427
428 static void
set_placement_range(struct nouveau_bo * nvbo,uint32_t domain)429 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
430 {
431 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
432 u64 vram_size = drm->client.device.info.ram_size;
433 unsigned i, fpfn, lpfn;
434
435 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
436 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
437 nvbo->bo.base.size < vram_size / 4) {
438 /*
439 * Make sure that the color and depth buffers are handled
440 * by independent memory controller units. Up to a 9x
441 * speed up when alpha-blending and depth-test are enabled
442 * at the same time.
443 */
444 if (nvbo->zeta) {
445 fpfn = (vram_size / 2) >> PAGE_SHIFT;
446 lpfn = ~0;
447 } else {
448 fpfn = 0;
449 lpfn = (vram_size / 2) >> PAGE_SHIFT;
450 }
451 for (i = 0; i < nvbo->placement.num_placement; ++i) {
452 nvbo->placements[i].fpfn = fpfn;
453 nvbo->placements[i].lpfn = lpfn;
454 }
455 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
456 nvbo->busy_placements[i].fpfn = fpfn;
457 nvbo->busy_placements[i].lpfn = lpfn;
458 }
459 }
460 }
461
462 void
nouveau_bo_placement_set(struct nouveau_bo * nvbo,uint32_t domain,uint32_t busy)463 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
464 uint32_t busy)
465 {
466 struct ttm_placement *pl = &nvbo->placement;
467
468 pl->placement = nvbo->placements;
469 set_placement_list(nvbo->placements, &pl->num_placement, domain);
470
471 pl->busy_placement = nvbo->busy_placements;
472 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
473 domain | busy);
474
475 set_placement_range(nvbo, domain);
476 }
477
478 int
nouveau_bo_pin(struct nouveau_bo * nvbo,uint32_t domain,bool contig)479 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
480 {
481 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
482 struct ttm_buffer_object *bo = &nvbo->bo;
483 bool force = false, evict = false;
484 int ret;
485
486 ret = ttm_bo_reserve(bo, false, false, NULL);
487 if (ret)
488 return ret;
489
490 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
491 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
492 if (!nvbo->contig) {
493 nvbo->contig = true;
494 force = true;
495 evict = true;
496 }
497 }
498
499 if (nvbo->bo.pin_count) {
500 bool error = evict;
501
502 switch (bo->resource->mem_type) {
503 case TTM_PL_VRAM:
504 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
505 break;
506 case TTM_PL_TT:
507 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
508 break;
509 default:
510 break;
511 }
512
513 if (error) {
514 NV_ERROR(drm, "bo %p pinned elsewhere: "
515 "0x%08x vs 0x%08x\n", bo,
516 bo->resource->mem_type, domain);
517 ret = -EBUSY;
518 }
519 ttm_bo_pin(&nvbo->bo);
520 goto out;
521 }
522
523 if (evict) {
524 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
525 ret = nouveau_bo_validate(nvbo, false, false);
526 if (ret)
527 goto out;
528 }
529
530 nouveau_bo_placement_set(nvbo, domain, 0);
531 ret = nouveau_bo_validate(nvbo, false, false);
532 if (ret)
533 goto out;
534
535 ttm_bo_pin(&nvbo->bo);
536
537 switch (bo->resource->mem_type) {
538 case TTM_PL_VRAM:
539 drm->gem.vram_available -= bo->base.size;
540 break;
541 case TTM_PL_TT:
542 drm->gem.gart_available -= bo->base.size;
543 break;
544 default:
545 break;
546 }
547
548 out:
549 if (force && ret)
550 nvbo->contig = false;
551 ttm_bo_unreserve(bo);
552 return ret;
553 }
554
555 int
nouveau_bo_unpin(struct nouveau_bo * nvbo)556 nouveau_bo_unpin(struct nouveau_bo *nvbo)
557 {
558 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
559 struct ttm_buffer_object *bo = &nvbo->bo;
560 int ret;
561
562 ret = ttm_bo_reserve(bo, false, false, NULL);
563 if (ret)
564 return ret;
565
566 ttm_bo_unpin(&nvbo->bo);
567 if (!nvbo->bo.pin_count) {
568 switch (bo->resource->mem_type) {
569 case TTM_PL_VRAM:
570 drm->gem.vram_available += bo->base.size;
571 break;
572 case TTM_PL_TT:
573 drm->gem.gart_available += bo->base.size;
574 break;
575 default:
576 break;
577 }
578 }
579
580 ttm_bo_unreserve(bo);
581 return 0;
582 }
583
584 int
nouveau_bo_map(struct nouveau_bo * nvbo)585 nouveau_bo_map(struct nouveau_bo *nvbo)
586 {
587 int ret;
588
589 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
590 if (ret)
591 return ret;
592
593 ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap);
594
595 ttm_bo_unreserve(&nvbo->bo);
596 return ret;
597 }
598
599 void
nouveau_bo_unmap(struct nouveau_bo * nvbo)600 nouveau_bo_unmap(struct nouveau_bo *nvbo)
601 {
602 if (!nvbo)
603 return;
604
605 ttm_bo_kunmap(&nvbo->kmap);
606 }
607
608 void
nouveau_bo_sync_for_device(struct nouveau_bo * nvbo)609 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
610 {
611 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
612 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
613 int i, j;
614
615 if (!ttm_dma || !ttm_dma->dma_address)
616 return;
617 if (!ttm_dma->pages) {
618 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
619 return;
620 }
621
622 /* Don't waste time looping if the object is coherent */
623 if (nvbo->force_coherent)
624 return;
625
626 i = 0;
627 while (i < ttm_dma->num_pages) {
628 struct page *p = ttm_dma->pages[i];
629 size_t num_pages = 1;
630
631 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
632 if (++p != ttm_dma->pages[j])
633 break;
634
635 ++num_pages;
636 }
637 dma_sync_single_for_device(drm->dev->dev,
638 ttm_dma->dma_address[i],
639 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
640 i += num_pages;
641 }
642 }
643
644 void
nouveau_bo_sync_for_cpu(struct nouveau_bo * nvbo)645 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
646 {
647 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
648 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
649 int i, j;
650
651 if (!ttm_dma || !ttm_dma->dma_address)
652 return;
653 if (!ttm_dma->pages) {
654 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
655 return;
656 }
657
658 /* Don't waste time looping if the object is coherent */
659 if (nvbo->force_coherent)
660 return;
661
662 i = 0;
663 while (i < ttm_dma->num_pages) {
664 struct page *p = ttm_dma->pages[i];
665 size_t num_pages = 1;
666
667 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
668 if (++p != ttm_dma->pages[j])
669 break;
670
671 ++num_pages;
672 }
673
674 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
675 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
676 i += num_pages;
677 }
678 }
679
nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object * bo)680 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
681 {
682 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
683 struct nouveau_bo *nvbo = nouveau_bo(bo);
684
685 mutex_lock(&drm->ttm.io_reserve_mutex);
686 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
687 mutex_unlock(&drm->ttm.io_reserve_mutex);
688 }
689
nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object * bo)690 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
691 {
692 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
693 struct nouveau_bo *nvbo = nouveau_bo(bo);
694
695 mutex_lock(&drm->ttm.io_reserve_mutex);
696 list_del_init(&nvbo->io_reserve_lru);
697 mutex_unlock(&drm->ttm.io_reserve_mutex);
698 }
699
700 int
nouveau_bo_validate(struct nouveau_bo * nvbo,bool interruptible,bool no_wait_gpu)701 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
702 bool no_wait_gpu)
703 {
704 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
705 int ret;
706
707 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
708 if (ret)
709 return ret;
710
711 nouveau_bo_sync_for_device(nvbo);
712
713 return 0;
714 }
715
716 void
nouveau_bo_wr16(struct nouveau_bo * nvbo,unsigned index,u16 val)717 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
718 {
719 bool is_iomem;
720 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
721
722 mem += index;
723
724 if (is_iomem)
725 iowrite16_native(val, (void __force __iomem *)mem);
726 else
727 *mem = val;
728 }
729
730 u32
nouveau_bo_rd32(struct nouveau_bo * nvbo,unsigned index)731 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
732 {
733 bool is_iomem;
734 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
735
736 mem += index;
737
738 if (is_iomem)
739 return ioread32_native((void __force __iomem *)mem);
740 else
741 return *mem;
742 }
743
744 void
nouveau_bo_wr32(struct nouveau_bo * nvbo,unsigned index,u32 val)745 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
746 {
747 bool is_iomem;
748 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
749
750 mem += index;
751
752 if (is_iomem)
753 iowrite32_native(val, (void __force __iomem *)mem);
754 else
755 *mem = val;
756 }
757
758 static struct ttm_tt *
nouveau_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)759 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
760 {
761 #if IS_ENABLED(CONFIG_AGP)
762 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
763
764 if (drm->agp.bridge) {
765 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
766 }
767 #endif
768
769 return nouveau_sgdma_create_ttm(bo, page_flags);
770 }
771
772 static int
nouveau_ttm_tt_bind(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_resource * reg)773 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
774 struct ttm_resource *reg)
775 {
776 #if IS_ENABLED(CONFIG_AGP)
777 struct nouveau_drm *drm = nouveau_bdev(bdev);
778 #endif
779 if (!reg)
780 return -EINVAL;
781 #if IS_ENABLED(CONFIG_AGP)
782 if (drm->agp.bridge)
783 return ttm_agp_bind(ttm, reg);
784 #endif
785 return nouveau_sgdma_bind(bdev, ttm, reg);
786 }
787
788 static void
nouveau_ttm_tt_unbind(struct ttm_device * bdev,struct ttm_tt * ttm)789 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
790 {
791 #if IS_ENABLED(CONFIG_AGP)
792 struct nouveau_drm *drm = nouveau_bdev(bdev);
793
794 if (drm->agp.bridge) {
795 ttm_agp_unbind(ttm);
796 return;
797 }
798 #endif
799 nouveau_sgdma_unbind(bdev, ttm);
800 }
801
802 static void
nouveau_bo_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * pl)803 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
804 {
805 struct nouveau_bo *nvbo = nouveau_bo(bo);
806
807 switch (bo->resource->mem_type) {
808 case TTM_PL_VRAM:
809 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
810 NOUVEAU_GEM_DOMAIN_CPU);
811 break;
812 default:
813 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
814 break;
815 }
816
817 *pl = nvbo->placement;
818 }
819
820 static int
nouveau_bo_move_prep(struct nouveau_drm * drm,struct ttm_buffer_object * bo,struct ttm_resource * reg)821 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
822 struct ttm_resource *reg)
823 {
824 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
825 struct nouveau_mem *new_mem = nouveau_mem(reg);
826 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
827 int ret;
828
829 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
830 old_mem->mem.size, &old_mem->vma[0]);
831 if (ret)
832 return ret;
833
834 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
835 new_mem->mem.size, &old_mem->vma[1]);
836 if (ret)
837 goto done;
838
839 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
840 if (ret)
841 goto done;
842
843 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
844 done:
845 if (ret) {
846 nvif_vmm_put(vmm, &old_mem->vma[1]);
847 nvif_vmm_put(vmm, &old_mem->vma[0]);
848 }
849 return 0;
850 }
851
852 static int
nouveau_bo_move_m2mf(struct ttm_buffer_object * bo,int evict,struct ttm_operation_ctx * ctx,struct ttm_resource * new_reg)853 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
854 struct ttm_operation_ctx *ctx,
855 struct ttm_resource *new_reg)
856 {
857 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
858 struct nouveau_channel *chan = drm->ttm.chan;
859 struct nouveau_cli *cli = (void *)chan->user.client;
860 struct nouveau_fence *fence;
861 int ret;
862
863 /* create temporary vmas for the transfer and attach them to the
864 * old nvkm_mem node, these will get cleaned up after ttm has
865 * destroyed the ttm_resource
866 */
867 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
868 ret = nouveau_bo_move_prep(drm, bo, new_reg);
869 if (ret)
870 return ret;
871 }
872
873 if (drm_drv_uses_atomic_modeset(drm->dev))
874 mutex_lock(&cli->mutex);
875 else
876 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
877
878 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
879 if (ret)
880 goto out_unlock;
881
882 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
883 if (ret)
884 goto out_unlock;
885
886 ret = nouveau_fence_new(&fence, chan);
887 if (ret)
888 goto out_unlock;
889
890 /* TODO: figure out a better solution here
891 *
892 * wait on the fence here explicitly as going through
893 * ttm_bo_move_accel_cleanup somehow doesn't seem to do it.
894 *
895 * Without this the operation can timeout and we'll fallback to a
896 * software copy, which might take several minutes to finish.
897 */
898 nouveau_fence_wait(fence, false, false);
899 ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false,
900 new_reg);
901 nouveau_fence_unref(&fence);
902
903 out_unlock:
904 mutex_unlock(&cli->mutex);
905 return ret;
906 }
907
908 void
nouveau_bo_move_init(struct nouveau_drm * drm)909 nouveau_bo_move_init(struct nouveau_drm *drm)
910 {
911 static const struct _method_table {
912 const char *name;
913 int engine;
914 s32 oclass;
915 int (*exec)(struct nouveau_channel *,
916 struct ttm_buffer_object *,
917 struct ttm_resource *, struct ttm_resource *);
918 int (*init)(struct nouveau_channel *, u32 handle);
919 } _methods[] = {
920 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
921 { "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init },
922 { "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init },
923 { "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init },
924 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
925 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
926 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
927 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
928 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
929 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
930 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
931 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
932 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
933 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
934 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
935 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
936 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
937 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
938 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
939 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
940 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
941 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
942 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
943 {},
944 };
945 const struct _method_table *mthd = _methods;
946 const char *name = "CPU";
947 int ret;
948
949 do {
950 struct nouveau_channel *chan;
951
952 if (mthd->engine)
953 chan = drm->cechan;
954 else
955 chan = drm->channel;
956 if (chan == NULL)
957 continue;
958
959 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
960 mthd->oclass | (mthd->engine << 16),
961 mthd->oclass, NULL, 0,
962 &drm->ttm.copy);
963 if (ret == 0) {
964 ret = mthd->init(chan, drm->ttm.copy.handle);
965 if (ret) {
966 nvif_object_dtor(&drm->ttm.copy);
967 continue;
968 }
969
970 drm->ttm.move = mthd->exec;
971 drm->ttm.chan = chan;
972 name = mthd->name;
973 break;
974 }
975 } while ((++mthd)->exec);
976
977 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
978 }
979
nouveau_bo_move_ntfy(struct ttm_buffer_object * bo,struct ttm_resource * new_reg)980 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
981 struct ttm_resource *new_reg)
982 {
983 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
984 struct nouveau_bo *nvbo = nouveau_bo(bo);
985 struct nouveau_vma *vma;
986 long ret;
987
988 /* ttm can now (stupidly) pass the driver bos it didn't create... */
989 if (bo->destroy != nouveau_bo_del_ttm)
990 return;
991
992 nouveau_bo_del_io_reserve_lru(bo);
993
994 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
995 mem->mem.page == nvbo->page) {
996 list_for_each_entry(vma, &nvbo->vma_list, head) {
997 nouveau_vma_map(vma, mem);
998 }
999 nouveau_uvmm_bo_map_all(nvbo, mem);
1000 } else {
1001 list_for_each_entry(vma, &nvbo->vma_list, head) {
1002 ret = dma_resv_wait_timeout(bo->base.resv,
1003 DMA_RESV_USAGE_BOOKKEEP,
1004 false, 15 * HZ);
1005 WARN_ON(ret <= 0);
1006 nouveau_vma_unmap(vma);
1007 }
1008 nouveau_uvmm_bo_unmap_all(nvbo);
1009 }
1010
1011 if (new_reg)
1012 nvbo->offset = (new_reg->start << PAGE_SHIFT);
1013
1014 }
1015
1016 static int
nouveau_bo_vm_bind(struct ttm_buffer_object * bo,struct ttm_resource * new_reg,struct nouveau_drm_tile ** new_tile)1017 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1018 struct nouveau_drm_tile **new_tile)
1019 {
1020 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1021 struct drm_device *dev = drm->dev;
1022 struct nouveau_bo *nvbo = nouveau_bo(bo);
1023 u64 offset = new_reg->start << PAGE_SHIFT;
1024
1025 *new_tile = NULL;
1026 if (new_reg->mem_type != TTM_PL_VRAM)
1027 return 0;
1028
1029 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1030 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
1031 nvbo->mode, nvbo->zeta);
1032 }
1033
1034 return 0;
1035 }
1036
1037 static void
nouveau_bo_vm_cleanup(struct ttm_buffer_object * bo,struct nouveau_drm_tile * new_tile,struct nouveau_drm_tile ** old_tile)1038 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1039 struct nouveau_drm_tile *new_tile,
1040 struct nouveau_drm_tile **old_tile)
1041 {
1042 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1043 struct drm_device *dev = drm->dev;
1044 struct dma_fence *fence;
1045 int ret;
1046
1047 ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
1048 &fence);
1049 if (ret)
1050 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
1051 false, MAX_SCHEDULE_TIMEOUT);
1052
1053 nv10_bo_put_tile_region(dev, *old_tile, fence);
1054 *old_tile = new_tile;
1055 }
1056
1057 static int
nouveau_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_resource * new_reg,struct ttm_place * hop)1058 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1059 struct ttm_operation_ctx *ctx,
1060 struct ttm_resource *new_reg,
1061 struct ttm_place *hop)
1062 {
1063 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1064 struct nouveau_bo *nvbo = nouveau_bo(bo);
1065 struct drm_gem_object *obj = &bo->base;
1066 struct ttm_resource *old_reg = bo->resource;
1067 struct nouveau_drm_tile *new_tile = NULL;
1068 int ret = 0;
1069
1070 if (new_reg->mem_type == TTM_PL_TT) {
1071 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
1072 if (ret)
1073 return ret;
1074 }
1075
1076 drm_gpuvm_bo_gem_evict(obj, evict);
1077 nouveau_bo_move_ntfy(bo, new_reg);
1078 ret = ttm_bo_wait_ctx(bo, ctx);
1079 if (ret)
1080 goto out_ntfy;
1081
1082 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1083 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1084 if (ret)
1085 goto out_ntfy;
1086 }
1087
1088 /* Fake bo copy. */
1089 if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1090 !bo->ttm)) {
1091 ttm_bo_move_null(bo, new_reg);
1092 goto out;
1093 }
1094
1095 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1096 new_reg->mem_type == TTM_PL_TT) {
1097 ttm_bo_move_null(bo, new_reg);
1098 goto out;
1099 }
1100
1101 if (old_reg->mem_type == TTM_PL_TT &&
1102 new_reg->mem_type == TTM_PL_SYSTEM) {
1103 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1104 ttm_resource_free(bo, &bo->resource);
1105 ttm_bo_assign_mem(bo, new_reg);
1106 goto out;
1107 }
1108
1109 /* Hardware assisted copy. */
1110 if (drm->ttm.move) {
1111 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1112 new_reg->mem_type == TTM_PL_VRAM) ||
1113 (old_reg->mem_type == TTM_PL_VRAM &&
1114 new_reg->mem_type == TTM_PL_SYSTEM)) {
1115 hop->fpfn = 0;
1116 hop->lpfn = 0;
1117 hop->mem_type = TTM_PL_TT;
1118 hop->flags = 0;
1119 return -EMULTIHOP;
1120 }
1121 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1122 new_reg);
1123 } else
1124 ret = -ENODEV;
1125
1126 if (ret) {
1127 /* Fallback to software copy. */
1128 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1129 }
1130
1131 out:
1132 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1133 if (ret)
1134 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1135 else
1136 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1137 }
1138 out_ntfy:
1139 if (ret) {
1140 nouveau_bo_move_ntfy(bo, bo->resource);
1141 drm_gpuvm_bo_gem_evict(obj, !evict);
1142 }
1143 return ret;
1144 }
1145
1146 static void
nouveau_ttm_io_mem_free_locked(struct nouveau_drm * drm,struct ttm_resource * reg)1147 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1148 struct ttm_resource *reg)
1149 {
1150 struct nouveau_mem *mem = nouveau_mem(reg);
1151
1152 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1153 switch (reg->mem_type) {
1154 case TTM_PL_TT:
1155 if (mem->kind)
1156 nvif_object_unmap_handle(&mem->mem.object);
1157 break;
1158 case TTM_PL_VRAM:
1159 nvif_object_unmap_handle(&mem->mem.object);
1160 break;
1161 default:
1162 break;
1163 }
1164 }
1165 }
1166
1167 static int
nouveau_ttm_io_mem_reserve(struct ttm_device * bdev,struct ttm_resource * reg)1168 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1169 {
1170 struct nouveau_drm *drm = nouveau_bdev(bdev);
1171 struct nvkm_device *device = nvxx_device(&drm->client.device);
1172 struct nouveau_mem *mem = nouveau_mem(reg);
1173 struct nvif_mmu *mmu = &drm->client.mmu;
1174 int ret;
1175
1176 mutex_lock(&drm->ttm.io_reserve_mutex);
1177 retry:
1178 switch (reg->mem_type) {
1179 case TTM_PL_SYSTEM:
1180 /* System memory */
1181 ret = 0;
1182 goto out;
1183 case TTM_PL_TT:
1184 #if IS_ENABLED(CONFIG_AGP)
1185 if (drm->agp.bridge) {
1186 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1187 drm->agp.base;
1188 reg->bus.is_iomem = !drm->agp.cma;
1189 reg->bus.caching = ttm_write_combined;
1190 }
1191 #endif
1192 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1193 !mem->kind) {
1194 /* untiled */
1195 ret = 0;
1196 break;
1197 }
1198 fallthrough; /* tiled memory */
1199 case TTM_PL_VRAM:
1200 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1201 device->func->resource_addr(device, 1);
1202 reg->bus.is_iomem = true;
1203
1204 /* Some BARs do not support being ioremapped WC */
1205 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1206 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1207 reg->bus.caching = ttm_uncached;
1208 else
1209 reg->bus.caching = ttm_write_combined;
1210
1211 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1212 union {
1213 struct nv50_mem_map_v0 nv50;
1214 struct gf100_mem_map_v0 gf100;
1215 } args;
1216 u64 handle, length;
1217 u32 argc = 0;
1218
1219 switch (mem->mem.object.oclass) {
1220 case NVIF_CLASS_MEM_NV50:
1221 args.nv50.version = 0;
1222 args.nv50.ro = 0;
1223 args.nv50.kind = mem->kind;
1224 args.nv50.comp = mem->comp;
1225 argc = sizeof(args.nv50);
1226 break;
1227 case NVIF_CLASS_MEM_GF100:
1228 args.gf100.version = 0;
1229 args.gf100.ro = 0;
1230 args.gf100.kind = mem->kind;
1231 argc = sizeof(args.gf100);
1232 break;
1233 default:
1234 WARN_ON(1);
1235 break;
1236 }
1237
1238 ret = nvif_object_map_handle(&mem->mem.object,
1239 &args, argc,
1240 &handle, &length);
1241 if (ret != 1) {
1242 if (WARN_ON(ret == 0))
1243 ret = -EINVAL;
1244 goto out;
1245 }
1246
1247 reg->bus.offset = handle;
1248 }
1249 ret = 0;
1250 break;
1251 default:
1252 ret = -EINVAL;
1253 }
1254
1255 out:
1256 if (ret == -ENOSPC) {
1257 struct nouveau_bo *nvbo;
1258
1259 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1260 typeof(*nvbo),
1261 io_reserve_lru);
1262 if (nvbo) {
1263 list_del_init(&nvbo->io_reserve_lru);
1264 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1265 bdev->dev_mapping);
1266 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1267 goto retry;
1268 }
1269
1270 }
1271 mutex_unlock(&drm->ttm.io_reserve_mutex);
1272 return ret;
1273 }
1274
1275 static void
nouveau_ttm_io_mem_free(struct ttm_device * bdev,struct ttm_resource * reg)1276 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1277 {
1278 struct nouveau_drm *drm = nouveau_bdev(bdev);
1279
1280 mutex_lock(&drm->ttm.io_reserve_mutex);
1281 nouveau_ttm_io_mem_free_locked(drm, reg);
1282 mutex_unlock(&drm->ttm.io_reserve_mutex);
1283 }
1284
nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object * bo)1285 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1286 {
1287 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1288 struct nouveau_bo *nvbo = nouveau_bo(bo);
1289 struct nvkm_device *device = nvxx_device(&drm->client.device);
1290 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1291 int i, ret;
1292
1293 /* as long as the bo isn't in vram, and isn't tiled, we've got
1294 * nothing to do here.
1295 */
1296 if (bo->resource->mem_type != TTM_PL_VRAM) {
1297 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1298 !nvbo->kind)
1299 return 0;
1300
1301 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1302 return 0;
1303
1304 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1305
1306 } else {
1307 /* make sure bo is in mappable vram */
1308 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1309 bo->resource->start + PFN_UP(bo->resource->size) < mappable)
1310 return 0;
1311
1312 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1313 nvbo->placements[i].fpfn = 0;
1314 nvbo->placements[i].lpfn = mappable;
1315 }
1316
1317 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1318 nvbo->busy_placements[i].fpfn = 0;
1319 nvbo->busy_placements[i].lpfn = mappable;
1320 }
1321
1322 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1323 }
1324
1325 ret = nouveau_bo_validate(nvbo, false, false);
1326 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1327 return VM_FAULT_NOPAGE;
1328 else if (unlikely(ret))
1329 return VM_FAULT_SIGBUS;
1330
1331 ttm_bo_move_to_lru_tail_unlocked(bo);
1332 return 0;
1333 }
1334
1335 static int
nouveau_ttm_tt_populate(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)1336 nouveau_ttm_tt_populate(struct ttm_device *bdev,
1337 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1338 {
1339 struct ttm_tt *ttm_dma = (void *)ttm;
1340 struct nouveau_drm *drm;
1341 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1342
1343 if (ttm_tt_is_populated(ttm))
1344 return 0;
1345
1346 if (slave && ttm->sg) {
1347 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1348 ttm->num_pages);
1349 return 0;
1350 }
1351
1352 drm = nouveau_bdev(bdev);
1353
1354 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1355 }
1356
1357 static void
nouveau_ttm_tt_unpopulate(struct ttm_device * bdev,struct ttm_tt * ttm)1358 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1359 struct ttm_tt *ttm)
1360 {
1361 struct nouveau_drm *drm;
1362 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1363
1364 if (slave)
1365 return;
1366
1367 nouveau_ttm_tt_unbind(bdev, ttm);
1368
1369 drm = nouveau_bdev(bdev);
1370
1371 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1372 }
1373
1374 static void
nouveau_ttm_tt_destroy(struct ttm_device * bdev,struct ttm_tt * ttm)1375 nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1376 struct ttm_tt *ttm)
1377 {
1378 #if IS_ENABLED(CONFIG_AGP)
1379 struct nouveau_drm *drm = nouveau_bdev(bdev);
1380 if (drm->agp.bridge) {
1381 ttm_agp_destroy(ttm);
1382 return;
1383 }
1384 #endif
1385 nouveau_sgdma_destroy(bdev, ttm);
1386 }
1387
1388 void
nouveau_bo_fence(struct nouveau_bo * nvbo,struct nouveau_fence * fence,bool exclusive)1389 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1390 {
1391 struct dma_resv *resv = nvbo->bo.base.resv;
1392
1393 if (!fence)
1394 return;
1395
1396 dma_resv_add_fence(resv, &fence->base, exclusive ?
1397 DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1398 }
1399
1400 static void
nouveau_bo_delete_mem_notify(struct ttm_buffer_object * bo)1401 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1402 {
1403 nouveau_bo_move_ntfy(bo, NULL);
1404 }
1405
1406 struct ttm_device_funcs nouveau_bo_driver = {
1407 .ttm_tt_create = &nouveau_ttm_tt_create,
1408 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1409 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1410 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1411 .eviction_valuable = ttm_bo_eviction_valuable,
1412 .evict_flags = nouveau_bo_evict_flags,
1413 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1414 .move = nouveau_bo_move,
1415 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1416 .io_mem_free = &nouveau_ttm_io_mem_free,
1417 };
1418