1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27 
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30 
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41 
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48 
49 /*
50  * DO NOT use these for err/warn/info/debug messages.
51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52  * They are more MGPU friendly.
53  */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58 
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63 
64 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
66 
67 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
69 
70 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
72 
73 #define SMU13_VOLTAGE_SCALE 4
74 
75 #define LINK_WIDTH_MAX				6
76 #define LINK_SPEED_MAX				3
77 
78 #define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
81 #define smnPCIE_LC_SPEED_CNTL			0x11140290
82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
84 
85 #define ENABLE_IMU_ARG_GFXOFF_ENABLE		1
86 
87 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
88 
89 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
90 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
91 
smu_v13_0_init_microcode(struct smu_context * smu)92 int smu_v13_0_init_microcode(struct smu_context *smu)
93 {
94 	struct amdgpu_device *adev = smu->adev;
95 	char fw_name[30];
96 	char ucode_prefix[30];
97 	int err = 0;
98 	const struct smc_firmware_header_v1_0 *hdr;
99 	const struct common_firmware_header *header;
100 	struct amdgpu_firmware_info *ucode = NULL;
101 
102 	/* doesn't need to load smu firmware in IOV mode */
103 	if (amdgpu_sriov_vf(adev))
104 		return 0;
105 
106 	amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
107 
108 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
109 
110 	err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
111 	if (err)
112 		goto out;
113 
114 	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
115 	amdgpu_ucode_print_smc_hdr(&hdr->header);
116 	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
117 
118 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
119 		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
120 		ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
121 		ucode->fw = adev->pm.fw;
122 		header = (const struct common_firmware_header *)ucode->fw->data;
123 		adev->firmware.fw_size +=
124 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
125 	}
126 
127 out:
128 	if (err)
129 		amdgpu_ucode_release(&adev->pm.fw);
130 	return err;
131 }
132 
smu_v13_0_fini_microcode(struct smu_context * smu)133 void smu_v13_0_fini_microcode(struct smu_context *smu)
134 {
135 	struct amdgpu_device *adev = smu->adev;
136 
137 	amdgpu_ucode_release(&adev->pm.fw);
138 	adev->pm.fw_version = 0;
139 }
140 
smu_v13_0_load_microcode(struct smu_context * smu)141 int smu_v13_0_load_microcode(struct smu_context *smu)
142 {
143 #if 0
144 	struct amdgpu_device *adev = smu->adev;
145 	const uint32_t *src;
146 	const struct smc_firmware_header_v1_0 *hdr;
147 	uint32_t addr_start = MP1_SRAM;
148 	uint32_t i;
149 	uint32_t smc_fw_size;
150 	uint32_t mp1_fw_flags;
151 
152 	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
153 	src = (const uint32_t *)(adev->pm.fw->data +
154 				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
155 	smc_fw_size = hdr->header.ucode_size_bytes;
156 
157 	for (i = 1; i < smc_fw_size/4 - 1; i++) {
158 		WREG32_PCIE(addr_start, src[i]);
159 		addr_start += 4;
160 	}
161 
162 	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
163 		    1 & MP1_SMN_PUB_CTRL__RESET_MASK);
164 	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
165 		    1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
166 
167 	for (i = 0; i < adev->usec_timeout; i++) {
168 		mp1_fw_flags = RREG32_PCIE(MP1_Public |
169 					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
170 		if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
171 		    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
172 			break;
173 		udelay(1);
174 	}
175 
176 	if (i == adev->usec_timeout)
177 		return -ETIME;
178 #endif
179 
180 	return 0;
181 }
182 
smu_v13_0_init_pptable_microcode(struct smu_context * smu)183 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
184 {
185 	struct amdgpu_device *adev = smu->adev;
186 	struct amdgpu_firmware_info *ucode = NULL;
187 	uint32_t size = 0, pptable_id = 0;
188 	int ret = 0;
189 	void *table;
190 
191 	/* doesn't need to load smu firmware in IOV mode */
192 	if (amdgpu_sriov_vf(adev))
193 		return 0;
194 
195 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
196 		return 0;
197 
198 	if (!adev->scpm_enabled)
199 		return 0;
200 
201 	if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 7)) ||
202 	    (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) ||
203 	    (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)))
204 		return 0;
205 
206 	/* override pptable_id from driver parameter */
207 	if (amdgpu_smu_pptable_id >= 0) {
208 		pptable_id = amdgpu_smu_pptable_id;
209 		dev_info(adev->dev, "override pptable id %d\n", pptable_id);
210 	} else {
211 		pptable_id = smu->smu_table.boot_values.pp_table_id;
212 	}
213 
214 	/* "pptable_id == 0" means vbios carries the pptable. */
215 	if (!pptable_id)
216 		return 0;
217 
218 	ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
219 	if (ret)
220 		return ret;
221 
222 	smu->pptable_firmware.data = table;
223 	smu->pptable_firmware.size = size;
224 
225 	ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
226 	ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
227 	ucode->fw = &smu->pptable_firmware;
228 	adev->firmware.fw_size +=
229 		ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
230 
231 	return 0;
232 }
233 
smu_v13_0_check_fw_status(struct smu_context * smu)234 int smu_v13_0_check_fw_status(struct smu_context *smu)
235 {
236 	struct amdgpu_device *adev = smu->adev;
237 	uint32_t mp1_fw_flags;
238 
239 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
240 	case IP_VERSION(13, 0, 4):
241 	case IP_VERSION(13, 0, 11):
242 		mp1_fw_flags = RREG32_PCIE(MP1_Public |
243 					   (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
244 		break;
245 	default:
246 		mp1_fw_flags = RREG32_PCIE(MP1_Public |
247 					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
248 		break;
249 	}
250 
251 	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
252 	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
253 		return 0;
254 
255 	return -EIO;
256 }
257 
smu_v13_0_check_fw_version(struct smu_context * smu)258 int smu_v13_0_check_fw_version(struct smu_context *smu)
259 {
260 	struct amdgpu_device *adev = smu->adev;
261 	uint32_t if_version = 0xff, smu_version = 0xff;
262 	uint8_t smu_program, smu_major, smu_minor, smu_debug;
263 	int ret = 0;
264 
265 	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
266 	if (ret)
267 		return ret;
268 
269 	smu_program = (smu_version >> 24) & 0xff;
270 	smu_major = (smu_version >> 16) & 0xff;
271 	smu_minor = (smu_version >> 8) & 0xff;
272 	smu_debug = (smu_version >> 0) & 0xff;
273 	if (smu->is_apu ||
274 	    amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6))
275 		adev->pm.fw_version = smu_version;
276 
277 	/* only for dGPU w/ SMU13*/
278 	if (adev->pm.fw)
279 		dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
280 			 smu_program, smu_version, smu_major, smu_minor, smu_debug);
281 
282 	/*
283 	 * 1. if_version mismatch is not critical as our fw is designed
284 	 * to be backward compatible.
285 	 * 2. New fw usually brings some optimizations. But that's visible
286 	 * only on the paired driver.
287 	 * Considering above, we just leave user a verbal message instead
288 	 * of halt driver loading.
289 	 */
290 	if (if_version != smu->smc_driver_if_version) {
291 		dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
292 			 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
293 			 smu->smc_driver_if_version, if_version,
294 			 smu_program, smu_version, smu_major, smu_minor, smu_debug);
295 		dev_info(adev->dev, "SMU driver if version not matched\n");
296 	}
297 
298 	return ret;
299 }
300 
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)301 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
302 {
303 	struct amdgpu_device *adev = smu->adev;
304 	uint32_t ppt_offset_bytes;
305 	const struct smc_firmware_header_v2_0 *v2;
306 
307 	v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
308 
309 	ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
310 	*size = le32_to_cpu(v2->ppt_size_bytes);
311 	*table = (uint8_t *)v2 + ppt_offset_bytes;
312 
313 	return 0;
314 }
315 
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)316 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
317 				      uint32_t *size, uint32_t pptable_id)
318 {
319 	struct amdgpu_device *adev = smu->adev;
320 	const struct smc_firmware_header_v2_1 *v2_1;
321 	struct smc_soft_pptable_entry *entries;
322 	uint32_t pptable_count = 0;
323 	int i = 0;
324 
325 	v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
326 	entries = (struct smc_soft_pptable_entry *)
327 		((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
328 	pptable_count = le32_to_cpu(v2_1->pptable_count);
329 	for (i = 0; i < pptable_count; i++) {
330 		if (le32_to_cpu(entries[i].id) == pptable_id) {
331 			*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
332 			*size = le32_to_cpu(entries[i].ppt_size_bytes);
333 			break;
334 		}
335 	}
336 
337 	if (i == pptable_count)
338 		return -EINVAL;
339 
340 	return 0;
341 }
342 
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)343 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
344 {
345 	struct amdgpu_device *adev = smu->adev;
346 	uint16_t atom_table_size;
347 	uint8_t frev, crev;
348 	int ret, index;
349 
350 	dev_info(adev->dev, "use vbios provided pptable\n");
351 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
352 					    powerplayinfo);
353 
354 	ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
355 					     (uint8_t **)table);
356 	if (ret)
357 		return ret;
358 
359 	if (size)
360 		*size = atom_table_size;
361 
362 	return 0;
363 }
364 
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)365 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
366 					void **table,
367 					uint32_t *size,
368 					uint32_t pptable_id)
369 {
370 	const struct smc_firmware_header_v1_0 *hdr;
371 	struct amdgpu_device *adev = smu->adev;
372 	uint16_t version_major, version_minor;
373 	int ret;
374 
375 	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
376 	if (!hdr)
377 		return -EINVAL;
378 
379 	dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
380 
381 	version_major = le16_to_cpu(hdr->header.header_version_major);
382 	version_minor = le16_to_cpu(hdr->header.header_version_minor);
383 	if (version_major != 2) {
384 		dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
385 			version_major, version_minor);
386 		return -EINVAL;
387 	}
388 
389 	switch (version_minor) {
390 	case 0:
391 		ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
392 		break;
393 	case 1:
394 		ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
395 		break;
396 	default:
397 		ret = -EINVAL;
398 		break;
399 	}
400 
401 	return ret;
402 }
403 
smu_v13_0_setup_pptable(struct smu_context * smu)404 int smu_v13_0_setup_pptable(struct smu_context *smu)
405 {
406 	struct amdgpu_device *adev = smu->adev;
407 	uint32_t size = 0, pptable_id = 0;
408 	void *table;
409 	int ret = 0;
410 
411 	/* override pptable_id from driver parameter */
412 	if (amdgpu_smu_pptable_id >= 0) {
413 		pptable_id = amdgpu_smu_pptable_id;
414 		dev_info(adev->dev, "override pptable id %d\n", pptable_id);
415 	} else {
416 		pptable_id = smu->smu_table.boot_values.pp_table_id;
417 	}
418 
419 	/* force using vbios pptable in sriov mode */
420 	if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
421 		ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
422 	else
423 		ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
424 
425 	if (ret)
426 		return ret;
427 
428 	if (!smu->smu_table.power_play_table)
429 		smu->smu_table.power_play_table = table;
430 	if (!smu->smu_table.power_play_table_size)
431 		smu->smu_table.power_play_table_size = size;
432 
433 	return 0;
434 }
435 
smu_v13_0_init_smc_tables(struct smu_context * smu)436 int smu_v13_0_init_smc_tables(struct smu_context *smu)
437 {
438 	struct smu_table_context *smu_table = &smu->smu_table;
439 	struct smu_table *tables = smu_table->tables;
440 	int ret = 0;
441 
442 	smu_table->driver_pptable =
443 		kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
444 	if (!smu_table->driver_pptable) {
445 		ret = -ENOMEM;
446 		goto err0_out;
447 	}
448 
449 	smu_table->max_sustainable_clocks =
450 		kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
451 	if (!smu_table->max_sustainable_clocks) {
452 		ret = -ENOMEM;
453 		goto err1_out;
454 	}
455 
456 	/* Aldebaran does not support OVERDRIVE */
457 	if (tables[SMU_TABLE_OVERDRIVE].size) {
458 		smu_table->overdrive_table =
459 			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
460 		if (!smu_table->overdrive_table) {
461 			ret = -ENOMEM;
462 			goto err2_out;
463 		}
464 
465 		smu_table->boot_overdrive_table =
466 			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
467 		if (!smu_table->boot_overdrive_table) {
468 			ret = -ENOMEM;
469 			goto err3_out;
470 		}
471 
472 		smu_table->user_overdrive_table =
473 			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
474 		if (!smu_table->user_overdrive_table) {
475 			ret = -ENOMEM;
476 			goto err4_out;
477 		}
478 	}
479 
480 	smu_table->combo_pptable =
481 		kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
482 	if (!smu_table->combo_pptable) {
483 		ret = -ENOMEM;
484 		goto err5_out;
485 	}
486 
487 	return 0;
488 
489 err5_out:
490 	kfree(smu_table->user_overdrive_table);
491 err4_out:
492 	kfree(smu_table->boot_overdrive_table);
493 err3_out:
494 	kfree(smu_table->overdrive_table);
495 err2_out:
496 	kfree(smu_table->max_sustainable_clocks);
497 err1_out:
498 	kfree(smu_table->driver_pptable);
499 err0_out:
500 	return ret;
501 }
502 
smu_v13_0_fini_smc_tables(struct smu_context * smu)503 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
504 {
505 	struct smu_table_context *smu_table = &smu->smu_table;
506 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
507 
508 	kfree(smu_table->gpu_metrics_table);
509 	kfree(smu_table->combo_pptable);
510 	kfree(smu_table->user_overdrive_table);
511 	kfree(smu_table->boot_overdrive_table);
512 	kfree(smu_table->overdrive_table);
513 	kfree(smu_table->max_sustainable_clocks);
514 	kfree(smu_table->driver_pptable);
515 	smu_table->gpu_metrics_table = NULL;
516 	smu_table->combo_pptable = NULL;
517 	smu_table->user_overdrive_table = NULL;
518 	smu_table->boot_overdrive_table = NULL;
519 	smu_table->overdrive_table = NULL;
520 	smu_table->max_sustainable_clocks = NULL;
521 	smu_table->driver_pptable = NULL;
522 	kfree(smu_table->hardcode_pptable);
523 	smu_table->hardcode_pptable = NULL;
524 
525 	kfree(smu_table->ecc_table);
526 	kfree(smu_table->metrics_table);
527 	kfree(smu_table->watermarks_table);
528 	smu_table->ecc_table = NULL;
529 	smu_table->metrics_table = NULL;
530 	smu_table->watermarks_table = NULL;
531 	smu_table->metrics_time = 0;
532 
533 	kfree(smu_dpm->dpm_context);
534 	kfree(smu_dpm->golden_dpm_context);
535 	kfree(smu_dpm->dpm_current_power_state);
536 	kfree(smu_dpm->dpm_request_power_state);
537 	smu_dpm->dpm_context = NULL;
538 	smu_dpm->golden_dpm_context = NULL;
539 	smu_dpm->dpm_context_size = 0;
540 	smu_dpm->dpm_current_power_state = NULL;
541 	smu_dpm->dpm_request_power_state = NULL;
542 
543 	return 0;
544 }
545 
smu_v13_0_init_power(struct smu_context * smu)546 int smu_v13_0_init_power(struct smu_context *smu)
547 {
548 	struct smu_power_context *smu_power = &smu->smu_power;
549 
550 	if (smu_power->power_context || smu_power->power_context_size != 0)
551 		return -EINVAL;
552 
553 	smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
554 					   GFP_KERNEL);
555 	if (!smu_power->power_context)
556 		return -ENOMEM;
557 	smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
558 
559 	return 0;
560 }
561 
smu_v13_0_fini_power(struct smu_context * smu)562 int smu_v13_0_fini_power(struct smu_context *smu)
563 {
564 	struct smu_power_context *smu_power = &smu->smu_power;
565 
566 	if (!smu_power->power_context || smu_power->power_context_size == 0)
567 		return -EINVAL;
568 
569 	kfree(smu_power->power_context);
570 	smu_power->power_context = NULL;
571 	smu_power->power_context_size = 0;
572 
573 	return 0;
574 }
575 
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)576 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
577 {
578 	int ret, index;
579 	uint16_t size;
580 	uint8_t frev, crev;
581 	struct atom_common_table_header *header;
582 	struct atom_firmware_info_v3_4 *v_3_4;
583 	struct atom_firmware_info_v3_3 *v_3_3;
584 	struct atom_firmware_info_v3_1 *v_3_1;
585 	struct atom_smu_info_v3_6 *smu_info_v3_6;
586 	struct atom_smu_info_v4_0 *smu_info_v4_0;
587 
588 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
589 					    firmwareinfo);
590 
591 	ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
592 					     (uint8_t **)&header);
593 	if (ret)
594 		return ret;
595 
596 	if (header->format_revision != 3) {
597 		dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
598 		return -EINVAL;
599 	}
600 
601 	switch (header->content_revision) {
602 	case 0:
603 	case 1:
604 	case 2:
605 		v_3_1 = (struct atom_firmware_info_v3_1 *)header;
606 		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
607 		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
608 		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
609 		smu->smu_table.boot_values.socclk = 0;
610 		smu->smu_table.boot_values.dcefclk = 0;
611 		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
612 		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
613 		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
614 		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
615 		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
616 		smu->smu_table.boot_values.pp_table_id = 0;
617 		break;
618 	case 3:
619 		v_3_3 = (struct atom_firmware_info_v3_3 *)header;
620 		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
621 		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
622 		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
623 		smu->smu_table.boot_values.socclk = 0;
624 		smu->smu_table.boot_values.dcefclk = 0;
625 		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
626 		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
627 		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
628 		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
629 		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
630 		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
631 		break;
632 	case 4:
633 	default:
634 		v_3_4 = (struct atom_firmware_info_v3_4 *)header;
635 		smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
636 		smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
637 		smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
638 		smu->smu_table.boot_values.socclk = 0;
639 		smu->smu_table.boot_values.dcefclk = 0;
640 		smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
641 		smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
642 		smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
643 		smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
644 		smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
645 		smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
646 		break;
647 	}
648 
649 	smu->smu_table.boot_values.format_revision = header->format_revision;
650 	smu->smu_table.boot_values.content_revision = header->content_revision;
651 
652 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
653 					    smu_info);
654 	if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
655 					    (uint8_t **)&header)) {
656 
657 		if ((frev == 3) && (crev == 6)) {
658 			smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
659 
660 			smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
661 			smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
662 			smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
663 			smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
664 		} else if ((frev == 3) && (crev == 1)) {
665 			return 0;
666 		} else if ((frev == 4) && (crev == 0)) {
667 			smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
668 
669 			smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
670 			smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
671 			smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
672 			smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
673 			smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
674 		} else {
675 			dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
676 						(uint32_t)frev, (uint32_t)crev);
677 		}
678 	}
679 
680 	return 0;
681 }
682 
683 
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)684 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
685 {
686 	struct smu_table_context *smu_table = &smu->smu_table;
687 	struct smu_table *memory_pool = &smu_table->memory_pool;
688 	int ret = 0;
689 	uint64_t address;
690 	uint32_t address_low, address_high;
691 
692 	if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
693 		return ret;
694 
695 	address = memory_pool->mc_address;
696 	address_high = (uint32_t)upper_32_bits(address);
697 	address_low  = (uint32_t)lower_32_bits(address);
698 
699 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
700 					      address_high, NULL);
701 	if (ret)
702 		return ret;
703 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
704 					      address_low, NULL);
705 	if (ret)
706 		return ret;
707 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
708 					      (uint32_t)memory_pool->size, NULL);
709 	if (ret)
710 		return ret;
711 
712 	return ret;
713 }
714 
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)715 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
716 {
717 	int ret;
718 
719 	ret = smu_cmn_send_smc_msg_with_param(smu,
720 					      SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
721 	if (ret)
722 		dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
723 
724 	return ret;
725 }
726 
smu_v13_0_set_driver_table_location(struct smu_context * smu)727 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
728 {
729 	struct smu_table *driver_table = &smu->smu_table.driver_table;
730 	int ret = 0;
731 
732 	if (driver_table->mc_address) {
733 		ret = smu_cmn_send_smc_msg_with_param(smu,
734 						      SMU_MSG_SetDriverDramAddrHigh,
735 						      upper_32_bits(driver_table->mc_address),
736 						      NULL);
737 		if (!ret)
738 			ret = smu_cmn_send_smc_msg_with_param(smu,
739 							      SMU_MSG_SetDriverDramAddrLow,
740 							      lower_32_bits(driver_table->mc_address),
741 							      NULL);
742 	}
743 
744 	return ret;
745 }
746 
smu_v13_0_set_tool_table_location(struct smu_context * smu)747 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
748 {
749 	int ret = 0;
750 	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
751 
752 	if (tool_table->mc_address) {
753 		ret = smu_cmn_send_smc_msg_with_param(smu,
754 						      SMU_MSG_SetToolsDramAddrHigh,
755 						      upper_32_bits(tool_table->mc_address),
756 						      NULL);
757 		if (!ret)
758 			ret = smu_cmn_send_smc_msg_with_param(smu,
759 							      SMU_MSG_SetToolsDramAddrLow,
760 							      lower_32_bits(tool_table->mc_address),
761 							      NULL);
762 	}
763 
764 	return ret;
765 }
766 
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)767 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
768 {
769 	int ret = 0;
770 
771 	if (!smu->pm_enabled)
772 		return ret;
773 
774 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
775 
776 	return ret;
777 }
778 
smu_v13_0_set_allowed_mask(struct smu_context * smu)779 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
780 {
781 	struct smu_feature *feature = &smu->smu_feature;
782 	int ret = 0;
783 	uint32_t feature_mask[2];
784 
785 	if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
786 	    feature->feature_num < 64)
787 		return -EINVAL;
788 
789 	bitmap_to_arr32(feature_mask, feature->allowed, 64);
790 
791 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
792 					      feature_mask[1], NULL);
793 	if (ret)
794 		return ret;
795 
796 	return smu_cmn_send_smc_msg_with_param(smu,
797 					       SMU_MSG_SetAllowedFeaturesMaskLow,
798 					       feature_mask[0],
799 					       NULL);
800 }
801 
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)802 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
803 {
804 	int ret = 0;
805 	struct amdgpu_device *adev = smu->adev;
806 
807 	switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
808 	case IP_VERSION(13, 0, 0):
809 	case IP_VERSION(13, 0, 1):
810 	case IP_VERSION(13, 0, 3):
811 	case IP_VERSION(13, 0, 4):
812 	case IP_VERSION(13, 0, 5):
813 	case IP_VERSION(13, 0, 7):
814 	case IP_VERSION(13, 0, 8):
815 	case IP_VERSION(13, 0, 10):
816 	case IP_VERSION(13, 0, 11):
817 		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
818 			return 0;
819 		if (enable)
820 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
821 		else
822 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
823 		break;
824 	default:
825 		break;
826 	}
827 
828 	return ret;
829 }
830 
smu_v13_0_system_features_control(struct smu_context * smu,bool en)831 int smu_v13_0_system_features_control(struct smu_context *smu,
832 				      bool en)
833 {
834 	return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
835 					  SMU_MSG_DisableAllSmuFeatures), NULL);
836 }
837 
smu_v13_0_notify_display_change(struct smu_context * smu)838 int smu_v13_0_notify_display_change(struct smu_context *smu)
839 {
840 	int ret = 0;
841 
842 	if (!amdgpu_device_has_dc_support(smu->adev))
843 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DALNotPresent, NULL);
844 
845 	return ret;
846 }
847 
848 	static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)849 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
850 				    enum smu_clk_type clock_select)
851 {
852 	int ret = 0;
853 	int clk_id;
854 
855 	if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
856 	    (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
857 		return 0;
858 
859 	clk_id = smu_cmn_to_asic_specific_index(smu,
860 						CMN2ASIC_MAPPING_CLK,
861 						clock_select);
862 	if (clk_id < 0)
863 		return -EINVAL;
864 
865 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
866 					      clk_id << 16, clock);
867 	if (ret) {
868 		dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
869 		return ret;
870 	}
871 
872 	if (*clock != 0)
873 		return 0;
874 
875 	/* if DC limit is zero, return AC limit */
876 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
877 					      clk_id << 16, clock);
878 	if (ret) {
879 		dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
880 		return ret;
881 	}
882 
883 	return 0;
884 }
885 
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)886 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
887 {
888 	struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
889 		smu->smu_table.max_sustainable_clocks;
890 	int ret = 0;
891 
892 	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
893 	max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
894 	max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
895 	max_sustainable_clocks->display_clock = 0xFFFFFFFF;
896 	max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
897 	max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
898 
899 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
900 		ret = smu_v13_0_get_max_sustainable_clock(smu,
901 							  &(max_sustainable_clocks->uclock),
902 							  SMU_UCLK);
903 		if (ret) {
904 			dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
905 				__func__);
906 			return ret;
907 		}
908 	}
909 
910 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
911 		ret = smu_v13_0_get_max_sustainable_clock(smu,
912 							  &(max_sustainable_clocks->soc_clock),
913 							  SMU_SOCCLK);
914 		if (ret) {
915 			dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
916 				__func__);
917 			return ret;
918 		}
919 	}
920 
921 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
922 		ret = smu_v13_0_get_max_sustainable_clock(smu,
923 							  &(max_sustainable_clocks->dcef_clock),
924 							  SMU_DCEFCLK);
925 		if (ret) {
926 			dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
927 				__func__);
928 			return ret;
929 		}
930 
931 		ret = smu_v13_0_get_max_sustainable_clock(smu,
932 							  &(max_sustainable_clocks->display_clock),
933 							  SMU_DISPCLK);
934 		if (ret) {
935 			dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
936 				__func__);
937 			return ret;
938 		}
939 		ret = smu_v13_0_get_max_sustainable_clock(smu,
940 							  &(max_sustainable_clocks->phy_clock),
941 							  SMU_PHYCLK);
942 		if (ret) {
943 			dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
944 				__func__);
945 			return ret;
946 		}
947 		ret = smu_v13_0_get_max_sustainable_clock(smu,
948 							  &(max_sustainable_clocks->pixel_clock),
949 							  SMU_PIXCLK);
950 		if (ret) {
951 			dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
952 				__func__);
953 			return ret;
954 		}
955 	}
956 
957 	if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
958 		max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
959 
960 	return 0;
961 }
962 
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)963 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
964 				      uint32_t *power_limit)
965 {
966 	int power_src;
967 	int ret = 0;
968 
969 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
970 		return -EINVAL;
971 
972 	power_src = smu_cmn_to_asic_specific_index(smu,
973 						   CMN2ASIC_MAPPING_PWR,
974 						   smu->adev->pm.ac_power ?
975 						   SMU_POWER_SOURCE_AC :
976 						   SMU_POWER_SOURCE_DC);
977 	if (power_src < 0)
978 		return -EINVAL;
979 
980 	ret = smu_cmn_send_smc_msg_with_param(smu,
981 					      SMU_MSG_GetPptLimit,
982 					      power_src << 16,
983 					      power_limit);
984 	if (ret)
985 		dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
986 
987 	return ret;
988 }
989 
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)990 int smu_v13_0_set_power_limit(struct smu_context *smu,
991 			      enum smu_ppt_limit_type limit_type,
992 			      uint32_t limit)
993 {
994 	int ret = 0;
995 
996 	if (limit_type != SMU_DEFAULT_PPT_LIMIT)
997 		return -EINVAL;
998 
999 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1000 		dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1001 		return -EOPNOTSUPP;
1002 	}
1003 
1004 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1005 	if (ret) {
1006 		dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1007 		return ret;
1008 	}
1009 
1010 	smu->current_power_limit = limit;
1011 
1012 	return 0;
1013 }
1014 
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)1015 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1016 {
1017 	return smu_cmn_send_smc_msg(smu,
1018 				    SMU_MSG_AllowIHHostInterrupt,
1019 				    NULL);
1020 }
1021 
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1022 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1023 {
1024 	int ret = 0;
1025 
1026 	if (smu->dc_controlled_by_gpio &&
1027 	    smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1028 		ret = smu_v13_0_allow_ih_interrupt(smu);
1029 
1030 	return ret;
1031 }
1032 
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1033 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1034 {
1035 	int ret = 0;
1036 
1037 	if (!smu->irq_source.num_types)
1038 		return 0;
1039 
1040 	ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1041 	if (ret)
1042 		return ret;
1043 
1044 	return smu_v13_0_process_pending_interrupt(smu);
1045 }
1046 
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1047 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1048 {
1049 	if (!smu->irq_source.num_types)
1050 		return 0;
1051 
1052 	return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1053 }
1054 
convert_to_vddc(uint8_t vid)1055 static uint16_t convert_to_vddc(uint8_t vid)
1056 {
1057 	return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1058 }
1059 
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1060 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1061 {
1062 	struct amdgpu_device *adev = smu->adev;
1063 	uint32_t vdd = 0, val_vid = 0;
1064 
1065 	if (!value)
1066 		return -EINVAL;
1067 	val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1068 		   SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1069 		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1070 
1071 	vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1072 
1073 	*value = vdd;
1074 
1075 	return 0;
1076 
1077 }
1078 
1079 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1080 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1081 					struct pp_display_clock_request
1082 					*clock_req)
1083 {
1084 	enum amd_pp_clock_type clk_type = clock_req->clock_type;
1085 	int ret = 0;
1086 	enum smu_clk_type clk_select = 0;
1087 	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1088 
1089 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1090 	    smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1091 		switch (clk_type) {
1092 		case amd_pp_dcef_clock:
1093 			clk_select = SMU_DCEFCLK;
1094 			break;
1095 		case amd_pp_disp_clock:
1096 			clk_select = SMU_DISPCLK;
1097 			break;
1098 		case amd_pp_pixel_clock:
1099 			clk_select = SMU_PIXCLK;
1100 			break;
1101 		case amd_pp_phy_clock:
1102 			clk_select = SMU_PHYCLK;
1103 			break;
1104 		case amd_pp_mem_clock:
1105 			clk_select = SMU_UCLK;
1106 			break;
1107 		default:
1108 			dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1109 			ret = -EINVAL;
1110 			break;
1111 		}
1112 
1113 		if (ret)
1114 			goto failed;
1115 
1116 		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1117 			return 0;
1118 
1119 		ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1120 
1121 		if (clk_select == SMU_UCLK)
1122 			smu->hard_min_uclk_req_from_dal = clk_freq;
1123 	}
1124 
1125 failed:
1126 	return ret;
1127 }
1128 
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1129 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1130 {
1131 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1132 		return AMD_FAN_CTRL_MANUAL;
1133 	else
1134 		return AMD_FAN_CTRL_AUTO;
1135 }
1136 
1137 	static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1138 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1139 {
1140 	int ret = 0;
1141 
1142 	if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1143 		return 0;
1144 
1145 	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1146 	if (ret)
1147 		dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1148 			__func__, (auto_fan_control ? "Start" : "Stop"));
1149 
1150 	return ret;
1151 }
1152 
1153 	static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1154 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1155 {
1156 	struct amdgpu_device *adev = smu->adev;
1157 
1158 	WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1159 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1160 				   CG_FDO_CTRL2, TMIN, 0));
1161 	WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1162 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1163 				   CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1164 
1165 	return 0;
1166 }
1167 
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1168 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1169 				uint32_t speed)
1170 {
1171 	struct amdgpu_device *adev = smu->adev;
1172 	uint32_t duty100, duty;
1173 	uint64_t tmp64;
1174 
1175 	speed = min_t(uint32_t, speed, 255);
1176 
1177 	if (smu_v13_0_auto_fan_control(smu, 0))
1178 		return -EINVAL;
1179 
1180 	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1181 				CG_FDO_CTRL1, FMAX_DUTY100);
1182 	if (!duty100)
1183 		return -EINVAL;
1184 
1185 	tmp64 = (uint64_t)speed * duty100;
1186 	do_div(tmp64, 255);
1187 	duty = (uint32_t)tmp64;
1188 
1189 	WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1190 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1191 				   CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1192 
1193 	return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1194 }
1195 
1196 	int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1197 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1198 			       uint32_t mode)
1199 {
1200 	int ret = 0;
1201 
1202 	switch (mode) {
1203 	case AMD_FAN_CTRL_NONE:
1204 		ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1205 		break;
1206 	case AMD_FAN_CTRL_MANUAL:
1207 		ret = smu_v13_0_auto_fan_control(smu, 0);
1208 		break;
1209 	case AMD_FAN_CTRL_AUTO:
1210 		ret = smu_v13_0_auto_fan_control(smu, 1);
1211 		break;
1212 	default:
1213 		break;
1214 	}
1215 
1216 	if (ret) {
1217 		dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1218 		return -EINVAL;
1219 	}
1220 
1221 	return ret;
1222 }
1223 
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1224 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1225 				uint32_t speed)
1226 {
1227 	struct amdgpu_device *adev = smu->adev;
1228 	uint32_t crystal_clock_freq = 2500;
1229 	uint32_t tach_period;
1230 	int ret;
1231 
1232 	if (!speed)
1233 		return -EINVAL;
1234 
1235 	ret = smu_v13_0_auto_fan_control(smu, 0);
1236 	if (ret)
1237 		return ret;
1238 
1239 	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1240 	WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1241 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1242 				   CG_TACH_CTRL, TARGET_PERIOD,
1243 				   tach_period));
1244 
1245 	return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1246 }
1247 
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1248 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1249 			      uint32_t pstate)
1250 {
1251 	int ret = 0;
1252 	ret = smu_cmn_send_smc_msg_with_param(smu,
1253 					      SMU_MSG_SetXgmiMode,
1254 					      pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1255 					      NULL);
1256 	return ret;
1257 }
1258 
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1259 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1260 				   struct amdgpu_irq_src *source,
1261 				   unsigned tyep,
1262 				   enum amdgpu_interrupt_state state)
1263 {
1264 	struct smu_context *smu = adev->powerplay.pp_handle;
1265 	uint32_t low, high;
1266 	uint32_t val = 0;
1267 
1268 	switch (state) {
1269 	case AMDGPU_IRQ_STATE_DISABLE:
1270 		/* For THM irqs */
1271 		val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1272 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1273 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1274 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1275 
1276 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1277 
1278 		/* For MP1 SW irqs */
1279 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1280 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1281 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1282 
1283 		break;
1284 	case AMDGPU_IRQ_STATE_ENABLE:
1285 		/* For THM irqs */
1286 		low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1287 			  smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1288 		high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1289 			   smu->thermal_range.software_shutdown_temp);
1290 
1291 		val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1292 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1293 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1294 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1295 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1296 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1297 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1298 		val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1299 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1300 
1301 		val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1302 		val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1303 		val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1304 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1305 
1306 		/* For MP1 SW irqs */
1307 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1308 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1309 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1310 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1311 
1312 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1313 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1314 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1315 
1316 		break;
1317 	default:
1318 		break;
1319 	}
1320 
1321 	return 0;
1322 }
1323 
smu_v13_0_ack_ac_dc_interrupt(struct smu_context * smu)1324 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1325 {
1326 	return smu_cmn_send_smc_msg(smu,
1327 				    SMU_MSG_ReenableAcDcInterrupt,
1328 				    NULL);
1329 }
1330 
1331 #define THM_11_0__SRCID__THM_DIG_THERM_L2H		0		/* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1332 #define THM_11_0__SRCID__THM_DIG_THERM_H2L		1		/* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1333 #define SMUIO_11_0__SRCID__SMUIO_GPIO19			83
1334 
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1335 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1336 				 struct amdgpu_irq_src *source,
1337 				 struct amdgpu_iv_entry *entry)
1338 {
1339 	struct smu_context *smu = adev->powerplay.pp_handle;
1340 	uint32_t client_id = entry->client_id;
1341 	uint32_t src_id = entry->src_id;
1342 	/*
1343 	 * ctxid is used to distinguish different
1344 	 * events for SMCToHost interrupt.
1345 	 */
1346 	uint32_t ctxid = entry->src_data[0];
1347 	uint32_t data;
1348 	uint32_t high;
1349 
1350 	if (client_id == SOC15_IH_CLIENTID_THM) {
1351 		switch (src_id) {
1352 		case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1353 			schedule_delayed_work(&smu->swctf_delayed_work,
1354 					      msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1355 			break;
1356 		case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1357 			dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1358 			break;
1359 		default:
1360 			dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1361 				  src_id);
1362 			break;
1363 		}
1364 	} else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1365 		dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1366 		/*
1367 		 * HW CTF just occurred. Shutdown to prevent further damage.
1368 		 */
1369 		dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1370 		orderly_poweroff(true);
1371 	} else if (client_id == SOC15_IH_CLIENTID_MP1) {
1372 		if (src_id == 0xfe) {
1373 			/* ACK SMUToHost interrupt */
1374 			data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1375 			data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1376 			WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1377 
1378 			switch (ctxid) {
1379 			case 0x3:
1380 				dev_dbg(adev->dev, "Switched to AC mode!\n");
1381 				smu_v13_0_ack_ac_dc_interrupt(smu);
1382 				adev->pm.ac_power = true;
1383 				break;
1384 			case 0x4:
1385 				dev_dbg(adev->dev, "Switched to DC mode!\n");
1386 				smu_v13_0_ack_ac_dc_interrupt(smu);
1387 				adev->pm.ac_power = false;
1388 				break;
1389 			case 0x7:
1390 				/*
1391 				 * Increment the throttle interrupt counter
1392 				 */
1393 				atomic64_inc(&smu->throttle_int_counter);
1394 
1395 				if (!atomic_read(&adev->throttling_logging_enabled))
1396 					return 0;
1397 
1398 				if (__ratelimit(&adev->throttling_logging_rs))
1399 					schedule_work(&smu->throttling_logging_work);
1400 
1401 				break;
1402 			case 0x8:
1403 				high = smu->thermal_range.software_shutdown_temp +
1404 					smu->thermal_range.software_shutdown_temp_offset;
1405 				high = min_t(typeof(high),
1406 					     SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1407 					     high);
1408 				dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1409 							high,
1410 							smu->thermal_range.software_shutdown_temp_offset);
1411 
1412 				data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1413 				data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1414 							DIG_THERM_INTH,
1415 							(high & 0xff));
1416 				data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1417 				WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1418 				break;
1419 			case 0x9:
1420 				high = min_t(typeof(high),
1421 					     SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1422 					     smu->thermal_range.software_shutdown_temp);
1423 				dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1424 
1425 				data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1426 				data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1427 							DIG_THERM_INTH,
1428 							(high & 0xff));
1429 				data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1430 				WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1431 				break;
1432 			}
1433 		}
1434 	}
1435 
1436 	return 0;
1437 }
1438 
1439 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1440 	.set = smu_v13_0_set_irq_state,
1441 	.process = smu_v13_0_irq_process,
1442 };
1443 
smu_v13_0_register_irq_handler(struct smu_context * smu)1444 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1445 {
1446 	struct amdgpu_device *adev = smu->adev;
1447 	struct amdgpu_irq_src *irq_src = &smu->irq_source;
1448 	int ret = 0;
1449 
1450 	if (amdgpu_sriov_vf(adev))
1451 		return 0;
1452 
1453 	irq_src->num_types = 1;
1454 	irq_src->funcs = &smu_v13_0_irq_funcs;
1455 
1456 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1457 				THM_11_0__SRCID__THM_DIG_THERM_L2H,
1458 				irq_src);
1459 	if (ret)
1460 		return ret;
1461 
1462 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1463 				THM_11_0__SRCID__THM_DIG_THERM_H2L,
1464 				irq_src);
1465 	if (ret)
1466 		return ret;
1467 
1468 	/* Register CTF(GPIO_19) interrupt */
1469 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1470 				SMUIO_11_0__SRCID__SMUIO_GPIO19,
1471 				irq_src);
1472 	if (ret)
1473 		return ret;
1474 
1475 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1476 				0xfe,
1477 				irq_src);
1478 	if (ret)
1479 		return ret;
1480 
1481 	return ret;
1482 }
1483 
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1484 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1485 					       struct pp_smu_nv_clock_table *max_clocks)
1486 {
1487 	struct smu_table_context *table_context = &smu->smu_table;
1488 	struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1489 
1490 	if (!max_clocks || !table_context->max_sustainable_clocks)
1491 		return -EINVAL;
1492 
1493 	sustainable_clocks = table_context->max_sustainable_clocks;
1494 
1495 	max_clocks->dcfClockInKhz =
1496 		(unsigned int) sustainable_clocks->dcef_clock * 1000;
1497 	max_clocks->displayClockInKhz =
1498 		(unsigned int) sustainable_clocks->display_clock * 1000;
1499 	max_clocks->phyClockInKhz =
1500 		(unsigned int) sustainable_clocks->phy_clock * 1000;
1501 	max_clocks->pixelClockInKhz =
1502 		(unsigned int) sustainable_clocks->pixel_clock * 1000;
1503 	max_clocks->uClockInKhz =
1504 		(unsigned int) sustainable_clocks->uclock * 1000;
1505 	max_clocks->socClockInKhz =
1506 		(unsigned int) sustainable_clocks->soc_clock * 1000;
1507 	max_clocks->dscClockInKhz = 0;
1508 	max_clocks->dppClockInKhz = 0;
1509 	max_clocks->fabricClockInKhz = 0;
1510 
1511 	return 0;
1512 }
1513 
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1514 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1515 {
1516 	int ret = 0;
1517 
1518 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1519 
1520 	return ret;
1521 }
1522 
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1523 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1524 					     uint64_t event_arg)
1525 {
1526 	int ret = 0;
1527 
1528 	dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1529 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1530 
1531 	return ret;
1532 }
1533 
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1534 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1535 			     uint64_t event_arg)
1536 {
1537 	int ret = -EINVAL;
1538 
1539 	switch (event) {
1540 	case SMU_EVENT_RESET_COMPLETE:
1541 		ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1542 		break;
1543 	default:
1544 		break;
1545 	}
1546 
1547 	return ret;
1548 }
1549 
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1550 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1551 				    uint32_t *min, uint32_t *max)
1552 {
1553 	int ret = 0, clk_id = 0;
1554 	uint32_t param = 0;
1555 	uint32_t clock_limit;
1556 
1557 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1558 		switch (clk_type) {
1559 		case SMU_MCLK:
1560 		case SMU_UCLK:
1561 			clock_limit = smu->smu_table.boot_values.uclk;
1562 			break;
1563 		case SMU_GFXCLK:
1564 		case SMU_SCLK:
1565 			clock_limit = smu->smu_table.boot_values.gfxclk;
1566 			break;
1567 		case SMU_SOCCLK:
1568 			clock_limit = smu->smu_table.boot_values.socclk;
1569 			break;
1570 		default:
1571 			clock_limit = 0;
1572 			break;
1573 		}
1574 
1575 		/* clock in Mhz unit */
1576 		if (min)
1577 			*min = clock_limit / 100;
1578 		if (max)
1579 			*max = clock_limit / 100;
1580 
1581 		return 0;
1582 	}
1583 
1584 	clk_id = smu_cmn_to_asic_specific_index(smu,
1585 						CMN2ASIC_MAPPING_CLK,
1586 						clk_type);
1587 	if (clk_id < 0) {
1588 		ret = -EINVAL;
1589 		goto failed;
1590 	}
1591 	param = (clk_id & 0xffff) << 16;
1592 
1593 	if (max) {
1594 		if (smu->adev->pm.ac_power)
1595 			ret = smu_cmn_send_smc_msg_with_param(smu,
1596 							      SMU_MSG_GetMaxDpmFreq,
1597 							      param,
1598 							      max);
1599 		else
1600 			ret = smu_cmn_send_smc_msg_with_param(smu,
1601 							      SMU_MSG_GetDcModeMaxDpmFreq,
1602 							      param,
1603 							      max);
1604 		if (ret)
1605 			goto failed;
1606 	}
1607 
1608 	if (min) {
1609 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1610 		if (ret)
1611 			goto failed;
1612 	}
1613 
1614 failed:
1615 	return ret;
1616 }
1617 
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1618 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1619 					  enum smu_clk_type clk_type,
1620 					  uint32_t min,
1621 					  uint32_t max)
1622 {
1623 	int ret = 0, clk_id = 0;
1624 	uint32_t param;
1625 
1626 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1627 		return 0;
1628 
1629 	clk_id = smu_cmn_to_asic_specific_index(smu,
1630 						CMN2ASIC_MAPPING_CLK,
1631 						clk_type);
1632 	if (clk_id < 0)
1633 		return clk_id;
1634 
1635 	if (max > 0) {
1636 		param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1637 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1638 						      param, NULL);
1639 		if (ret)
1640 			goto out;
1641 	}
1642 
1643 	if (min > 0) {
1644 		param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1645 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1646 						      param, NULL);
1647 		if (ret)
1648 			goto out;
1649 	}
1650 
1651 out:
1652 	return ret;
1653 }
1654 
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1655 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1656 					  enum smu_clk_type clk_type,
1657 					  uint32_t min,
1658 					  uint32_t max)
1659 {
1660 	int ret = 0, clk_id = 0;
1661 	uint32_t param;
1662 
1663 	if (min <= 0 && max <= 0)
1664 		return -EINVAL;
1665 
1666 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1667 		return 0;
1668 
1669 	clk_id = smu_cmn_to_asic_specific_index(smu,
1670 						CMN2ASIC_MAPPING_CLK,
1671 						clk_type);
1672 	if (clk_id < 0)
1673 		return clk_id;
1674 
1675 	if (max > 0) {
1676 		param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1677 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1678 						      param, NULL);
1679 		if (ret)
1680 			return ret;
1681 	}
1682 
1683 	if (min > 0) {
1684 		param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1685 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1686 						      param, NULL);
1687 		if (ret)
1688 			return ret;
1689 	}
1690 
1691 	return ret;
1692 }
1693 
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1694 int smu_v13_0_set_performance_level(struct smu_context *smu,
1695 				    enum amd_dpm_forced_level level)
1696 {
1697 	struct smu_13_0_dpm_context *dpm_context =
1698 		smu->smu_dpm.dpm_context;
1699 	struct smu_13_0_dpm_table *gfx_table =
1700 		&dpm_context->dpm_tables.gfx_table;
1701 	struct smu_13_0_dpm_table *mem_table =
1702 		&dpm_context->dpm_tables.uclk_table;
1703 	struct smu_13_0_dpm_table *soc_table =
1704 		&dpm_context->dpm_tables.soc_table;
1705 	struct smu_13_0_dpm_table *vclk_table =
1706 		&dpm_context->dpm_tables.vclk_table;
1707 	struct smu_13_0_dpm_table *dclk_table =
1708 		&dpm_context->dpm_tables.dclk_table;
1709 	struct smu_13_0_dpm_table *fclk_table =
1710 		&dpm_context->dpm_tables.fclk_table;
1711 	struct smu_umd_pstate_table *pstate_table =
1712 		&smu->pstate_table;
1713 	struct amdgpu_device *adev = smu->adev;
1714 	uint32_t sclk_min = 0, sclk_max = 0;
1715 	uint32_t mclk_min = 0, mclk_max = 0;
1716 	uint32_t socclk_min = 0, socclk_max = 0;
1717 	uint32_t vclk_min = 0, vclk_max = 0;
1718 	uint32_t dclk_min = 0, dclk_max = 0;
1719 	uint32_t fclk_min = 0, fclk_max = 0;
1720 	int ret = 0, i;
1721 
1722 	switch (level) {
1723 	case AMD_DPM_FORCED_LEVEL_HIGH:
1724 		sclk_min = sclk_max = gfx_table->max;
1725 		mclk_min = mclk_max = mem_table->max;
1726 		socclk_min = socclk_max = soc_table->max;
1727 		vclk_min = vclk_max = vclk_table->max;
1728 		dclk_min = dclk_max = dclk_table->max;
1729 		fclk_min = fclk_max = fclk_table->max;
1730 		break;
1731 	case AMD_DPM_FORCED_LEVEL_LOW:
1732 		sclk_min = sclk_max = gfx_table->min;
1733 		mclk_min = mclk_max = mem_table->min;
1734 		socclk_min = socclk_max = soc_table->min;
1735 		vclk_min = vclk_max = vclk_table->min;
1736 		dclk_min = dclk_max = dclk_table->min;
1737 		fclk_min = fclk_max = fclk_table->min;
1738 		break;
1739 	case AMD_DPM_FORCED_LEVEL_AUTO:
1740 		sclk_min = gfx_table->min;
1741 		sclk_max = gfx_table->max;
1742 		mclk_min = mem_table->min;
1743 		mclk_max = mem_table->max;
1744 		socclk_min = soc_table->min;
1745 		socclk_max = soc_table->max;
1746 		vclk_min = vclk_table->min;
1747 		vclk_max = vclk_table->max;
1748 		dclk_min = dclk_table->min;
1749 		dclk_max = dclk_table->max;
1750 		fclk_min = fclk_table->min;
1751 		fclk_max = fclk_table->max;
1752 		break;
1753 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1754 		sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1755 		mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1756 		socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1757 		vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1758 		dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1759 		fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1760 		break;
1761 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1762 		sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1763 		break;
1764 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1765 		mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1766 		break;
1767 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1768 		sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1769 		mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1770 		socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1771 		vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1772 		dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1773 		fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1774 		break;
1775 	case AMD_DPM_FORCED_LEVEL_MANUAL:
1776 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1777 		return 0;
1778 	default:
1779 		dev_err(adev->dev, "Invalid performance level %d\n", level);
1780 		return -EINVAL;
1781 	}
1782 
1783 	/*
1784 	 * Unset those settings for SMU 13.0.2. As soft limits settings
1785 	 * for those clock domains are not supported.
1786 	 */
1787 	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) {
1788 		mclk_min = mclk_max = 0;
1789 		socclk_min = socclk_max = 0;
1790 		vclk_min = vclk_max = 0;
1791 		dclk_min = dclk_max = 0;
1792 		fclk_min = fclk_max = 0;
1793 	}
1794 
1795 	if (sclk_min && sclk_max) {
1796 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1797 							    SMU_GFXCLK,
1798 							    sclk_min,
1799 							    sclk_max);
1800 		if (ret)
1801 			return ret;
1802 
1803 		pstate_table->gfxclk_pstate.curr.min = sclk_min;
1804 		pstate_table->gfxclk_pstate.curr.max = sclk_max;
1805 	}
1806 
1807 	if (mclk_min && mclk_max) {
1808 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1809 							    SMU_MCLK,
1810 							    mclk_min,
1811 							    mclk_max);
1812 		if (ret)
1813 			return ret;
1814 
1815 		pstate_table->uclk_pstate.curr.min = mclk_min;
1816 		pstate_table->uclk_pstate.curr.max = mclk_max;
1817 	}
1818 
1819 	if (socclk_min && socclk_max) {
1820 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1821 							    SMU_SOCCLK,
1822 							    socclk_min,
1823 							    socclk_max);
1824 		if (ret)
1825 			return ret;
1826 
1827 		pstate_table->socclk_pstate.curr.min = socclk_min;
1828 		pstate_table->socclk_pstate.curr.max = socclk_max;
1829 	}
1830 
1831 	if (vclk_min && vclk_max) {
1832 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1833 			if (adev->vcn.harvest_config & (1 << i))
1834 				continue;
1835 			ret = smu_v13_0_set_soft_freq_limited_range(smu,
1836 								    i ? SMU_VCLK1 : SMU_VCLK,
1837 								    vclk_min,
1838 								    vclk_max);
1839 			if (ret)
1840 				return ret;
1841 		}
1842 		pstate_table->vclk_pstate.curr.min = vclk_min;
1843 		pstate_table->vclk_pstate.curr.max = vclk_max;
1844 	}
1845 
1846 	if (dclk_min && dclk_max) {
1847 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1848 			if (adev->vcn.harvest_config & (1 << i))
1849 				continue;
1850 			ret = smu_v13_0_set_soft_freq_limited_range(smu,
1851 								    i ? SMU_DCLK1 : SMU_DCLK,
1852 								    dclk_min,
1853 								    dclk_max);
1854 			if (ret)
1855 				return ret;
1856 		}
1857 		pstate_table->dclk_pstate.curr.min = dclk_min;
1858 		pstate_table->dclk_pstate.curr.max = dclk_max;
1859 	}
1860 
1861 	if (fclk_min && fclk_max) {
1862 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1863 							    SMU_FCLK,
1864 							    fclk_min,
1865 							    fclk_max);
1866 		if (ret)
1867 			return ret;
1868 
1869 		pstate_table->fclk_pstate.curr.min = fclk_min;
1870 		pstate_table->fclk_pstate.curr.max = fclk_max;
1871 	}
1872 
1873 	return ret;
1874 }
1875 
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1876 int smu_v13_0_set_power_source(struct smu_context *smu,
1877 			       enum smu_power_src_type power_src)
1878 {
1879 	int pwr_source;
1880 
1881 	pwr_source = smu_cmn_to_asic_specific_index(smu,
1882 						    CMN2ASIC_MAPPING_PWR,
1883 						    (uint32_t)power_src);
1884 	if (pwr_source < 0)
1885 		return -EINVAL;
1886 
1887 	return smu_cmn_send_smc_msg_with_param(smu,
1888 					       SMU_MSG_NotifyPowerSource,
1889 					       pwr_source,
1890 					       NULL);
1891 }
1892 
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1893 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1894 				    enum smu_clk_type clk_type, uint16_t level,
1895 				    uint32_t *value)
1896 {
1897 	int ret = 0, clk_id = 0;
1898 	uint32_t param;
1899 
1900 	if (!value)
1901 		return -EINVAL;
1902 
1903 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1904 		return 0;
1905 
1906 	clk_id = smu_cmn_to_asic_specific_index(smu,
1907 						CMN2ASIC_MAPPING_CLK,
1908 						clk_type);
1909 	if (clk_id < 0)
1910 		return clk_id;
1911 
1912 	param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1913 
1914 	ret = smu_cmn_send_smc_msg_with_param(smu,
1915 					      SMU_MSG_GetDpmFreqByIndex,
1916 					      param,
1917 					      value);
1918 	if (ret)
1919 		return ret;
1920 
1921 	*value = *value & 0x7fffffff;
1922 
1923 	return ret;
1924 }
1925 
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1926 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1927 					 enum smu_clk_type clk_type,
1928 					 uint32_t *value)
1929 {
1930 	int ret;
1931 
1932 	ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1933 	/* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1934 	if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) && (!ret && value))
1935 		++(*value);
1936 
1937 	return ret;
1938 }
1939 
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1940 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1941 					     enum smu_clk_type clk_type,
1942 					     bool *is_fine_grained_dpm)
1943 {
1944 	int ret = 0, clk_id = 0;
1945 	uint32_t param;
1946 	uint32_t value;
1947 
1948 	if (!is_fine_grained_dpm)
1949 		return -EINVAL;
1950 
1951 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1952 		return 0;
1953 
1954 	clk_id = smu_cmn_to_asic_specific_index(smu,
1955 						CMN2ASIC_MAPPING_CLK,
1956 						clk_type);
1957 	if (clk_id < 0)
1958 		return clk_id;
1959 
1960 	param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1961 
1962 	ret = smu_cmn_send_smc_msg_with_param(smu,
1963 					      SMU_MSG_GetDpmFreqByIndex,
1964 					      param,
1965 					      &value);
1966 	if (ret)
1967 		return ret;
1968 
1969 	/*
1970 	 * BIT31:  1 - Fine grained DPM, 0 - Dicrete DPM
1971 	 * now, we un-support it
1972 	 */
1973 	*is_fine_grained_dpm = value & 0x80000000;
1974 
1975 	return 0;
1976 }
1977 
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)1978 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1979 				   enum smu_clk_type clk_type,
1980 				   struct smu_13_0_dpm_table *single_dpm_table)
1981 {
1982 	int ret = 0;
1983 	uint32_t clk;
1984 	int i;
1985 
1986 	ret = smu_v13_0_get_dpm_level_count(smu,
1987 					    clk_type,
1988 					    &single_dpm_table->count);
1989 	if (ret) {
1990 		dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1991 		return ret;
1992 	}
1993 
1994 	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 2)) {
1995 		ret = smu_v13_0_get_fine_grained_status(smu,
1996 							clk_type,
1997 							&single_dpm_table->is_fine_grained);
1998 		if (ret) {
1999 			dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2000 			return ret;
2001 		}
2002 	}
2003 
2004 	for (i = 0; i < single_dpm_table->count; i++) {
2005 		ret = smu_v13_0_get_dpm_freq_by_index(smu,
2006 						      clk_type,
2007 						      i,
2008 						      &clk);
2009 		if (ret) {
2010 			dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2011 			return ret;
2012 		}
2013 
2014 		single_dpm_table->dpm_levels[i].value = clk;
2015 		single_dpm_table->dpm_levels[i].enabled = true;
2016 
2017 		if (i == 0)
2018 			single_dpm_table->min = clk;
2019 		else if (i == single_dpm_table->count - 1)
2020 			single_dpm_table->max = clk;
2021 	}
2022 
2023 	return 0;
2024 }
2025 
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)2026 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2027 {
2028 	struct amdgpu_device *adev = smu->adev;
2029 
2030 	return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2031 		PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2032 		>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2033 }
2034 
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)2035 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2036 {
2037 	uint32_t width_level;
2038 
2039 	width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2040 	if (width_level > LINK_WIDTH_MAX)
2041 		width_level = 0;
2042 
2043 	return link_width[width_level];
2044 }
2045 
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)2046 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2047 {
2048 	struct amdgpu_device *adev = smu->adev;
2049 
2050 	return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2051 		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2052 		>> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2053 }
2054 
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)2055 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2056 {
2057 	uint32_t speed_level;
2058 
2059 	speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2060 	if (speed_level > LINK_SPEED_MAX)
2061 		speed_level = 0;
2062 
2063 	return link_speed[speed_level];
2064 }
2065 
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable)2066 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2067 			     bool enable)
2068 {
2069 	struct amdgpu_device *adev = smu->adev;
2070 	int i, ret = 0;
2071 
2072 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2073 		if (adev->vcn.harvest_config & (1 << i))
2074 			continue;
2075 
2076 		ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2077 						      SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2078 						      i << 16U, NULL);
2079 		if (ret)
2080 			return ret;
2081 	}
2082 
2083 	return ret;
2084 }
2085 
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2086 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2087 			      bool enable)
2088 {
2089 	return smu_cmn_send_smc_msg_with_param(smu, enable ?
2090 					       SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2091 					       0, NULL);
2092 }
2093 
smu_v13_0_run_btc(struct smu_context * smu)2094 int smu_v13_0_run_btc(struct smu_context *smu)
2095 {
2096 	int res;
2097 
2098 	res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2099 	if (res)
2100 		dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2101 
2102 	return res;
2103 }
2104 
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2105 int smu_v13_0_gpo_control(struct smu_context *smu,
2106 			  bool enablement)
2107 {
2108 	int res;
2109 
2110 	res = smu_cmn_send_smc_msg_with_param(smu,
2111 					      SMU_MSG_AllowGpo,
2112 					      enablement ? 1 : 0,
2113 					      NULL);
2114 	if (res)
2115 		dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2116 
2117 	return res;
2118 }
2119 
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2120 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2121 				 bool enablement)
2122 {
2123 	struct amdgpu_device *adev = smu->adev;
2124 	int ret = 0;
2125 
2126 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2127 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2128 		if (ret) {
2129 			dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2130 			return ret;
2131 		}
2132 	}
2133 
2134 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2135 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2136 		if (ret) {
2137 			dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2138 			return ret;
2139 		}
2140 	}
2141 
2142 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2143 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2144 		if (ret) {
2145 			dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2146 			return ret;
2147 		}
2148 	}
2149 
2150 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2151 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2152 		if (ret) {
2153 			dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2154 			return ret;
2155 		}
2156 	}
2157 
2158 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2159 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2160 		if (ret) {
2161 			dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2162 			return ret;
2163 		}
2164 	}
2165 
2166 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2167 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2168 		if (ret) {
2169 			dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2170 			return ret;
2171 		}
2172 	}
2173 
2174 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2175 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2176 		if (ret) {
2177 			dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2178 			return ret;
2179 		}
2180 	}
2181 
2182 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2183 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2184 		if (ret) {
2185 			dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2186 			return ret;
2187 		}
2188 	}
2189 
2190 	return ret;
2191 }
2192 
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2193 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2194 			      bool enablement)
2195 {
2196 	int ret = 0;
2197 
2198 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2199 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2200 
2201 	return ret;
2202 }
2203 
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2204 static int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2205 				      enum smu_baco_seq baco_seq)
2206 {
2207 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2208 	int ret;
2209 
2210 	ret = smu_cmn_send_smc_msg_with_param(smu,
2211 					      SMU_MSG_ArmD3,
2212 					      baco_seq,
2213 					      NULL);
2214 	if (ret)
2215 		return ret;
2216 
2217 	if (baco_seq == BACO_SEQ_BAMACO ||
2218 	    baco_seq == BACO_SEQ_BACO)
2219 		smu_baco->state = SMU_BACO_STATE_ENTER;
2220 	else
2221 		smu_baco->state = SMU_BACO_STATE_EXIT;
2222 
2223 	return 0;
2224 }
2225 
smu_v13_0_baco_get_state(struct smu_context * smu)2226 static enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2227 {
2228 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2229 
2230 	return smu_baco->state;
2231 }
2232 
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2233 static int smu_v13_0_baco_set_state(struct smu_context *smu,
2234 			     enum smu_baco_state state)
2235 {
2236 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2237 	struct amdgpu_device *adev = smu->adev;
2238 	int ret = 0;
2239 
2240 	if (smu_v13_0_baco_get_state(smu) == state)
2241 		return 0;
2242 
2243 	if (state == SMU_BACO_STATE_ENTER) {
2244 		ret = smu_cmn_send_smc_msg_with_param(smu,
2245 						      SMU_MSG_EnterBaco,
2246 						      (smu_baco->maco_support && amdgpu_runtime_pm != 1) ?
2247 						      BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2248 						      NULL);
2249 	} else {
2250 		ret = smu_cmn_send_smc_msg(smu,
2251 					   SMU_MSG_ExitBaco,
2252 					   NULL);
2253 		if (ret)
2254 			return ret;
2255 
2256 		/* clear vbios scratch 6 and 7 for coming asic reinit */
2257 		WREG32(adev->bios_scratch_reg_offset + 6, 0);
2258 		WREG32(adev->bios_scratch_reg_offset + 7, 0);
2259 	}
2260 
2261 	if (!ret)
2262 		smu_baco->state = state;
2263 
2264 	return ret;
2265 }
2266 
smu_v13_0_baco_is_support(struct smu_context * smu)2267 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2268 {
2269 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2270 
2271 	if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
2272 		return false;
2273 
2274 	/* return true if ASIC is in BACO state already */
2275 	if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2276 		return true;
2277 
2278 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2279 	    !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2280 		return false;
2281 
2282 	return true;
2283 }
2284 
smu_v13_0_baco_enter(struct smu_context * smu)2285 int smu_v13_0_baco_enter(struct smu_context *smu)
2286 {
2287 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2288 	struct amdgpu_device *adev = smu->adev;
2289 	int ret;
2290 
2291 	if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2292 		return smu_v13_0_baco_set_armd3_sequence(smu,
2293 				(smu_baco->maco_support && amdgpu_runtime_pm != 1) ?
2294 					BACO_SEQ_BAMACO : BACO_SEQ_BACO);
2295 	} else {
2296 		ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
2297 		if (!ret)
2298 			usleep_range(10000, 11000);
2299 
2300 		return ret;
2301 	}
2302 }
2303 
smu_v13_0_baco_exit(struct smu_context * smu)2304 int smu_v13_0_baco_exit(struct smu_context *smu)
2305 {
2306 	struct amdgpu_device *adev = smu->adev;
2307 	int ret;
2308 
2309 	if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2310 		/* Wait for PMFW handling for the Dstate change */
2311 		usleep_range(10000, 11000);
2312 		ret = smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2313 	} else {
2314 		ret = smu_v13_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
2315 	}
2316 
2317 	if (!ret)
2318 		adev->gfx.is_poweron = false;
2319 
2320 	return ret;
2321 }
2322 
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2323 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2324 {
2325 	uint16_t index;
2326 	struct amdgpu_device *adev = smu->adev;
2327 
2328 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2329 		return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu,
2330 						       ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL);
2331 	}
2332 
2333 	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2334 					       SMU_MSG_EnableGfxImu);
2335 	return smu_cmn_send_msg_without_waiting(smu, index,
2336 						ENABLE_IMU_ARG_GFXOFF_ENABLE);
2337 }
2338 
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2339 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2340 				enum PP_OD_DPM_TABLE_COMMAND type,
2341 				long input[], uint32_t size)
2342 {
2343 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2344 	int ret = 0;
2345 
2346 	/* Only allowed in manual mode */
2347 	if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2348 		return -EINVAL;
2349 
2350 	switch (type) {
2351 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
2352 		if (size != 2) {
2353 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2354 			return -EINVAL;
2355 		}
2356 
2357 		if (input[0] == 0) {
2358 			if (input[1] < smu->gfx_default_hard_min_freq) {
2359 				dev_warn(smu->adev->dev,
2360 					 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2361 					 input[1], smu->gfx_default_hard_min_freq);
2362 				return -EINVAL;
2363 			}
2364 			smu->gfx_actual_hard_min_freq = input[1];
2365 		} else if (input[0] == 1) {
2366 			if (input[1] > smu->gfx_default_soft_max_freq) {
2367 				dev_warn(smu->adev->dev,
2368 					 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2369 					 input[1], smu->gfx_default_soft_max_freq);
2370 				return -EINVAL;
2371 			}
2372 			smu->gfx_actual_soft_max_freq = input[1];
2373 		} else {
2374 			return -EINVAL;
2375 		}
2376 		break;
2377 	case PP_OD_RESTORE_DEFAULT_TABLE:
2378 		if (size != 0) {
2379 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2380 			return -EINVAL;
2381 		}
2382 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2383 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2384 		break;
2385 	case PP_OD_COMMIT_DPM_TABLE:
2386 		if (size != 0) {
2387 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2388 			return -EINVAL;
2389 		}
2390 		if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2391 			dev_err(smu->adev->dev,
2392 				"The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2393 				smu->gfx_actual_hard_min_freq,
2394 				smu->gfx_actual_soft_max_freq);
2395 			return -EINVAL;
2396 		}
2397 
2398 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2399 						      smu->gfx_actual_hard_min_freq,
2400 						      NULL);
2401 		if (ret) {
2402 			dev_err(smu->adev->dev, "Set hard min sclk failed!");
2403 			return ret;
2404 		}
2405 
2406 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2407 						      smu->gfx_actual_soft_max_freq,
2408 						      NULL);
2409 		if (ret) {
2410 			dev_err(smu->adev->dev, "Set soft max sclk failed!");
2411 			return ret;
2412 		}
2413 		break;
2414 	default:
2415 		return -ENOSYS;
2416 	}
2417 
2418 	return ret;
2419 }
2420 
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2421 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2422 {
2423 	struct smu_table_context *smu_table = &smu->smu_table;
2424 
2425 	return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2426 				    smu_table->clocks_table, false);
2427 }
2428 
smu_v13_0_set_smu_mailbox_registers(struct smu_context * smu)2429 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2430 {
2431 	struct amdgpu_device *adev = smu->adev;
2432 
2433 	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2434 	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2435 	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2436 }
2437 
smu_v13_0_mode1_reset(struct smu_context * smu)2438 int smu_v13_0_mode1_reset(struct smu_context *smu)
2439 {
2440 	int ret = 0;
2441 
2442 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2443 	if (!ret)
2444 		msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2445 
2446 	return ret;
2447 }
2448 
smu_v13_0_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2449 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2450 				     uint8_t pcie_gen_cap,
2451 				     uint8_t pcie_width_cap)
2452 {
2453 	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2454 	struct smu_13_0_pcie_table *pcie_table =
2455 				&dpm_context->dpm_tables.pcie_table;
2456 	int num_of_levels = pcie_table->num_of_link_levels;
2457 	uint32_t smu_pcie_arg;
2458 	int ret, i;
2459 
2460 	if (!num_of_levels)
2461 		return 0;
2462 
2463 	if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2464 		if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2465 			pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2466 
2467 		if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2468 			pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2469 
2470 		/* Force all levels to use the same settings */
2471 		for (i = 0; i < num_of_levels; i++) {
2472 			pcie_table->pcie_gen[i] = pcie_gen_cap;
2473 			pcie_table->pcie_lane[i] = pcie_width_cap;
2474 		}
2475 	} else {
2476 		for (i = 0; i < num_of_levels; i++) {
2477 			if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2478 				pcie_table->pcie_gen[i] = pcie_gen_cap;
2479 			if (pcie_table->pcie_lane[i] > pcie_width_cap)
2480 				pcie_table->pcie_lane[i] = pcie_width_cap;
2481 		}
2482 	}
2483 
2484 	for (i = 0; i < num_of_levels; i++) {
2485 		smu_pcie_arg = i << 16;
2486 		smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2487 		smu_pcie_arg |= pcie_table->pcie_lane[i];
2488 
2489 		ret = smu_cmn_send_smc_msg_with_param(smu,
2490 						      SMU_MSG_OverridePcieParameters,
2491 						      smu_pcie_arg,
2492 						      NULL);
2493 		if (ret)
2494 			return ret;
2495 	}
2496 
2497 	return 0;
2498 }
2499 
smu_v13_0_disable_pmfw_state(struct smu_context * smu)2500 int smu_v13_0_disable_pmfw_state(struct smu_context *smu)
2501 {
2502 	int ret;
2503 	struct amdgpu_device *adev = smu->adev;
2504 
2505 	WREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff), 0);
2506 
2507 	ret = RREG32_PCIE(MP1_Public |
2508 					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
2509 
2510 	return ret == 0 ? 0 : -EINVAL;
2511 }
2512 
smu_v13_0_enable_uclk_shadow(struct smu_context * smu,bool enable)2513 int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable)
2514 {
2515 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableUCLKShadow, enable, NULL);
2516 }
2517 
smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context * smu,struct freq_band_range * exclusion_ranges)2518 int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
2519 						 struct freq_band_range *exclusion_ranges)
2520 {
2521 	WifiBandEntryTable_t wifi_bands;
2522 	int valid_entries = 0;
2523 	int ret, i;
2524 
2525 	memset(&wifi_bands, 0, sizeof(wifi_bands));
2526 	for (i = 0; i < ARRAY_SIZE(wifi_bands.WifiBandEntry); i++) {
2527 		if (!exclusion_ranges[i].start && !exclusion_ranges[i].end)
2528 			break;
2529 
2530 		/* PMFW expects the inputs to be in Mhz unit */
2531 		wifi_bands.WifiBandEntry[valid_entries].LowFreq =
2532 			DIV_ROUND_DOWN_ULL(exclusion_ranges[i].start, HZ_PER_MHZ);
2533 		wifi_bands.WifiBandEntry[valid_entries++].HighFreq =
2534 			DIV_ROUND_UP_ULL(exclusion_ranges[i].end, HZ_PER_MHZ);
2535 	}
2536 	wifi_bands.WifiBandEntryNum = valid_entries;
2537 
2538 	/*
2539 	 * Per confirm with PMFW team, WifiBandEntryNum = 0
2540 	 * is a valid setting.
2541 	 *
2542 	 * Considering the scenarios below:
2543 	 * - At first the wifi device adds an exclusion range e.g. (2400,2500) to
2544 	 *   BIOS and our driver gets notified. We will set WifiBandEntryNum = 1
2545 	 *   and pass the WifiBandEntry (2400, 2500) to PMFW.
2546 	 *
2547 	 * - Later the wifi device removes the wifiband list added above and
2548 	 *   our driver gets notified again. At this time, driver will set
2549 	 *   WifiBandEntryNum = 0 and pass an empty WifiBandEntry list to PMFW.
2550 	 *
2551 	 * - PMFW may still need to do some uclk shadow update(e.g. switching
2552 	 *   from shadow clock back to primary clock) on receiving this.
2553 	 */
2554 	ret = smu_cmn_update_table(smu, SMU_TABLE_WIFIBAND, 0, &wifi_bands, true);
2555 	if (ret)
2556 		dev_warn(smu->adev->dev, "Failed to set wifiband!");
2557 
2558 	return ret;
2559 }
2560