1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __SMU_V14_0_H__
24 #define __SMU_V14_0_H__
25 
26 #include "amdgpu_smu.h"
27 
28 #define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7
30 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x1
31 
32 #define FEATURE_MASK(feature) (1ULL << feature)
33 
34 /* MP Apertures */
35 #define MP0_Public			0x03800000
36 #define MP0_SRAM			0x03900000
37 #define MP1_Public			0x03b00000
38 #define MP1_SRAM			0x03c00004
39 
40 /* address block */
41 #define smnMP1_FIRMWARE_FLAGS		0x3010028
42 #define smnMP1_PUB_CTRL			0x3010d10
43 
44 #define MAX_DPM_LEVELS 16
45 #define MAX_PCIE_CONF 3
46 
47 struct smu_14_0_max_sustainable_clocks {
48 	uint32_t display_clock;
49 	uint32_t phy_clock;
50 	uint32_t pixel_clock;
51 	uint32_t uclock;
52 	uint32_t dcef_clock;
53 	uint32_t soc_clock;
54 };
55 
56 struct smu_14_0_dpm_clk_level {
57 	bool				enabled;
58 	uint32_t			value;
59 };
60 
61 struct smu_14_0_dpm_table {
62 	uint32_t			min;        /* MHz */
63 	uint32_t			max;        /* MHz */
64 	uint32_t			count;
65 	bool				is_fine_grained;
66 	struct smu_14_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];
67 };
68 
69 struct smu_14_0_pcie_table {
70 	uint8_t  pcie_gen[MAX_PCIE_CONF];
71 	uint8_t  pcie_lane[MAX_PCIE_CONF];
72 	uint16_t clk_freq[MAX_PCIE_CONF];
73 	uint32_t num_of_link_levels;
74 };
75 
76 struct smu_14_0_dpm_tables {
77 	struct smu_14_0_dpm_table        soc_table;
78 	struct smu_14_0_dpm_table        gfx_table;
79 	struct smu_14_0_dpm_table        uclk_table;
80 	struct smu_14_0_dpm_table        eclk_table;
81 	struct smu_14_0_dpm_table        vclk_table;
82 	struct smu_14_0_dpm_table        dclk_table;
83 	struct smu_14_0_dpm_table        dcef_table;
84 	struct smu_14_0_dpm_table        pixel_table;
85 	struct smu_14_0_dpm_table        display_table;
86 	struct smu_14_0_dpm_table        phy_table;
87 	struct smu_14_0_dpm_table        fclk_table;
88 	struct smu_14_0_pcie_table       pcie_table;
89 };
90 
91 struct smu_14_0_dpm_context {
92 	struct smu_14_0_dpm_tables  dpm_tables;
93 	uint32_t                    workload_policy_mask;
94 	uint32_t                    dcef_min_ds_clk;
95 };
96 
97 enum smu_14_0_power_state {
98 	SMU_14_0_POWER_STATE__D0 = 0,
99 	SMU_14_0_POWER_STATE__D1,
100 	SMU_14_0_POWER_STATE__D3, /* Sleep*/
101 	SMU_14_0_POWER_STATE__D4, /* Hibernate*/
102 	SMU_14_0_POWER_STATE__D5, /* Power off*/
103 };
104 
105 struct smu_14_0_power_context {
106 	uint32_t	power_source;
107 	uint8_t		in_power_limit_boost_mode;
108 	enum smu_14_0_power_state power_state;
109 };
110 
111 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
112 
113 int smu_v14_0_init_microcode(struct smu_context *smu);
114 
115 void smu_v14_0_fini_microcode(struct smu_context *smu);
116 
117 int smu_v14_0_load_microcode(struct smu_context *smu);
118 
119 int smu_v14_0_init_smc_tables(struct smu_context *smu);
120 
121 int smu_v14_0_fini_smc_tables(struct smu_context *smu);
122 
123 int smu_v14_0_init_power(struct smu_context *smu);
124 
125 int smu_v14_0_fini_power(struct smu_context *smu);
126 
127 int smu_v14_0_check_fw_status(struct smu_context *smu);
128 
129 int smu_v14_0_setup_pptable(struct smu_context *smu);
130 
131 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu);
132 
133 int smu_v14_0_check_fw_version(struct smu_context *smu);
134 
135 int smu_v14_0_set_driver_table_location(struct smu_context *smu);
136 
137 int smu_v14_0_set_tool_table_location(struct smu_context *smu);
138 
139 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu);
140 
141 int smu_v14_0_system_features_control(struct smu_context *smu,
142 				      bool en);
143 
144 int smu_v14_0_set_allowed_mask(struct smu_context *smu);
145 
146 int smu_v14_0_notify_display_change(struct smu_context *smu);
147 
148 int smu_v14_0_get_current_power_limit(struct smu_context *smu,
149 				      uint32_t *power_limit);
150 
151 int smu_v14_0_set_power_limit(struct smu_context *smu,
152 			      enum smu_ppt_limit_type limit_type,
153 			      uint32_t limit);
154 
155 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable);
156 
157 int smu_v14_0_register_irq_handler(struct smu_context *smu);
158 
159 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
160 				      enum smu_baco_seq baco_seq);
161 
162 bool smu_v14_0_baco_is_support(struct smu_context *smu);
163 
164 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu);
165 
166 int smu_v14_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
167 
168 int smu_v14_0_baco_enter(struct smu_context *smu);
169 int smu_v14_0_baco_exit(struct smu_context *smu);
170 
171 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
172 				    uint32_t *min, uint32_t *max);
173 
174 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
175 					  uint32_t min, uint32_t max);
176 
177 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
178 					  enum smu_clk_type clk_type,
179 					  uint32_t min,
180 					  uint32_t max);
181 
182 int smu_v14_0_set_performance_level(struct smu_context *smu,
183 				    enum amd_dpm_forced_level level);
184 
185 int smu_v14_0_set_power_source(struct smu_context *smu,
186 			       enum smu_power_src_type power_src);
187 
188 int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
189 				   enum smu_clk_type clk_type,
190 				   struct smu_14_0_dpm_table *single_dpm_table);
191 
192 int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
193 			      bool enablement);
194 
195 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
196 			     uint64_t event_arg);
197 
198 int smu_v14_0_set_vcn_enable(struct smu_context *smu,
199 			     bool enable);
200 
201 int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
202 			      bool enable);
203 
204 int smu_v14_0_init_pptable_microcode(struct smu_context *smu);
205 
206 int smu_v14_0_run_btc(struct smu_context *smu);
207 
208 int smu_v14_0_gpo_control(struct smu_context *smu,
209 			  bool enablement);
210 
211 int smu_v14_0_deep_sleep_control(struct smu_context *smu,
212 				 bool enablement);
213 
214 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu);
215 
216 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu);
217 
218 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
219 					void **table,
220 					uint32_t *size,
221 					uint32_t pptable_id);
222 
223 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
224 				enum PP_OD_DPM_TABLE_COMMAND type,
225 				long input[], uint32_t size);
226 
227 void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu);
228 
229 #endif
230 #endif
231