1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn32/dcn32_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn32_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn30/dcn30_hubbub.h"
41 #include "dcn31/dcn31_hubbub.h"
42 #include "dcn32/dcn32_hubbub.h"
43 #include "dcn32/dcn32_mpc.h"
44 #include "dcn32/dcn32_hubp.h"
45 #include "irq/dcn32/irq_service_dcn32.h"
46 #include "dcn32/dcn32_dpp.h"
47 #include "dcn32/dcn32_optc.h"
48 #include "dcn20/dcn20_hwseq.h"
49 #include "dcn30/dcn30_hwseq.h"
50 #include "dce110/dce110_hwseq.h"
51 #include "dcn30/dcn30_opp.h"
52 #include "dcn20/dcn20_dsc.h"
53 #include "dcn30/dcn30_vpg.h"
54 #include "dcn30/dcn30_afmt.h"
55 #include "dcn30/dcn30_dio_stream_encoder.h"
56 #include "dcn32/dcn32_dio_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
59 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
60 #include "dcn31/dcn31_apg.h"
61 #include "dcn31/dcn31_dio_link_encoder.h"
62 #include "dcn32/dcn32_dio_link_encoder.h"
63 #include "dce/dce_clock_source.h"
64 #include "dce/dce_audio.h"
65 #include "dce/dce_hwseq.h"
66 #include "clk_mgr.h"
67 #include "virtual/virtual_stream_encoder.h"
68 #include "dml/display_mode_vba.h"
69 #include "dcn32/dcn32_dccg.h"
70 #include "dcn10/dcn10_resource.h"
71 #include "link.h"
72 #include "dcn31/dcn31_panel_cntl.h"
73
74 #include "dcn30/dcn30_dwb.h"
75 #include "dcn32/dcn32_mmhubbub.h"
76
77 #include "dcn/dcn_3_2_0_offset.h"
78 #include "dcn/dcn_3_2_0_sh_mask.h"
79 #include "nbio/nbio_4_3_0_offset.h"
80
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86
87 #include "dml/dcn30/display_mode_vba_30.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "dml/dcn32/dcn32_fpu.h"
91
92 #include "dc_state_priv.h"
93
94 #include "dml2/dml2_wrapper.h"
95
96 #define DC_LOGGER_INIT(logger)
97
98 enum dcn32_clk_src_array_id {
99 DCN32_CLK_SRC_PLL0,
100 DCN32_CLK_SRC_PLL1,
101 DCN32_CLK_SRC_PLL2,
102 DCN32_CLK_SRC_PLL3,
103 DCN32_CLK_SRC_PLL4,
104 DCN32_CLK_SRC_TOTAL
105 };
106
107 /* begin *********************
108 * macros to expend register list macro defined in HW object header file
109 */
110
111 /* DCN */
112 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
113
114 #define BASE(seg) BASE_INNER(seg)
115
116 #define SR(reg_name)\
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
118 reg ## reg_name
119 #define SR_ARR(reg_name, id) \
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
121
122 #define SR_ARR_INIT(reg_name, id, value) \
123 REG_STRUCT[id].reg_name = value
124
125 #define SRI(reg_name, block, id)\
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
127 reg ## block ## id ## _ ## reg_name
128
129 #define SRI_ARR(reg_name, block, id)\
130 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 reg ## block ## id ## _ ## reg_name
132
133 #define SR_ARR_I2C(reg_name, id) \
134 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
135
136 #define SRI_ARR_I2C(reg_name, block, id)\
137 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 reg ## block ## id ## _ ## reg_name
139
140 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
141 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 reg ## block ## id ## _ ## reg_name
143
144 #define SRI2(reg_name, block, id)\
145 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
146 reg ## reg_name
147 #define SRI2_ARR(reg_name, block, id)\
148 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 reg ## reg_name
150
151 #define SRIR(var_name, reg_name, block, id)\
152 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 reg ## block ## id ## _ ## reg_name
154
155 #define SRII(reg_name, block, id)\
156 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 reg ## block ## id ## _ ## reg_name
158
159 #define SRII_ARR_2(reg_name, block, id, inst)\
160 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 reg ## block ## id ## _ ## reg_name
162
163 #define SRII_MPC_RMU(reg_name, block, id)\
164 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define SRII_DWB(reg_name, temp_name, block, id)\
168 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
169 reg ## block ## id ## _ ## temp_name
170
171 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
172 .field_name = reg_name ## __ ## field_name ## post_fix
173
174 #define DCCG_SRII(reg_name, block, id)\
175 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
176 reg ## block ## id ## _ ## reg_name
177
178 #define VUPDATE_SRII(reg_name, block, id)\
179 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
180 reg ## reg_name ## _ ## block ## id
181
182 /* NBIO */
183 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
184
185 #define NBIO_BASE(seg) \
186 NBIO_BASE_INNER(seg)
187
188 #define NBIO_SR(reg_name)\
189 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
190 regBIF_BX0_ ## reg_name
191 #define NBIO_SR_ARR(reg_name, id)\
192 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
193 regBIF_BX0_ ## reg_name
194
195 #undef CTX
196 #define CTX ctx
197 #define REG(reg_name) \
198 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
199
200 static struct bios_registers bios_regs;
201
202 #define bios_regs_init() \
203 ( \
204 NBIO_SR(BIOS_SCRATCH_3),\
205 NBIO_SR(BIOS_SCRATCH_6)\
206 )
207
208 #define clk_src_regs_init(index, pllid)\
209 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
210
211 static struct dce110_clk_src_regs clk_src_regs[5];
212
213 static const struct dce110_clk_src_shift cs_shift = {
214 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
215 };
216
217 static const struct dce110_clk_src_mask cs_mask = {
218 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
219 };
220
221 #define abm_regs_init(id)\
222 ABM_DCN32_REG_LIST_RI(id)
223
224 static struct dce_abm_registers abm_regs[4];
225
226 static const struct dce_abm_shift abm_shift = {
227 ABM_MASK_SH_LIST_DCN32(__SHIFT)
228 };
229
230 static const struct dce_abm_mask abm_mask = {
231 ABM_MASK_SH_LIST_DCN32(_MASK)
232 };
233
234 #define audio_regs_init(id)\
235 AUD_COMMON_REG_LIST_RI(id)
236
237 static struct dce_audio_registers audio_regs[5];
238
239 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
240 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
242 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
243
244 static const struct dce_audio_shift audio_shift = {
245 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
246 };
247
248 static const struct dce_audio_mask audio_mask = {
249 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
250 };
251
252 #define vpg_regs_init(id)\
253 VPG_DCN3_REG_LIST_RI(id)
254
255 static struct dcn30_vpg_registers vpg_regs[10];
256
257 static const struct dcn30_vpg_shift vpg_shift = {
258 DCN3_VPG_MASK_SH_LIST(__SHIFT)
259 };
260
261 static const struct dcn30_vpg_mask vpg_mask = {
262 DCN3_VPG_MASK_SH_LIST(_MASK)
263 };
264
265 #define afmt_regs_init(id)\
266 AFMT_DCN3_REG_LIST_RI(id)
267
268 static struct dcn30_afmt_registers afmt_regs[6];
269
270 static const struct dcn30_afmt_shift afmt_shift = {
271 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
272 };
273
274 static const struct dcn30_afmt_mask afmt_mask = {
275 DCN3_AFMT_MASK_SH_LIST(_MASK)
276 };
277
278 #define apg_regs_init(id)\
279 APG_DCN31_REG_LIST_RI(id)
280
281 static struct dcn31_apg_registers apg_regs[4];
282
283 static const struct dcn31_apg_shift apg_shift = {
284 DCN31_APG_MASK_SH_LIST(__SHIFT)
285 };
286
287 static const struct dcn31_apg_mask apg_mask = {
288 DCN31_APG_MASK_SH_LIST(_MASK)
289 };
290
291 #define stream_enc_regs_init(id)\
292 SE_DCN32_REG_LIST_RI(id)
293
294 static struct dcn10_stream_enc_registers stream_enc_regs[5];
295
296 static const struct dcn10_stream_encoder_shift se_shift = {
297 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
298 };
299
300 static const struct dcn10_stream_encoder_mask se_mask = {
301 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
302 };
303
304
305 #define aux_regs_init(id)\
306 DCN2_AUX_REG_LIST_RI(id)
307
308 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
309
310 #define hpd_regs_init(id)\
311 HPD_REG_LIST_RI(id)
312
313 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
314
315 #define link_regs_init(id, phyid)\
316 ( \
317 LE_DCN31_REG_LIST_RI(id), \
318 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
319 )
320 /*DPCS_DCN31_REG_LIST(id),*/ \
321
322 static struct dcn10_link_enc_registers link_enc_regs[5];
323
324 static const struct dcn10_link_enc_shift le_shift = {
325 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
326 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
327 };
328
329 static const struct dcn10_link_enc_mask le_mask = {
330 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
331 //DPCS_DCN31_MASK_SH_LIST(_MASK)
332 };
333
334 #define hpo_dp_stream_encoder_reg_init(id)\
335 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
336
337 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
338
339 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
340 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
341 };
342
343 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
344 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
345 };
346
347
348 #define hpo_dp_link_encoder_reg_init(id)\
349 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
350 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
351 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
352 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
353 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
354
355 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
356
357 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
358 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
359 };
360
361 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
362 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
363 };
364
365 #define dpp_regs_init(id)\
366 DPP_REG_LIST_DCN30_COMMON_RI(id)
367
368 static struct dcn3_dpp_registers dpp_regs[4];
369
370 static const struct dcn3_dpp_shift tf_shift = {
371 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
372 };
373
374 static const struct dcn3_dpp_mask tf_mask = {
375 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
376 };
377
378
379 #define opp_regs_init(id)\
380 OPP_REG_LIST_DCN30_RI(id)
381
382 static struct dcn20_opp_registers opp_regs[4];
383
384 static const struct dcn20_opp_shift opp_shift = {
385 OPP_MASK_SH_LIST_DCN20(__SHIFT)
386 };
387
388 static const struct dcn20_opp_mask opp_mask = {
389 OPP_MASK_SH_LIST_DCN20(_MASK)
390 };
391
392 #define aux_engine_regs_init(id)\
393 ( \
394 AUX_COMMON_REG_LIST0_RI(id), \
395 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
396 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
397 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
398 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
399 )
400
401 static struct dce110_aux_registers aux_engine_regs[5];
402
403 static const struct dce110_aux_registers_shift aux_shift = {
404 DCN_AUX_MASK_SH_LIST(__SHIFT)
405 };
406
407 static const struct dce110_aux_registers_mask aux_mask = {
408 DCN_AUX_MASK_SH_LIST(_MASK)
409 };
410
411 #define dwbc_regs_dcn3_init(id)\
412 DWBC_COMMON_REG_LIST_DCN30_RI(id)
413
414 static struct dcn30_dwbc_registers dwbc30_regs[1];
415
416 static const struct dcn30_dwbc_shift dwbc30_shift = {
417 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
418 };
419
420 static const struct dcn30_dwbc_mask dwbc30_mask = {
421 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
422 };
423
424 #define mcif_wb_regs_dcn3_init(id)\
425 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
426
427 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
428
429 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
430 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
431 };
432
433 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
434 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
435 };
436
437 #define dsc_regsDCN20_init(id)\
438 DSC_REG_LIST_DCN20_RI(id)
439
440 static struct dcn20_dsc_registers dsc_regs[4];
441
442 static const struct dcn20_dsc_shift dsc_shift = {
443 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
444 };
445
446 static const struct dcn20_dsc_mask dsc_mask = {
447 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
448 };
449
450 static struct dcn30_mpc_registers mpc_regs;
451
452 #define dcn_mpc_regs_init() \
453 MPC_REG_LIST_DCN3_2_RI(0),\
454 MPC_REG_LIST_DCN3_2_RI(1),\
455 MPC_REG_LIST_DCN3_2_RI(2),\
456 MPC_REG_LIST_DCN3_2_RI(3),\
457 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
458 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
459 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
460 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
461 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
462
463 static const struct dcn30_mpc_shift mpc_shift = {
464 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
465 };
466
467 static const struct dcn30_mpc_mask mpc_mask = {
468 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
469 };
470
471 #define optc_regs_init(id)\
472 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
473
474 static struct dcn_optc_registers optc_regs[4];
475
476 static const struct dcn_optc_shift optc_shift = {
477 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
478 };
479
480 static const struct dcn_optc_mask optc_mask = {
481 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
482 };
483
484 #define hubp_regs_init(id)\
485 HUBP_REG_LIST_DCN32_RI(id)
486
487 static struct dcn_hubp2_registers hubp_regs[4];
488
489
490 static const struct dcn_hubp2_shift hubp_shift = {
491 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
492 };
493
494 static const struct dcn_hubp2_mask hubp_mask = {
495 HUBP_MASK_SH_LIST_DCN32(_MASK)
496 };
497
498 static struct dcn_hubbub_registers hubbub_reg;
499 #define hubbub_reg_init()\
500 HUBBUB_REG_LIST_DCN32_RI(0)
501
502 static const struct dcn_hubbub_shift hubbub_shift = {
503 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
504 };
505
506 static const struct dcn_hubbub_mask hubbub_mask = {
507 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
508 };
509
510 static struct dccg_registers dccg_regs;
511
512 #define dccg_regs_init()\
513 DCCG_REG_LIST_DCN32_RI()
514
515 static const struct dccg_shift dccg_shift = {
516 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
517 };
518
519 static const struct dccg_mask dccg_mask = {
520 DCCG_MASK_SH_LIST_DCN32(_MASK)
521 };
522
523
524 #define SRII2(reg_name_pre, reg_name_post, id)\
525 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
526 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
527 reg ## reg_name_pre ## id ## _ ## reg_name_post
528
529
530 #define HWSEQ_DCN32_REG_LIST()\
531 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
532 SR(DIO_MEM_PWR_CTRL), \
533 SR(ODM_MEM_PWR_CTRL3), \
534 SR(MMHUBBUB_MEM_PWR_CNTL), \
535 SR(DCCG_GATE_DISABLE_CNTL), \
536 SR(DCCG_GATE_DISABLE_CNTL2), \
537 SR(DCFCLK_CNTL),\
538 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
539 SRII(PIXEL_RATE_CNTL, OTG, 0), \
540 SRII(PIXEL_RATE_CNTL, OTG, 1),\
541 SRII(PIXEL_RATE_CNTL, OTG, 2),\
542 SRII(PIXEL_RATE_CNTL, OTG, 3),\
543 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
547 SR(MICROSECOND_TIME_BASE_DIV), \
548 SR(MILLISECOND_TIME_BASE_DIV), \
549 SR(DISPCLK_FREQ_CHANGE_CNTL), \
550 SR(RBBMIF_TIMEOUT_DIS), \
551 SR(RBBMIF_TIMEOUT_DIS_2), \
552 SR(DCHUBBUB_CRC_CTRL), \
553 SR(DPP_TOP0_DPP_CRC_CTRL), \
554 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
555 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
556 SR(MPC_CRC_CTRL), \
557 SR(MPC_CRC_RESULT_GB), \
558 SR(MPC_CRC_RESULT_C), \
559 SR(MPC_CRC_RESULT_AR), \
560 SR(DOMAIN0_PG_CONFIG), \
561 SR(DOMAIN1_PG_CONFIG), \
562 SR(DOMAIN2_PG_CONFIG), \
563 SR(DOMAIN3_PG_CONFIG), \
564 SR(DOMAIN16_PG_CONFIG), \
565 SR(DOMAIN17_PG_CONFIG), \
566 SR(DOMAIN18_PG_CONFIG), \
567 SR(DOMAIN19_PG_CONFIG), \
568 SR(DOMAIN0_PG_STATUS), \
569 SR(DOMAIN1_PG_STATUS), \
570 SR(DOMAIN2_PG_STATUS), \
571 SR(DOMAIN3_PG_STATUS), \
572 SR(DOMAIN16_PG_STATUS), \
573 SR(DOMAIN17_PG_STATUS), \
574 SR(DOMAIN18_PG_STATUS), \
575 SR(DOMAIN19_PG_STATUS), \
576 SR(D1VGA_CONTROL), \
577 SR(D2VGA_CONTROL), \
578 SR(D3VGA_CONTROL), \
579 SR(D4VGA_CONTROL), \
580 SR(D5VGA_CONTROL), \
581 SR(D6VGA_CONTROL), \
582 SR(DC_IP_REQUEST_CNTL), \
583 SR(AZALIA_AUDIO_DTO), \
584 SR(AZALIA_CONTROLLER_CLOCK_GATING)
585
586 static struct dce_hwseq_registers hwseq_reg;
587
588 #define hwseq_reg_init()\
589 HWSEQ_DCN32_REG_LIST()
590
591 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
592 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
593 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
594 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
595 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
596 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
597 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
598 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
599 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
600 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
601 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
602 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
603 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
604 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
605 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
606 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
607 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
608 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
609 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
610 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
614 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
615 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
616 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
617 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
618 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
619 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
620 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
621 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
622 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
623 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
624
625 static const struct dce_hwseq_shift hwseq_shift = {
626 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
627 };
628
629 static const struct dce_hwseq_mask hwseq_mask = {
630 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
631 };
632 #define vmid_regs_init(id)\
633 DCN20_VMID_REG_LIST_RI(id)
634
635 static struct dcn_vmid_registers vmid_regs[16];
636
637 static const struct dcn20_vmid_shift vmid_shifts = {
638 DCN20_VMID_MASK_SH_LIST(__SHIFT)
639 };
640
641 static const struct dcn20_vmid_mask vmid_masks = {
642 DCN20_VMID_MASK_SH_LIST(_MASK)
643 };
644
645 static const struct resource_caps res_cap_dcn32 = {
646 .num_timing_generator = 4,
647 .num_opp = 4,
648 .num_video_plane = 4,
649 .num_audio = 5,
650 .num_stream_encoder = 5,
651 .num_hpo_dp_stream_encoder = 4,
652 .num_hpo_dp_link_encoder = 2,
653 .num_pll = 5,
654 .num_dwb = 1,
655 .num_ddc = 5,
656 .num_vmid = 16,
657 .num_mpc_3dlut = 4,
658 .num_dsc = 4,
659 };
660
661 static const struct dc_plane_cap plane_cap = {
662 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
663 .per_pixel_alpha = true,
664
665 .pixel_format_support = {
666 .argb8888 = true,
667 .nv12 = true,
668 .fp16 = true,
669 .p010 = true,
670 .ayuv = false,
671 },
672
673 .max_upscale_factor = {
674 .argb8888 = 16000,
675 .nv12 = 16000,
676 .fp16 = 16000
677 },
678
679 // 6:1 downscaling ratio: 1000/6 = 166.666
680 .max_downscale_factor = {
681 .argb8888 = 167,
682 .nv12 = 167,
683 .fp16 = 167
684 },
685 64,
686 64
687 };
688
689 static const struct dc_debug_options debug_defaults_drv = {
690 .disable_dmcu = true,
691 .force_abm_enable = false,
692 .timing_trace = false,
693 .clock_trace = true,
694 .disable_pplib_clock_request = false,
695 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore
696 .force_single_disp_pipe_split = false,
697 .disable_dcc = DCC_ENABLE,
698 .vsr_support = true,
699 .performance_trace = false,
700 .max_downscale_src_width = 7680,/*upto 8K*/
701 .disable_pplib_wm_range = false,
702 .scl_reset_length10 = true,
703 .sanity_checks = false,
704 .underflow_assert_delay_us = 0xFFFFFFFF,
705 .dwb_fi_phase = -1, // -1 = disable,
706 .dmub_command_table = true,
707 .enable_mem_low_power = {
708 .bits = {
709 .vga = false,
710 .i2c = false,
711 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
712 .dscl = false,
713 .cm = false,
714 .mpc = false,
715 .optc = true,
716 }
717 },
718 .use_max_lb = true,
719 .force_disable_subvp = false,
720 .exit_idle_opt_for_cursor_updates = true,
721 .using_dml2 = false,
722 .enable_single_display_2to1_odm_policy = true,
723
724 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
725 .enable_double_buffered_dsc_pg_support = true,
726 .enable_dp_dig_pixel_rate_div_policy = 1,
727 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
728 .alloc_extra_way_for_cursor = true,
729 .min_prefetch_in_strobe_ns = 60000, // 60us
730 .disable_unbounded_requesting = false,
731 .override_dispclk_programming = true,
732 .disable_fpo_optimizations = false,
733 .fpo_vactive_margin_us = 2000, // 2000us
734 .disable_fpo_vactive = false,
735 .disable_boot_optimizations = false,
736 .disable_subvp_high_refresh = false,
737 .disable_dp_plus_plus_wa = true,
738 .fpo_vactive_min_active_margin_us = 200,
739 .fpo_vactive_max_blank_us = 1000,
740 .enable_legacy_fast_update = false,
741 };
742
dcn32_aux_engine_create(struct dc_context * ctx,uint32_t inst)743 static struct dce_aux *dcn32_aux_engine_create(
744 struct dc_context *ctx,
745 uint32_t inst)
746 {
747 struct aux_engine_dce110 *aux_engine =
748 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
749
750 if (!aux_engine)
751 return NULL;
752
753 #undef REG_STRUCT
754 #define REG_STRUCT aux_engine_regs
755 aux_engine_regs_init(0),
756 aux_engine_regs_init(1),
757 aux_engine_regs_init(2),
758 aux_engine_regs_init(3),
759 aux_engine_regs_init(4);
760
761 dce110_aux_engine_construct(aux_engine, ctx, inst,
762 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
763 &aux_engine_regs[inst],
764 &aux_mask,
765 &aux_shift,
766 ctx->dc->caps.extended_aux_timeout_support);
767
768 return &aux_engine->base;
769 }
770 #define i2c_inst_regs_init(id)\
771 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
772
773 static struct dce_i2c_registers i2c_hw_regs[5];
774
775 static const struct dce_i2c_shift i2c_shifts = {
776 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
777 };
778
779 static const struct dce_i2c_mask i2c_masks = {
780 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
781 };
782
dcn32_i2c_hw_create(struct dc_context * ctx,uint32_t inst)783 static struct dce_i2c_hw *dcn32_i2c_hw_create(
784 struct dc_context *ctx,
785 uint32_t inst)
786 {
787 struct dce_i2c_hw *dce_i2c_hw =
788 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
789
790 if (!dce_i2c_hw)
791 return NULL;
792
793 #undef REG_STRUCT
794 #define REG_STRUCT i2c_hw_regs
795 i2c_inst_regs_init(1),
796 i2c_inst_regs_init(2),
797 i2c_inst_regs_init(3),
798 i2c_inst_regs_init(4),
799 i2c_inst_regs_init(5);
800
801 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
802 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
803
804 return dce_i2c_hw;
805 }
806
dcn32_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)807 static struct clock_source *dcn32_clock_source_create(
808 struct dc_context *ctx,
809 struct dc_bios *bios,
810 enum clock_source_id id,
811 const struct dce110_clk_src_regs *regs,
812 bool dp_clk_src)
813 {
814 struct dce110_clk_src *clk_src =
815 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
816
817 if (!clk_src)
818 return NULL;
819
820 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
821 regs, &cs_shift, &cs_mask)) {
822 clk_src->base.dp_clk_src = dp_clk_src;
823 return &clk_src->base;
824 }
825
826 kfree(clk_src);
827 BREAK_TO_DEBUGGER();
828 return NULL;
829 }
830
dcn32_hubbub_create(struct dc_context * ctx)831 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
832 {
833 int i;
834
835 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
836 GFP_KERNEL);
837
838 if (!hubbub2)
839 return NULL;
840
841 #undef REG_STRUCT
842 #define REG_STRUCT hubbub_reg
843 hubbub_reg_init();
844
845 #undef REG_STRUCT
846 #define REG_STRUCT vmid_regs
847 vmid_regs_init(0),
848 vmid_regs_init(1),
849 vmid_regs_init(2),
850 vmid_regs_init(3),
851 vmid_regs_init(4),
852 vmid_regs_init(5),
853 vmid_regs_init(6),
854 vmid_regs_init(7),
855 vmid_regs_init(8),
856 vmid_regs_init(9),
857 vmid_regs_init(10),
858 vmid_regs_init(11),
859 vmid_regs_init(12),
860 vmid_regs_init(13),
861 vmid_regs_init(14),
862 vmid_regs_init(15);
863
864 hubbub32_construct(hubbub2, ctx,
865 &hubbub_reg,
866 &hubbub_shift,
867 &hubbub_mask,
868 ctx->dc->dml.ip.det_buffer_size_kbytes,
869 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
870 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
871
872
873 for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
874 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
875
876 vmid->ctx = ctx;
877
878 vmid->regs = &vmid_regs[i];
879 vmid->shifts = &vmid_shifts;
880 vmid->masks = &vmid_masks;
881 }
882
883 return &hubbub2->base;
884 }
885
dcn32_hubp_create(struct dc_context * ctx,uint32_t inst)886 static struct hubp *dcn32_hubp_create(
887 struct dc_context *ctx,
888 uint32_t inst)
889 {
890 struct dcn20_hubp *hubp2 =
891 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
892
893 if (!hubp2)
894 return NULL;
895
896 #undef REG_STRUCT
897 #define REG_STRUCT hubp_regs
898 hubp_regs_init(0),
899 hubp_regs_init(1),
900 hubp_regs_init(2),
901 hubp_regs_init(3);
902
903 if (hubp32_construct(hubp2, ctx, inst,
904 &hubp_regs[inst], &hubp_shift, &hubp_mask))
905 return &hubp2->base;
906
907 BREAK_TO_DEBUGGER();
908 kfree(hubp2);
909 return NULL;
910 }
911
dcn32_dpp_destroy(struct dpp ** dpp)912 static void dcn32_dpp_destroy(struct dpp **dpp)
913 {
914 kfree(TO_DCN30_DPP(*dpp));
915 *dpp = NULL;
916 }
917
dcn32_dpp_create(struct dc_context * ctx,uint32_t inst)918 static struct dpp *dcn32_dpp_create(
919 struct dc_context *ctx,
920 uint32_t inst)
921 {
922 struct dcn3_dpp *dpp3 =
923 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
924
925 if (!dpp3)
926 return NULL;
927
928 #undef REG_STRUCT
929 #define REG_STRUCT dpp_regs
930 dpp_regs_init(0),
931 dpp_regs_init(1),
932 dpp_regs_init(2),
933 dpp_regs_init(3);
934
935 if (dpp32_construct(dpp3, ctx, inst,
936 &dpp_regs[inst], &tf_shift, &tf_mask))
937 return &dpp3->base;
938
939 BREAK_TO_DEBUGGER();
940 kfree(dpp3);
941 return NULL;
942 }
943
dcn32_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)944 static struct mpc *dcn32_mpc_create(
945 struct dc_context *ctx,
946 int num_mpcc,
947 int num_rmu)
948 {
949 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
950 GFP_KERNEL);
951
952 if (!mpc30)
953 return NULL;
954
955 #undef REG_STRUCT
956 #define REG_STRUCT mpc_regs
957 dcn_mpc_regs_init();
958
959 dcn32_mpc_construct(mpc30, ctx,
960 &mpc_regs,
961 &mpc_shift,
962 &mpc_mask,
963 num_mpcc,
964 num_rmu);
965
966 return &mpc30->base;
967 }
968
dcn32_opp_create(struct dc_context * ctx,uint32_t inst)969 static struct output_pixel_processor *dcn32_opp_create(
970 struct dc_context *ctx, uint32_t inst)
971 {
972 struct dcn20_opp *opp2 =
973 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
974
975 if (!opp2) {
976 BREAK_TO_DEBUGGER();
977 return NULL;
978 }
979
980 #undef REG_STRUCT
981 #define REG_STRUCT opp_regs
982 opp_regs_init(0),
983 opp_regs_init(1),
984 opp_regs_init(2),
985 opp_regs_init(3);
986
987 dcn20_opp_construct(opp2, ctx, inst,
988 &opp_regs[inst], &opp_shift, &opp_mask);
989 return &opp2->base;
990 }
991
992
dcn32_timing_generator_create(struct dc_context * ctx,uint32_t instance)993 static struct timing_generator *dcn32_timing_generator_create(
994 struct dc_context *ctx,
995 uint32_t instance)
996 {
997 struct optc *tgn10 =
998 kzalloc(sizeof(struct optc), GFP_KERNEL);
999
1000 if (!tgn10)
1001 return NULL;
1002
1003 #undef REG_STRUCT
1004 #define REG_STRUCT optc_regs
1005 optc_regs_init(0),
1006 optc_regs_init(1),
1007 optc_regs_init(2),
1008 optc_regs_init(3);
1009
1010 tgn10->base.inst = instance;
1011 tgn10->base.ctx = ctx;
1012
1013 tgn10->tg_regs = &optc_regs[instance];
1014 tgn10->tg_shift = &optc_shift;
1015 tgn10->tg_mask = &optc_mask;
1016
1017 dcn32_timing_generator_init(tgn10);
1018
1019 return &tgn10->base;
1020 }
1021
1022 static const struct encoder_feature_support link_enc_feature = {
1023 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1024 .max_hdmi_pixel_clock = 600000,
1025 .hdmi_ycbcr420_supported = true,
1026 .dp_ycbcr420_supported = true,
1027 .fec_supported = true,
1028 .flags.bits.IS_HBR2_CAPABLE = true,
1029 .flags.bits.IS_HBR3_CAPABLE = true,
1030 .flags.bits.IS_TPS3_CAPABLE = true,
1031 .flags.bits.IS_TPS4_CAPABLE = true
1032 };
1033
dcn32_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1034 static struct link_encoder *dcn32_link_encoder_create(
1035 struct dc_context *ctx,
1036 const struct encoder_init_data *enc_init_data)
1037 {
1038 struct dcn20_link_encoder *enc20 =
1039 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1040
1041 if (!enc20)
1042 return NULL;
1043
1044 #undef REG_STRUCT
1045 #define REG_STRUCT link_enc_aux_regs
1046 aux_regs_init(0),
1047 aux_regs_init(1),
1048 aux_regs_init(2),
1049 aux_regs_init(3),
1050 aux_regs_init(4);
1051
1052 #undef REG_STRUCT
1053 #define REG_STRUCT link_enc_hpd_regs
1054 hpd_regs_init(0),
1055 hpd_regs_init(1),
1056 hpd_regs_init(2),
1057 hpd_regs_init(3),
1058 hpd_regs_init(4);
1059
1060 #undef REG_STRUCT
1061 #define REG_STRUCT link_enc_regs
1062 link_regs_init(0, A),
1063 link_regs_init(1, B),
1064 link_regs_init(2, C),
1065 link_regs_init(3, D),
1066 link_regs_init(4, E);
1067
1068 dcn32_link_encoder_construct(enc20,
1069 enc_init_data,
1070 &link_enc_feature,
1071 &link_enc_regs[enc_init_data->transmitter],
1072 &link_enc_aux_regs[enc_init_data->channel - 1],
1073 &link_enc_hpd_regs[enc_init_data->hpd_source],
1074 &le_shift,
1075 &le_mask);
1076
1077 return &enc20->enc10.base;
1078 }
1079
dcn32_panel_cntl_create(const struct panel_cntl_init_data * init_data)1080 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1081 {
1082 struct dcn31_panel_cntl *panel_cntl =
1083 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1084
1085 if (!panel_cntl)
1086 return NULL;
1087
1088 dcn31_panel_cntl_construct(panel_cntl, init_data);
1089
1090 return &panel_cntl->base;
1091 }
1092
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1093 static void read_dce_straps(
1094 struct dc_context *ctx,
1095 struct resource_straps *straps)
1096 {
1097 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1098 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1099
1100 }
1101
dcn32_create_audio(struct dc_context * ctx,unsigned int inst)1102 static struct audio *dcn32_create_audio(
1103 struct dc_context *ctx, unsigned int inst)
1104 {
1105
1106 #undef REG_STRUCT
1107 #define REG_STRUCT audio_regs
1108 audio_regs_init(0),
1109 audio_regs_init(1),
1110 audio_regs_init(2),
1111 audio_regs_init(3),
1112 audio_regs_init(4);
1113
1114 return dce_audio_create(ctx, inst,
1115 &audio_regs[inst], &audio_shift, &audio_mask);
1116 }
1117
dcn32_vpg_create(struct dc_context * ctx,uint32_t inst)1118 static struct vpg *dcn32_vpg_create(
1119 struct dc_context *ctx,
1120 uint32_t inst)
1121 {
1122 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1123
1124 if (!vpg3)
1125 return NULL;
1126
1127 #undef REG_STRUCT
1128 #define REG_STRUCT vpg_regs
1129 vpg_regs_init(0),
1130 vpg_regs_init(1),
1131 vpg_regs_init(2),
1132 vpg_regs_init(3),
1133 vpg_regs_init(4),
1134 vpg_regs_init(5),
1135 vpg_regs_init(6),
1136 vpg_regs_init(7),
1137 vpg_regs_init(8),
1138 vpg_regs_init(9);
1139
1140 vpg3_construct(vpg3, ctx, inst,
1141 &vpg_regs[inst],
1142 &vpg_shift,
1143 &vpg_mask);
1144
1145 return &vpg3->base;
1146 }
1147
dcn32_afmt_create(struct dc_context * ctx,uint32_t inst)1148 static struct afmt *dcn32_afmt_create(
1149 struct dc_context *ctx,
1150 uint32_t inst)
1151 {
1152 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1153
1154 if (!afmt3)
1155 return NULL;
1156
1157 #undef REG_STRUCT
1158 #define REG_STRUCT afmt_regs
1159 afmt_regs_init(0),
1160 afmt_regs_init(1),
1161 afmt_regs_init(2),
1162 afmt_regs_init(3),
1163 afmt_regs_init(4),
1164 afmt_regs_init(5);
1165
1166 afmt3_construct(afmt3, ctx, inst,
1167 &afmt_regs[inst],
1168 &afmt_shift,
1169 &afmt_mask);
1170
1171 return &afmt3->base;
1172 }
1173
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1174 static struct apg *dcn31_apg_create(
1175 struct dc_context *ctx,
1176 uint32_t inst)
1177 {
1178 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1179
1180 if (!apg31)
1181 return NULL;
1182
1183 #undef REG_STRUCT
1184 #define REG_STRUCT apg_regs
1185 apg_regs_init(0),
1186 apg_regs_init(1),
1187 apg_regs_init(2),
1188 apg_regs_init(3);
1189
1190 apg31_construct(apg31, ctx, inst,
1191 &apg_regs[inst],
1192 &apg_shift,
1193 &apg_mask);
1194
1195 return &apg31->base;
1196 }
1197
dcn32_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1198 static struct stream_encoder *dcn32_stream_encoder_create(
1199 enum engine_id eng_id,
1200 struct dc_context *ctx)
1201 {
1202 struct dcn10_stream_encoder *enc1;
1203 struct vpg *vpg;
1204 struct afmt *afmt;
1205 int vpg_inst;
1206 int afmt_inst;
1207
1208 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1209 if (eng_id <= ENGINE_ID_DIGF) {
1210 vpg_inst = eng_id;
1211 afmt_inst = eng_id;
1212 } else
1213 return NULL;
1214
1215 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1216 vpg = dcn32_vpg_create(ctx, vpg_inst);
1217 afmt = dcn32_afmt_create(ctx, afmt_inst);
1218
1219 if (!enc1 || !vpg || !afmt) {
1220 kfree(enc1);
1221 kfree(vpg);
1222 kfree(afmt);
1223 return NULL;
1224 }
1225
1226 #undef REG_STRUCT
1227 #define REG_STRUCT stream_enc_regs
1228 stream_enc_regs_init(0),
1229 stream_enc_regs_init(1),
1230 stream_enc_regs_init(2),
1231 stream_enc_regs_init(3),
1232 stream_enc_regs_init(4);
1233
1234 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1235 eng_id, vpg, afmt,
1236 &stream_enc_regs[eng_id],
1237 &se_shift, &se_mask);
1238
1239 return &enc1->base;
1240 }
1241
dcn32_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1242 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1243 enum engine_id eng_id,
1244 struct dc_context *ctx)
1245 {
1246 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1247 struct vpg *vpg;
1248 struct apg *apg;
1249 uint32_t hpo_dp_inst;
1250 uint32_t vpg_inst;
1251 uint32_t apg_inst;
1252
1253 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1254 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1255
1256 /* Mapping of VPG register blocks to HPO DP block instance:
1257 * VPG[6] -> HPO_DP[0]
1258 * VPG[7] -> HPO_DP[1]
1259 * VPG[8] -> HPO_DP[2]
1260 * VPG[9] -> HPO_DP[3]
1261 */
1262 vpg_inst = hpo_dp_inst + 6;
1263
1264 /* Mapping of APG register blocks to HPO DP block instance:
1265 * APG[0] -> HPO_DP[0]
1266 * APG[1] -> HPO_DP[1]
1267 * APG[2] -> HPO_DP[2]
1268 * APG[3] -> HPO_DP[3]
1269 */
1270 apg_inst = hpo_dp_inst;
1271
1272 /* allocate HPO stream encoder and create VPG sub-block */
1273 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1274 vpg = dcn32_vpg_create(ctx, vpg_inst);
1275 apg = dcn31_apg_create(ctx, apg_inst);
1276
1277 if (!hpo_dp_enc31 || !vpg || !apg) {
1278 kfree(hpo_dp_enc31);
1279 kfree(vpg);
1280 kfree(apg);
1281 return NULL;
1282 }
1283
1284 #undef REG_STRUCT
1285 #define REG_STRUCT hpo_dp_stream_enc_regs
1286 hpo_dp_stream_encoder_reg_init(0),
1287 hpo_dp_stream_encoder_reg_init(1),
1288 hpo_dp_stream_encoder_reg_init(2),
1289 hpo_dp_stream_encoder_reg_init(3);
1290
1291 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1292 hpo_dp_inst, eng_id, vpg, apg,
1293 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1294 &hpo_dp_se_shift, &hpo_dp_se_mask);
1295
1296 return &hpo_dp_enc31->base;
1297 }
1298
dcn32_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1299 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1300 uint8_t inst,
1301 struct dc_context *ctx)
1302 {
1303 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1304
1305 /* allocate HPO link encoder */
1306 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1307
1308 #undef REG_STRUCT
1309 #define REG_STRUCT hpo_dp_link_enc_regs
1310 hpo_dp_link_encoder_reg_init(0),
1311 hpo_dp_link_encoder_reg_init(1);
1312
1313 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1314 &hpo_dp_link_enc_regs[inst],
1315 &hpo_dp_le_shift, &hpo_dp_le_mask);
1316
1317 return &hpo_dp_enc31->base;
1318 }
1319
dcn32_hwseq_create(struct dc_context * ctx)1320 static struct dce_hwseq *dcn32_hwseq_create(
1321 struct dc_context *ctx)
1322 {
1323 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1324
1325 #undef REG_STRUCT
1326 #define REG_STRUCT hwseq_reg
1327 hwseq_reg_init();
1328
1329 if (hws) {
1330 hws->ctx = ctx;
1331 hws->regs = &hwseq_reg;
1332 hws->shifts = &hwseq_shift;
1333 hws->masks = &hwseq_mask;
1334 }
1335 return hws;
1336 }
1337 static const struct resource_create_funcs res_create_funcs = {
1338 .read_dce_straps = read_dce_straps,
1339 .create_audio = dcn32_create_audio,
1340 .create_stream_encoder = dcn32_stream_encoder_create,
1341 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1342 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1343 .create_hwseq = dcn32_hwseq_create,
1344 };
1345
dcn32_resource_destruct(struct dcn32_resource_pool * pool)1346 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1347 {
1348 unsigned int i;
1349
1350 for (i = 0; i < pool->base.stream_enc_count; i++) {
1351 if (pool->base.stream_enc[i] != NULL) {
1352 if (pool->base.stream_enc[i]->vpg != NULL) {
1353 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1354 pool->base.stream_enc[i]->vpg = NULL;
1355 }
1356 if (pool->base.stream_enc[i]->afmt != NULL) {
1357 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1358 pool->base.stream_enc[i]->afmt = NULL;
1359 }
1360 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1361 pool->base.stream_enc[i] = NULL;
1362 }
1363 }
1364
1365 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1366 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1367 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1368 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1369 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1370 }
1371 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1372 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1373 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1374 }
1375 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1376 pool->base.hpo_dp_stream_enc[i] = NULL;
1377 }
1378 }
1379
1380 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1381 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1382 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1383 pool->base.hpo_dp_link_enc[i] = NULL;
1384 }
1385 }
1386
1387 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1388 if (pool->base.dscs[i] != NULL)
1389 dcn20_dsc_destroy(&pool->base.dscs[i]);
1390 }
1391
1392 if (pool->base.mpc != NULL) {
1393 kfree(TO_DCN20_MPC(pool->base.mpc));
1394 pool->base.mpc = NULL;
1395 }
1396 if (pool->base.hubbub != NULL) {
1397 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1398 pool->base.hubbub = NULL;
1399 }
1400 for (i = 0; i < pool->base.pipe_count; i++) {
1401 if (pool->base.dpps[i] != NULL)
1402 dcn32_dpp_destroy(&pool->base.dpps[i]);
1403
1404 if (pool->base.ipps[i] != NULL)
1405 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1406
1407 if (pool->base.hubps[i] != NULL) {
1408 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1409 pool->base.hubps[i] = NULL;
1410 }
1411
1412 if (pool->base.irqs != NULL) {
1413 dal_irq_service_destroy(&pool->base.irqs);
1414 }
1415 }
1416
1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1418 if (pool->base.engines[i] != NULL)
1419 dce110_engine_destroy(&pool->base.engines[i]);
1420 if (pool->base.hw_i2cs[i] != NULL) {
1421 kfree(pool->base.hw_i2cs[i]);
1422 pool->base.hw_i2cs[i] = NULL;
1423 }
1424 if (pool->base.sw_i2cs[i] != NULL) {
1425 kfree(pool->base.sw_i2cs[i]);
1426 pool->base.sw_i2cs[i] = NULL;
1427 }
1428 }
1429
1430 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1431 if (pool->base.opps[i] != NULL)
1432 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1433 }
1434
1435 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1436 if (pool->base.timing_generators[i] != NULL) {
1437 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1438 pool->base.timing_generators[i] = NULL;
1439 }
1440 }
1441
1442 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1443 if (pool->base.dwbc[i] != NULL) {
1444 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1445 pool->base.dwbc[i] = NULL;
1446 }
1447 if (pool->base.mcif_wb[i] != NULL) {
1448 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1449 pool->base.mcif_wb[i] = NULL;
1450 }
1451 }
1452
1453 for (i = 0; i < pool->base.audio_count; i++) {
1454 if (pool->base.audios[i])
1455 dce_aud_destroy(&pool->base.audios[i]);
1456 }
1457
1458 for (i = 0; i < pool->base.clk_src_count; i++) {
1459 if (pool->base.clock_sources[i] != NULL) {
1460 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1461 pool->base.clock_sources[i] = NULL;
1462 }
1463 }
1464
1465 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1466 if (pool->base.mpc_lut[i] != NULL) {
1467 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1468 pool->base.mpc_lut[i] = NULL;
1469 }
1470 if (pool->base.mpc_shaper[i] != NULL) {
1471 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1472 pool->base.mpc_shaper[i] = NULL;
1473 }
1474 }
1475
1476 if (pool->base.dp_clock_source != NULL) {
1477 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1478 pool->base.dp_clock_source = NULL;
1479 }
1480
1481 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1482 if (pool->base.multiple_abms[i] != NULL)
1483 dce_abm_destroy(&pool->base.multiple_abms[i]);
1484 }
1485
1486 if (pool->base.psr != NULL)
1487 dmub_psr_destroy(&pool->base.psr);
1488
1489 if (pool->base.dccg != NULL)
1490 dcn_dccg_destroy(&pool->base.dccg);
1491
1492 if (pool->base.oem_device != NULL) {
1493 struct dc *dc = pool->base.oem_device->ctx->dc;
1494
1495 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1496 }
1497 }
1498
1499
dcn32_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1500 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1501 {
1502 int i;
1503 uint32_t dwb_count = pool->res_cap->num_dwb;
1504
1505 for (i = 0; i < dwb_count; i++) {
1506 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1507 GFP_KERNEL);
1508
1509 if (!dwbc30) {
1510 dm_error("DC: failed to create dwbc30!\n");
1511 return false;
1512 }
1513
1514 #undef REG_STRUCT
1515 #define REG_STRUCT dwbc30_regs
1516 dwbc_regs_dcn3_init(0);
1517
1518 dcn30_dwbc_construct(dwbc30, ctx,
1519 &dwbc30_regs[i],
1520 &dwbc30_shift,
1521 &dwbc30_mask,
1522 i);
1523
1524 pool->dwbc[i] = &dwbc30->base;
1525 }
1526 return true;
1527 }
1528
dcn32_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1529 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1530 {
1531 int i;
1532 uint32_t dwb_count = pool->res_cap->num_dwb;
1533
1534 for (i = 0; i < dwb_count; i++) {
1535 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1536 GFP_KERNEL);
1537
1538 if (!mcif_wb30) {
1539 dm_error("DC: failed to create mcif_wb30!\n");
1540 return false;
1541 }
1542
1543 #undef REG_STRUCT
1544 #define REG_STRUCT mcif_wb30_regs
1545 mcif_wb_regs_dcn3_init(0);
1546
1547 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1548 &mcif_wb30_regs[i],
1549 &mcif_wb30_shift,
1550 &mcif_wb30_mask,
1551 i);
1552
1553 pool->mcif_wb[i] = &mcif_wb30->base;
1554 }
1555 return true;
1556 }
1557
dcn32_dsc_create(struct dc_context * ctx,uint32_t inst)1558 static struct display_stream_compressor *dcn32_dsc_create(
1559 struct dc_context *ctx, uint32_t inst)
1560 {
1561 struct dcn20_dsc *dsc =
1562 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1563
1564 if (!dsc) {
1565 BREAK_TO_DEBUGGER();
1566 return NULL;
1567 }
1568
1569 #undef REG_STRUCT
1570 #define REG_STRUCT dsc_regs
1571 dsc_regsDCN20_init(0),
1572 dsc_regsDCN20_init(1),
1573 dsc_regsDCN20_init(2),
1574 dsc_regsDCN20_init(3);
1575
1576 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1577
1578 dsc->max_image_width = 6016;
1579
1580 return &dsc->base;
1581 }
1582
dcn32_destroy_resource_pool(struct resource_pool ** pool)1583 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1584 {
1585 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1586
1587 dcn32_resource_destruct(dcn32_pool);
1588 kfree(dcn32_pool);
1589 *pool = NULL;
1590 }
1591
dcn32_acquire_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,int mpcc_id,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1592 bool dcn32_acquire_post_bldn_3dlut(
1593 struct resource_context *res_ctx,
1594 const struct resource_pool *pool,
1595 int mpcc_id,
1596 struct dc_3dlut **lut,
1597 struct dc_transfer_func **shaper)
1598 {
1599 bool ret = false;
1600
1601 ASSERT(*lut == NULL && *shaper == NULL);
1602 *lut = NULL;
1603 *shaper = NULL;
1604
1605 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1606 *lut = pool->mpc_lut[mpcc_id];
1607 *shaper = pool->mpc_shaper[mpcc_id];
1608 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1609 ret = true;
1610 }
1611 return ret;
1612 }
1613
dcn32_release_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1614 bool dcn32_release_post_bldn_3dlut(
1615 struct resource_context *res_ctx,
1616 const struct resource_pool *pool,
1617 struct dc_3dlut **lut,
1618 struct dc_transfer_func **shaper)
1619 {
1620 int i;
1621 bool ret = false;
1622
1623 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1624 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1625 res_ctx->is_mpc_3dlut_acquired[i] = false;
1626 pool->mpc_lut[i]->state.raw = 0;
1627 *lut = NULL;
1628 *shaper = NULL;
1629 ret = true;
1630 break;
1631 }
1632 }
1633 return ret;
1634 }
1635
dcn32_enable_phantom_plane(struct dc * dc,struct dc_state * context,struct dc_stream_state * phantom_stream,unsigned int dc_pipe_idx)1636 static void dcn32_enable_phantom_plane(struct dc *dc,
1637 struct dc_state *context,
1638 struct dc_stream_state *phantom_stream,
1639 unsigned int dc_pipe_idx)
1640 {
1641 struct dc_plane_state *phantom_plane = NULL;
1642 struct dc_plane_state *prev_phantom_plane = NULL;
1643 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1644
1645 while (curr_pipe) {
1646 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1647 phantom_plane = prev_phantom_plane;
1648 else
1649 phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);
1650
1651 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1652 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1653 sizeof(phantom_plane->scaling_quality));
1654 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1655 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1656 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1657 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1658 sizeof(phantom_plane->plane_size));
1659 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1660 sizeof(phantom_plane->tiling_info));
1661 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1662 phantom_plane->format = curr_pipe->plane_state->format;
1663 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1664 phantom_plane->visible = curr_pipe->plane_state->visible;
1665
1666 /* Shadow pipe has small viewport. */
1667 phantom_plane->clip_rect.y = 0;
1668 phantom_plane->clip_rect.height = phantom_stream->src.height;
1669
1670 dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);
1671
1672 curr_pipe = curr_pipe->bottom_pipe;
1673 prev_phantom_plane = phantom_plane;
1674 }
1675 }
1676
dcn32_enable_phantom_stream(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int dc_pipe_idx)1677 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
1678 struct dc_state *context,
1679 display_e2e_pipe_params_st *pipes,
1680 unsigned int pipe_cnt,
1681 unsigned int dc_pipe_idx)
1682 {
1683 struct dc_stream_state *phantom_stream = NULL;
1684 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1685
1686 phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);
1687
1688 /* stream has limited viewport and small timing */
1689 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
1690 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
1691 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
1692 DC_FP_START();
1693 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
1694 DC_FP_END();
1695
1696 dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);
1697 return phantom_stream;
1698 }
1699
1700 /* TODO: Input to this function should indicate which pipe indexes (or streams)
1701 * require a phantom pipe / stream
1702 */
dcn32_add_phantom_pipes(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int index)1703 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
1704 display_e2e_pipe_params_st *pipes,
1705 unsigned int pipe_cnt,
1706 unsigned int index)
1707 {
1708 struct dc_stream_state *phantom_stream = NULL;
1709 unsigned int i;
1710
1711 // The index of the DC pipe passed into this function is guarenteed to
1712 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
1713 // already have phantom pipe assigned, etc.) by previous checks.
1714 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
1715 dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
1716
1717 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1718 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1719
1720 // Build scaling params for phantom pipes which were newly added.
1721 // We determine which phantom pipes were added by comparing with
1722 // the phantom stream.
1723 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
1724 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
1725 pipe->stream->use_dynamic_meta = false;
1726 pipe->plane_state->flip_immediate = false;
1727 if (!resource_build_scaling_params(pipe)) {
1728 // Log / remove phantom pipes since failed to build scaling params
1729 }
1730 }
1731 }
1732 }
1733
dml1_validate(struct dc * dc,struct dc_state * context,bool fast_validate)1734 static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_validate)
1735 {
1736 bool out = false;
1737
1738 BW_VAL_TRACE_SETUP();
1739
1740 int vlevel = 0;
1741 int pipe_cnt = 0;
1742 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1743
1744 /* To handle Freesync properly, setting FreeSync DML parameters
1745 * to its default state for the first stage of validation
1746 */
1747 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
1748 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1749
1750 DC_LOGGER_INIT(dc->ctx->logger);
1751
1752 BW_VAL_TRACE_COUNT();
1753
1754 DC_FP_START();
1755 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1756 DC_FP_END();
1757
1758 if (pipe_cnt == 0)
1759 goto validate_out;
1760
1761 if (!out)
1762 goto validate_fail;
1763
1764 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1765
1766 if (fast_validate) {
1767 BW_VAL_TRACE_SKIP(fast);
1768 goto validate_out;
1769 }
1770
1771 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1772
1773 dcn32_override_min_req_memclk(dc, context);
1774
1775 BW_VAL_TRACE_END_WATERMARKS();
1776
1777 goto validate_out;
1778
1779 validate_fail:
1780 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1781 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1782
1783 BW_VAL_TRACE_SKIP(fail);
1784 out = false;
1785
1786 validate_out:
1787 kfree(pipes);
1788
1789 BW_VAL_TRACE_FINISH();
1790
1791 return out;
1792 }
1793
dcn32_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1794 bool dcn32_validate_bandwidth(struct dc *dc,
1795 struct dc_state *context,
1796 bool fast_validate)
1797 {
1798 bool out = false;
1799
1800 if (dc->debug.using_dml2)
1801 out = dml2_validate(dc, context, fast_validate);
1802 else
1803 out = dml1_validate(dc, context, fast_validate);
1804 return out;
1805 }
1806
dcn32_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1807 int dcn32_populate_dml_pipes_from_context(
1808 struct dc *dc, struct dc_state *context,
1809 display_e2e_pipe_params_st *pipes,
1810 bool fast_validate)
1811 {
1812 int i, pipe_cnt;
1813 struct resource_context *res_ctx = &context->res_ctx;
1814 struct pipe_ctx *pipe = NULL;
1815 bool subvp_in_use = false;
1816 struct dc_crtc_timing *timing;
1817
1818 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1819
1820 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1821
1822 if (!res_ctx->pipe_ctx[i].stream)
1823 continue;
1824 pipe = &res_ctx->pipe_ctx[i];
1825 timing = &pipe->stream->timing;
1826
1827 pipes[pipe_cnt].pipe.src.gpuvm = true;
1828 DC_FP_START();
1829 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1830 DC_FP_END();
1831 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1832 if (dc->config.enable_windowed_mpo_odm &&
1833 dc->debug.enable_single_display_2to1_odm_policy) {
1834 switch (resource_get_odm_slice_count(pipe)) {
1835 case 2:
1836 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1837 break;
1838 case 4:
1839 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;
1840 break;
1841 default:
1842 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1843 }
1844 } else {
1845 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1846 }
1847 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
1848 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1849 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
1850
1851 /* Only populate DML input with subvp info for full updates.
1852 * This is just a workaround -- needs a proper fix.
1853 */
1854 if (!fast_validate) {
1855 switch (dc_state_get_pipe_subvp_type(context, pipe)) {
1856 case SUBVP_MAIN:
1857 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
1858 subvp_in_use = true;
1859 break;
1860 case SUBVP_PHANTOM:
1861 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
1862 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1863 // Disallow unbounded req for SubVP according to DCHUB programming guide
1864 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1865 break;
1866 case SUBVP_NONE:
1867 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
1868 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1869 break;
1870 default:
1871 break;
1872 }
1873 }
1874
1875 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1876 if (pipes[pipe_cnt].dout.dsc_enable) {
1877 switch (timing->display_color_depth) {
1878 case COLOR_DEPTH_888:
1879 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1880 break;
1881 case COLOR_DEPTH_101010:
1882 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1883 break;
1884 case COLOR_DEPTH_121212:
1885 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1886 break;
1887 default:
1888 ASSERT(0);
1889 break;
1890 }
1891 }
1892
1893
1894 pipe_cnt++;
1895 }
1896
1897 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
1898 * the DET available for each pipe). Use the DET override input to maintain our driver
1899 * policy.
1900 */
1901 dcn32_set_det_allocations(dc, context, pipes);
1902
1903 // In general cases we want to keep the dram clock change requirement
1904 // (prefer configs that support MCLK switch). Only override to false
1905 // for SubVP
1906 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)
1907 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
1908 else
1909 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1910
1911 return pipe_cnt;
1912 }
1913
1914 static struct dc_cap_funcs cap_funcs = {
1915 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1916 .get_subvp_en = dcn32_subvp_in_use,
1917 };
1918
dcn32_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1919 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
1920 display_e2e_pipe_params_st *pipes,
1921 int pipe_cnt,
1922 int vlevel)
1923 {
1924 DC_FP_START();
1925 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);
1926 DC_FP_END();
1927 }
1928
dcn32_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1929 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1930 {
1931 DC_FP_START();
1932 dcn32_update_bw_bounding_box_fpu(dc, bw_params);
1933 DC_FP_END();
1934 }
1935
1936 static struct resource_funcs dcn32_res_pool_funcs = {
1937 .destroy = dcn32_destroy_resource_pool,
1938 .link_enc_create = dcn32_link_encoder_create,
1939 .link_enc_create_minimal = NULL,
1940 .panel_cntl_create = dcn32_panel_cntl_create,
1941 .validate_bandwidth = dcn32_validate_bandwidth,
1942 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
1943 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
1944 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1945 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1946 .release_pipe = dcn20_release_pipe,
1947 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1948 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1949 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1950 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1951 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1952 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1953 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1954 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1955 .update_bw_bounding_box = dcn32_update_bw_bounding_box,
1956 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1957 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1958 .add_phantom_pipes = dcn32_add_phantom_pipes,
1959 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1960 };
1961
read_pipe_fuses(struct dc_context * ctx)1962 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1963 {
1964 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1965 /* DCN32 support max 4 pipes */
1966 value = value & 0xf;
1967 return value;
1968 }
1969
1970
dcn32_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn32_resource_pool * pool)1971 static bool dcn32_resource_construct(
1972 uint8_t num_virtual_links,
1973 struct dc *dc,
1974 struct dcn32_resource_pool *pool)
1975 {
1976 int i, j;
1977 struct dc_context *ctx = dc->ctx;
1978 struct irq_service_init_data init_data;
1979 struct ddc_service_init_data ddc_init_data = {0};
1980 uint32_t pipe_fuses = 0;
1981 uint32_t num_pipes = 4;
1982
1983 #undef REG_STRUCT
1984 #define REG_STRUCT bios_regs
1985 bios_regs_init();
1986
1987 #undef REG_STRUCT
1988 #define REG_STRUCT clk_src_regs
1989 clk_src_regs_init(0, A),
1990 clk_src_regs_init(1, B),
1991 clk_src_regs_init(2, C),
1992 clk_src_regs_init(3, D),
1993 clk_src_regs_init(4, E);
1994
1995 #undef REG_STRUCT
1996 #define REG_STRUCT abm_regs
1997 abm_regs_init(0),
1998 abm_regs_init(1),
1999 abm_regs_init(2),
2000 abm_regs_init(3);
2001
2002 #undef REG_STRUCT
2003 #define REG_STRUCT dccg_regs
2004 dccg_regs_init();
2005
2006 DC_FP_START();
2007
2008 ctx->dc_bios->regs = &bios_regs;
2009
2010 pool->base.res_cap = &res_cap_dcn32;
2011 /* max number of pipes for ASIC before checking for pipe fuses */
2012 num_pipes = pool->base.res_cap->num_timing_generator;
2013 pipe_fuses = read_pipe_fuses(ctx);
2014
2015 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
2016 if (pipe_fuses & 1 << i)
2017 num_pipes--;
2018
2019 if (pipe_fuses & 1)
2020 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2021
2022 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2023 ASSERT(0); //Entire DCN is harvested!
2024
2025 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
2026 * value will be changed, update max_num_dpp and max_num_otg for dml.
2027 */
2028 dcn3_2_ip.max_num_dpp = num_pipes;
2029 dcn3_2_ip.max_num_otg = num_pipes;
2030
2031 pool->base.funcs = &dcn32_res_pool_funcs;
2032
2033 /*************************************************
2034 * Resource + asic cap harcoding *
2035 *************************************************/
2036 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2037 pool->base.timing_generator_count = num_pipes;
2038 pool->base.pipe_count = num_pipes;
2039 pool->base.mpcc_count = num_pipes;
2040 dc->caps.max_downscale_ratio = 600;
2041 dc->caps.i2c_speed_in_khz = 100;
2042 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
2043 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/
2044 dc->caps.max_cursor_size = 64;
2045 dc->caps.min_horizontal_blanking_period = 80;
2046 dc->caps.dmdata_alloc_size = 2048;
2047 dc->caps.mall_size_per_mem_channel = 4;
2048 dc->caps.mall_size_total = 0;
2049 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2050
2051 dc->caps.cache_line_size = 64;
2052 dc->caps.cache_num_ways = 16;
2053
2054 /* Calculate the available MALL space */
2055 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
2056 dc, dc->ctx->dc_bios->vram_info.num_chans) *
2057 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
2058 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
2059
2060 dc->caps.subvp_fw_processing_delay_us = 15;
2061 dc->caps.subvp_drr_max_vblank_margin_us = 40;
2062 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2063 dc->caps.subvp_swath_height_margin_lines = 16;
2064 dc->caps.subvp_pstate_allow_width_us = 20;
2065 dc->caps.subvp_vertical_int_margin_us = 30;
2066 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
2067
2068 dc->caps.max_slave_planes = 2;
2069 dc->caps.max_slave_yuv_planes = 2;
2070 dc->caps.max_slave_rgb_planes = 2;
2071 dc->caps.post_blend_color_processing = true;
2072 dc->caps.force_dp_tps4_for_cp2520 = true;
2073 if (dc->config.forceHBR2CP2520)
2074 dc->caps.force_dp_tps4_for_cp2520 = false;
2075 dc->caps.dp_hpo = true;
2076 dc->caps.dp_hdmi21_pcon_support = true;
2077 dc->caps.edp_dsc_support = true;
2078 dc->caps.extended_aux_timeout_support = true;
2079 dc->caps.dmcub_support = true;
2080 dc->caps.seamless_odm = true;
2081 dc->caps.max_v_total = (1 << 15) - 1;
2082
2083 /* Color pipeline capabilities */
2084 dc->caps.color.dpp.dcn_arch = 1;
2085 dc->caps.color.dpp.input_lut_shared = 0;
2086 dc->caps.color.dpp.icsc = 1;
2087 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2088 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2089 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2090 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2091 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2092 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2093 dc->caps.color.dpp.post_csc = 1;
2094 dc->caps.color.dpp.gamma_corr = 1;
2095 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2096
2097 dc->caps.color.dpp.hw_3d_lut = 1;
2098 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2099 // no OGAM ROM on DCN2 and later ASICs
2100 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2101 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2102 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2103 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2104 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2105 dc->caps.color.dpp.ocsc = 0;
2106
2107 dc->caps.color.mpc.gamut_remap = 1;
2108 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2109 dc->caps.color.mpc.ogam_ram = 1;
2110 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2111 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2112 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2113 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2114 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2115 dc->caps.color.mpc.ocsc = 1;
2116
2117 /* Use pipe context based otg sync logic */
2118 dc->config.use_pipe_ctx_sync_logic = true;
2119
2120 dc->config.dc_mode_clk_limit_support = true;
2121 /* read VBIOS LTTPR caps */
2122 {
2123 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2124 enum bp_result bp_query_result;
2125 uint8_t is_vbios_lttpr_enable = 0;
2126
2127 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2128 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2129 }
2130
2131 /* interop bit is implicit */
2132 {
2133 dc->caps.vbios_lttpr_aware = true;
2134 }
2135 }
2136
2137 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2138 dc->debug = debug_defaults_drv;
2139
2140 // Init the vm_helper
2141 if (dc->vm_helper)
2142 vm_helper_init(dc->vm_helper, 16);
2143
2144 /*************************************************
2145 * Create resources *
2146 *************************************************/
2147
2148 /* Clock Sources for Pixel Clock*/
2149 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
2150 dcn32_clock_source_create(ctx, ctx->dc_bios,
2151 CLOCK_SOURCE_COMBO_PHY_PLL0,
2152 &clk_src_regs[0], false);
2153 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
2154 dcn32_clock_source_create(ctx, ctx->dc_bios,
2155 CLOCK_SOURCE_COMBO_PHY_PLL1,
2156 &clk_src_regs[1], false);
2157 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
2158 dcn32_clock_source_create(ctx, ctx->dc_bios,
2159 CLOCK_SOURCE_COMBO_PHY_PLL2,
2160 &clk_src_regs[2], false);
2161 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
2162 dcn32_clock_source_create(ctx, ctx->dc_bios,
2163 CLOCK_SOURCE_COMBO_PHY_PLL3,
2164 &clk_src_regs[3], false);
2165 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
2166 dcn32_clock_source_create(ctx, ctx->dc_bios,
2167 CLOCK_SOURCE_COMBO_PHY_PLL4,
2168 &clk_src_regs[4], false);
2169
2170 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
2171
2172 /* todo: not reuse phy_pll registers */
2173 pool->base.dp_clock_source =
2174 dcn32_clock_source_create(ctx, ctx->dc_bios,
2175 CLOCK_SOURCE_ID_DP_DTO,
2176 &clk_src_regs[0], true);
2177
2178 for (i = 0; i < pool->base.clk_src_count; i++) {
2179 if (pool->base.clock_sources[i] == NULL) {
2180 dm_error("DC: failed to create clock sources!\n");
2181 BREAK_TO_DEBUGGER();
2182 goto create_fail;
2183 }
2184 }
2185
2186 /* DCCG */
2187 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2188 if (pool->base.dccg == NULL) {
2189 dm_error("DC: failed to create dccg!\n");
2190 BREAK_TO_DEBUGGER();
2191 goto create_fail;
2192 }
2193
2194 /* DML */
2195 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2196
2197 /* IRQ Service */
2198 init_data.ctx = dc->ctx;
2199 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2200 if (!pool->base.irqs)
2201 goto create_fail;
2202
2203 /* HUBBUB */
2204 pool->base.hubbub = dcn32_hubbub_create(ctx);
2205 if (pool->base.hubbub == NULL) {
2206 BREAK_TO_DEBUGGER();
2207 dm_error("DC: failed to create hubbub!\n");
2208 goto create_fail;
2209 }
2210
2211 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2212 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2213
2214 /* if pipe is disabled, skip instance of HW pipe,
2215 * i.e, skip ASIC register instance
2216 */
2217 if (pipe_fuses & 1 << i)
2218 continue;
2219
2220 /* HUBPs */
2221 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
2222 if (pool->base.hubps[j] == NULL) {
2223 BREAK_TO_DEBUGGER();
2224 dm_error(
2225 "DC: failed to create hubps!\n");
2226 goto create_fail;
2227 }
2228
2229 /* DPPs */
2230 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
2231 if (pool->base.dpps[j] == NULL) {
2232 BREAK_TO_DEBUGGER();
2233 dm_error(
2234 "DC: failed to create dpps!\n");
2235 goto create_fail;
2236 }
2237
2238 /* OPPs */
2239 pool->base.opps[j] = dcn32_opp_create(ctx, i);
2240 if (pool->base.opps[j] == NULL) {
2241 BREAK_TO_DEBUGGER();
2242 dm_error(
2243 "DC: failed to create output pixel processor!\n");
2244 goto create_fail;
2245 }
2246
2247 /* TGs */
2248 pool->base.timing_generators[j] = dcn32_timing_generator_create(
2249 ctx, i);
2250 if (pool->base.timing_generators[j] == NULL) {
2251 BREAK_TO_DEBUGGER();
2252 dm_error("DC: failed to create tg!\n");
2253 goto create_fail;
2254 }
2255
2256 /* ABMs */
2257 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2258 &abm_regs[i],
2259 &abm_shift,
2260 &abm_mask);
2261 if (pool->base.multiple_abms[j] == NULL) {
2262 dm_error("DC: failed to create abm for pipe %d!\n", i);
2263 BREAK_TO_DEBUGGER();
2264 goto create_fail;
2265 }
2266
2267 /* index for resource pool arrays for next valid pipe */
2268 j++;
2269 }
2270
2271 /* PSR */
2272 pool->base.psr = dmub_psr_create(ctx);
2273 if (pool->base.psr == NULL) {
2274 dm_error("DC: failed to create psr obj!\n");
2275 BREAK_TO_DEBUGGER();
2276 goto create_fail;
2277 }
2278
2279 /* MPCCs */
2280 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2281 if (pool->base.mpc == NULL) {
2282 BREAK_TO_DEBUGGER();
2283 dm_error("DC: failed to create mpc!\n");
2284 goto create_fail;
2285 }
2286
2287 /* DSCs */
2288 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2289 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
2290 if (pool->base.dscs[i] == NULL) {
2291 BREAK_TO_DEBUGGER();
2292 dm_error("DC: failed to create display stream compressor %d!\n", i);
2293 goto create_fail;
2294 }
2295 }
2296
2297 /* DWB */
2298 if (!dcn32_dwbc_create(ctx, &pool->base)) {
2299 BREAK_TO_DEBUGGER();
2300 dm_error("DC: failed to create dwbc!\n");
2301 goto create_fail;
2302 }
2303
2304 /* MMHUBBUB */
2305 if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
2306 BREAK_TO_DEBUGGER();
2307 dm_error("DC: failed to create mcif_wb!\n");
2308 goto create_fail;
2309 }
2310
2311 /* AUX and I2C */
2312 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2313 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
2314 if (pool->base.engines[i] == NULL) {
2315 BREAK_TO_DEBUGGER();
2316 dm_error(
2317 "DC:failed to create aux engine!!\n");
2318 goto create_fail;
2319 }
2320 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
2321 if (pool->base.hw_i2cs[i] == NULL) {
2322 BREAK_TO_DEBUGGER();
2323 dm_error(
2324 "DC:failed to create hw i2c!!\n");
2325 goto create_fail;
2326 }
2327 pool->base.sw_i2cs[i] = NULL;
2328 }
2329
2330 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2331 if (!resource_construct(num_virtual_links, dc, &pool->base,
2332 &res_create_funcs))
2333 goto create_fail;
2334
2335 /* HW Sequencer init functions and Plane caps */
2336 dcn32_hw_sequencer_init_functions(dc);
2337
2338 dc->caps.max_planes = pool->base.pipe_count;
2339
2340 for (i = 0; i < dc->caps.max_planes; ++i)
2341 dc->caps.planes[i] = plane_cap;
2342
2343 dc->cap_funcs = cap_funcs;
2344
2345 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2346 ddc_init_data.ctx = dc->ctx;
2347 ddc_init_data.link = NULL;
2348 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2349 ddc_init_data.id.enum_id = 0;
2350 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2351 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2352 } else {
2353 pool->base.oem_device = NULL;
2354 }
2355
2356 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2357 dc->dml2_options.use_native_pstate_optimization = false;
2358 dc->dml2_options.use_native_soc_bb_construction = true;
2359 dc->dml2_options.minimize_dispclk_using_odm = true;
2360
2361 dc->dml2_options.callbacks.dc = dc;
2362 dc->dml2_options.callbacks.build_scaling_params = &resource_build_scaling_params;
2363 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2364 dc->dml2_options.callbacks.acquire_secondary_pipe_for_mpc_odm = &dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy;
2365 dc->dml2_options.callbacks.update_pipes_for_stream_with_slice_count = &resource_update_pipes_for_stream_with_slice_count;
2366 dc->dml2_options.callbacks.update_pipes_for_plane_with_slice_count = &resource_update_pipes_for_plane_with_slice_count;
2367 dc->dml2_options.callbacks.get_mpc_slice_index = &resource_get_mpc_slice_index;
2368 dc->dml2_options.callbacks.get_odm_slice_index = &resource_get_odm_slice_index;
2369 dc->dml2_options.callbacks.get_opp_head = &resource_get_opp_head;
2370
2371 dc->dml2_options.svp_pstate.callbacks.dc = dc;
2372 dc->dml2_options.svp_pstate.callbacks.add_phantom_plane = &dc_state_add_phantom_plane;
2373 dc->dml2_options.svp_pstate.callbacks.add_phantom_stream = &dc_state_add_phantom_stream;
2374 dc->dml2_options.svp_pstate.callbacks.build_scaling_params = &resource_build_scaling_params;
2375 dc->dml2_options.svp_pstate.callbacks.create_phantom_plane = &dc_state_create_phantom_plane;
2376 dc->dml2_options.svp_pstate.callbacks.remove_phantom_plane = &dc_state_remove_phantom_plane;
2377 dc->dml2_options.svp_pstate.callbacks.remove_phantom_stream = &dc_state_remove_phantom_stream;
2378 dc->dml2_options.svp_pstate.callbacks.create_phantom_stream = &dc_state_create_phantom_stream;
2379 dc->dml2_options.svp_pstate.callbacks.release_phantom_plane = &dc_state_release_phantom_plane;
2380 dc->dml2_options.svp_pstate.callbacks.release_phantom_stream = &dc_state_release_phantom_stream;
2381 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2382 dc->dml2_options.svp_pstate.callbacks.get_pipe_subvp_type = &dc_state_get_pipe_subvp_type;
2383 dc->dml2_options.svp_pstate.callbacks.get_stream_subvp_type = &dc_state_get_stream_subvp_type;
2384 dc->dml2_options.svp_pstate.callbacks.get_paired_subvp_stream = &dc_state_get_paired_subvp_stream;
2385
2386 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2387 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2388 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2389 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2390
2391 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2392 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2393
2394 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2395 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2396 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2397 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2398 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2399 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2400 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2401
2402 dc->dml2_options.max_segments_per_hubp = 18;
2403 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2404 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2405
2406 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))
2407 dc->config.sdpif_request_limit_words_per_umc = 16;
2408
2409 DC_FP_END();
2410
2411 return true;
2412
2413 create_fail:
2414
2415 DC_FP_END();
2416
2417 dcn32_resource_destruct(pool);
2418
2419 return false;
2420 }
2421
dcn32_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2422 struct resource_pool *dcn32_create_resource_pool(
2423 const struct dc_init_data *init_data,
2424 struct dc *dc)
2425 {
2426 struct dcn32_resource_pool *pool =
2427 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
2428
2429 if (!pool)
2430 return NULL;
2431
2432 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
2433 return &pool->base;
2434
2435 BREAK_TO_DEBUGGER();
2436 kfree(pool);
2437 return NULL;
2438 }
2439
2440 /*
2441 * Find the most optimal free pipe from res_ctx, which could be used as a
2442 * secondary dpp pipe for input opp head pipe.
2443 *
2444 * a free pipe - a pipe in input res_ctx not yet used for any streams or
2445 * planes.
2446 * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending
2447 * tree. This is typical used for rendering MPO planes or additional offset
2448 * areas in MPCC combine.
2449 *
2450 * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe
2451 * -------------------------------------------------------------------------
2452 *
2453 * PROBLEM:
2454 *
2455 * 1. There is a hardware limitation that a secondary DPP pipe cannot be
2456 * transferred from one MPC blending tree to the other in a single frame.
2457 * Otherwise it could cause glitches on the screen.
2458 *
2459 * For instance, we cannot transition from state 1 to state 2 in one frame. This
2460 * is because PIPE1 is transferred from PIPE0's MPC blending tree over to
2461 * PIPE2's MPC blending tree, which is not supported by hardware.
2462 * To support this transition we need to first remove PIPE1 from PIPE0's MPC
2463 * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree
2464 * in the next frame. This is not optimal as it will delay the flip for two
2465 * frames.
2466 *
2467 * State 1:
2468 * PIPE0 -- secondary DPP pipe --> (PIPE1)
2469 * PIPE2 -- secondary DPP pipe --> NONE
2470 *
2471 * State 2:
2472 * PIPE0 -- secondary DPP pipe --> NONE
2473 * PIPE2 -- secondary DPP pipe --> (PIPE1)
2474 *
2475 * 2. We want to in general minimize the unnecessary changes in pipe topology.
2476 * If a pipe is already added in current blending tree and there are no changes
2477 * to plane topology, we don't want to swap it with another free pipe
2478 * unnecessarily in every update. Powering up and down a pipe would require a
2479 * full update which delays the flip for 1 frame. If we use the original pipe
2480 * we don't have to toggle its power. So we can flip faster.
2481 */
find_optimal_free_pipe_as_secondary_dpp_pipe(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_opp_head)2482 static int find_optimal_free_pipe_as_secondary_dpp_pipe(
2483 const struct resource_context *cur_res_ctx,
2484 struct resource_context *new_res_ctx,
2485 const struct resource_pool *pool,
2486 const struct pipe_ctx *new_opp_head)
2487 {
2488 const struct pipe_ctx *cur_opp_head;
2489 int free_pipe_idx;
2490
2491 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];
2492 free_pipe_idx = resource_find_free_pipe_used_in_cur_mpc_blending_tree(
2493 cur_res_ctx, new_res_ctx, cur_opp_head);
2494
2495 /* Up until here if we have not found a free secondary pipe, we will
2496 * need to wait for at least one frame to complete the transition
2497 * sequence.
2498 */
2499 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2500 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2501 cur_res_ctx, new_res_ctx, pool);
2502
2503 /* Up until here if we have not found a free secondary pipe, we will
2504 * need to wait for at least two frames to complete the transition
2505 * sequence. It really doesn't matter which pipe we decide take from
2506 * current enabled pipes. It won't save our frame time when we swap only
2507 * one pipe or more pipes.
2508 */
2509 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2510 free_pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
2511 cur_res_ctx, new_res_ctx, pool);
2512
2513 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2514 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2515
2516 return free_pipe_idx;
2517 }
2518
find_idle_secondary_pipe_check_mpo(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)2519 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
2520 struct resource_context *res_ctx,
2521 const struct resource_pool *pool,
2522 const struct pipe_ctx *primary_pipe)
2523 {
2524 int i;
2525 struct pipe_ctx *secondary_pipe = NULL;
2526 struct pipe_ctx *next_odm_mpo_pipe = NULL;
2527 int primary_index, preferred_pipe_idx;
2528 struct pipe_ctx *old_primary_pipe = NULL;
2529
2530 /*
2531 * Modified from find_idle_secondary_pipe
2532 * With windowed MPO and ODM, we want to avoid the case where we want a
2533 * free pipe for the left side but the free pipe is being used on the
2534 * right side.
2535 * Add check on current_state if the primary_pipe is the left side,
2536 * to check the right side ( primary_pipe->next_odm_pipe ) to see if
2537 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
2538 * - If so, then don't use this pipe
2539 * EXCEPTION - 3 plane ( 2 MPO plane ) case
2540 * - in this case, the primary pipe has already gotten a free pipe for the
2541 * MPO window in the left
2542 * - when it tries to get a free pipe for the MPO window on the right,
2543 * it will see that it is already assigned to the right side
2544 * ( primary_pipe->next_odm_pipe ). But in this case, we want this
2545 * free pipe, since it will be for the right side. So add an
2546 * additional condition, that skipping the free pipe on the right only
2547 * applies if the primary pipe has no bottom pipe currently assigned
2548 */
2549 if (primary_pipe) {
2550 primary_index = primary_pipe->pipe_idx;
2551 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
2552 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
2553 && (!primary_pipe->bottom_pipe))
2554 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
2555
2556 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
2557 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
2558 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
2559 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2560 secondary_pipe->pipe_idx = preferred_pipe_idx;
2561 }
2562 }
2563
2564 /*
2565 * search backwards for the second pipe to keep pipe
2566 * assignment more consistent
2567 */
2568 if (!secondary_pipe)
2569 for (i = pool->pipe_count - 1; i >= 0; i--) {
2570 if ((res_ctx->pipe_ctx[i].stream == NULL) &&
2571 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
2572 secondary_pipe = &res_ctx->pipe_ctx[i];
2573 secondary_pipe->pipe_idx = i;
2574 break;
2575 }
2576 }
2577
2578 return secondary_pipe;
2579 }
2580
dcn32_acquire_idle_pipe_for_head_pipe_in_layer(struct dc_state * state,const struct resource_pool * pool,struct dc_stream_state * stream,const struct pipe_ctx * head_pipe)2581 static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2582 struct dc_state *state,
2583 const struct resource_pool *pool,
2584 struct dc_stream_state *stream,
2585 const struct pipe_ctx *head_pipe)
2586 {
2587 struct resource_context *res_ctx = &state->res_ctx;
2588 struct pipe_ctx *idle_pipe, *pipe;
2589 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
2590 int head_index;
2591
2592 if (!head_pipe)
2593 ASSERT(0);
2594
2595 /*
2596 * Modified from dcn20_acquire_idle_pipe_for_layer
2597 * Check if head_pipe in old_context already has bottom_pipe allocated.
2598 * - If so, check if that pipe is available in the current context.
2599 * -- If so, reuse pipe from old_context
2600 */
2601 head_index = head_pipe->pipe_idx;
2602 pipe = &old_ctx->pipe_ctx[head_index];
2603 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
2604 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
2605 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
2606 } else {
2607 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
2608 if (!idle_pipe)
2609 return NULL;
2610 }
2611
2612 idle_pipe->stream = head_pipe->stream;
2613 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2614 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2615
2616 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2617 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2618 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2619 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2620
2621 return idle_pipe;
2622 }
2623
find_optimal_free_pipe_as_secondary_opp_head(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_otg_master)2624 static int find_optimal_free_pipe_as_secondary_opp_head(
2625 const struct resource_context *cur_res_ctx,
2626 struct resource_context *new_res_ctx,
2627 const struct resource_pool *pool,
2628 const struct pipe_ctx *new_otg_master)
2629 {
2630 const struct pipe_ctx *cur_otg_master;
2631 int free_pipe_idx;
2632
2633 cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];
2634 free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
2635 cur_res_ctx, new_res_ctx, cur_otg_master);
2636
2637 /* Up until here if we have not found a free secondary pipe, we will
2638 * need to wait for at least one frame to complete the transition
2639 * sequence.
2640 */
2641 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2642 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2643 cur_res_ctx, new_res_ctx, pool);
2644
2645 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2646 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2647
2648 return free_pipe_idx;
2649 }
2650
dcn32_acquire_free_pipe_as_secondary_dpp_pipe(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)2651 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
2652 const struct dc_state *cur_ctx,
2653 struct dc_state *new_ctx,
2654 const struct resource_pool *pool,
2655 const struct pipe_ctx *opp_head_pipe)
2656 {
2657
2658 int free_pipe_idx;
2659 struct pipe_ctx *free_pipe;
2660
2661 if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)
2662 return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2663 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
2664
2665 free_pipe_idx = find_optimal_free_pipe_as_secondary_dpp_pipe(
2666 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2667 pool, opp_head_pipe);
2668 if (free_pipe_idx >= 0) {
2669 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2670 free_pipe->pipe_idx = free_pipe_idx;
2671 free_pipe->stream = opp_head_pipe->stream;
2672 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
2673 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
2674
2675 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
2676 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
2677 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
2678 free_pipe->plane_res.mpcc_inst =
2679 pool->dpps[free_pipe->pipe_idx]->inst;
2680 } else {
2681 ASSERT(opp_head_pipe);
2682 free_pipe = NULL;
2683 }
2684
2685 return free_pipe;
2686 }
2687
dcn32_acquire_free_pipe_as_secondary_opp_head(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * otg_master)2688 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
2689 const struct dc_state *cur_ctx,
2690 struct dc_state *new_ctx,
2691 const struct resource_pool *pool,
2692 const struct pipe_ctx *otg_master)
2693 {
2694 int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head(
2695 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2696 pool, otg_master);
2697 struct pipe_ctx *free_pipe;
2698
2699 if (free_pipe_idx >= 0) {
2700 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2701 free_pipe->pipe_idx = free_pipe_idx;
2702 free_pipe->stream = otg_master->stream;
2703 free_pipe->stream_res.tg = otg_master->stream_res.tg;
2704 free_pipe->stream_res.dsc = NULL;
2705 free_pipe->stream_res.opp = pool->opps[free_pipe_idx];
2706 free_pipe->plane_res.mi = pool->mis[free_pipe_idx];
2707 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];
2708 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
2709 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
2710 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
2711 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
2712 if (free_pipe->stream->timing.flags.DSC == 1) {
2713 dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
2714 &new_ctx->res_ctx,
2715 &free_pipe->stream_res.dsc,
2716 free_pipe_idx);
2717 ASSERT(free_pipe->stream_res.dsc);
2718 if (free_pipe->stream_res.dsc == NULL) {
2719 memset(free_pipe, 0, sizeof(*free_pipe));
2720 free_pipe = NULL;
2721 }
2722 }
2723 } else {
2724 ASSERT(otg_master);
2725 free_pipe = NULL;
2726 }
2727
2728 return free_pipe;
2729 }
2730
dcn32_calc_num_avail_chans_for_mall(struct dc * dc,int num_chans)2731 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
2732 {
2733 /*
2734 * DCN32 and DCN321 SKUs may have different sizes for MALL
2735 * but we may not be able to access all the MALL space.
2736 * If the num_chans is power of 2, then we can access all
2737 * of the available MALL space. Otherwise, we can only
2738 * access:
2739 *
2740 * max_cab_size_in_bytes = total_cache_size_in_bytes *
2741 * ((2^floor(log2(num_chans)))/num_chans)
2742 *
2743 * Calculating the MALL sizes for all available SKUs, we
2744 * have come up with the follow simplified check.
2745 * - we have max_chans which provides the max MALL size.
2746 * Each chans supports 4MB of MALL so:
2747 *
2748 * total_cache_size_in_bytes = max_chans * 4 MB
2749 *
2750 * - we have avail_chans which shows the number of channels
2751 * we can use if we can't access the entire MALL space.
2752 * It is generally half of max_chans
2753 * - so we use the following checks:
2754 *
2755 * if (num_chans == max_chans), return max_chans
2756 * if (num_chans < max_chans), return avail_chans
2757 *
2758 * - exception is GC_11_0_0 where we can't access max_chans,
2759 * so we define max_avail_chans as the maximum available
2760 * MALL space
2761 *
2762 */
2763 int gc_11_0_0_max_chans = 48;
2764 int gc_11_0_0_max_avail_chans = 32;
2765 int gc_11_0_0_avail_chans = 16;
2766 int gc_11_0_3_max_chans = 16;
2767 int gc_11_0_3_avail_chans = 8;
2768 int gc_11_0_2_max_chans = 8;
2769 int gc_11_0_2_avail_chans = 4;
2770
2771 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {
2772 return (num_chans == gc_11_0_0_max_chans) ?
2773 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans;
2774 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {
2775 return (num_chans == gc_11_0_2_max_chans) ?
2776 gc_11_0_2_max_chans : gc_11_0_2_avail_chans;
2777 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) {
2778 return (num_chans == gc_11_0_3_max_chans) ?
2779 gc_11_0_3_max_chans : gc_11_0_3_avail_chans;
2780 }
2781 }
2782