1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn31_resource.h"
35
36 #include "dcn20/dcn20_resource.h"
37 #include "dcn30/dcn30_resource.h"
38
39 #include "dml/dcn30/dcn30_fpu.h"
40
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn30/dcn30_hubbub.h"
43 #include "dcn31/dcn31_hubbub.h"
44 #include "dcn30/dcn30_mpc.h"
45 #include "dcn31/dcn31_hubp.h"
46 #include "irq/dcn31/irq_service_dcn31.h"
47 #include "dcn30/dcn30_dpp.h"
48 #include "dcn31/dcn31_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hwseq.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
59 #include "dcn31/dcn31_apg.h"
60 #include "dcn31/dcn31_dio_link_encoder.h"
61 #include "dcn31/dcn31_vpg.h"
62 #include "dcn31/dcn31_afmt.h"
63 #include "dce/dce_clock_source.h"
64 #include "dce/dce_audio.h"
65 #include "dce/dce_hwseq.h"
66 #include "clk_mgr.h"
67 #include "virtual/virtual_stream_encoder.h"
68 #include "dce110/dce110_resource.h"
69 #include "dml/display_mode_vba.h"
70 #include "dml/dcn31/dcn31_fpu.h"
71 #include "dcn31/dcn31_dccg.h"
72 #include "dcn10/dcn10_resource.h"
73 #include "dcn31/dcn31_panel_cntl.h"
74
75 #include "dcn30/dcn30_dwb.h"
76 #include "dcn30/dcn30_mmhubbub.h"
77
78 // TODO: change include headers /amd/include/asic_reg after upstream
79 #include "yellow_carp_offset.h"
80 #include "dcn/dcn_3_1_2_offset.h"
81 #include "dcn/dcn_3_1_2_sh_mask.h"
82 #include "nbio/nbio_7_2_0_offset.h"
83 #include "dpcs/dpcs_4_2_0_offset.h"
84 #include "dpcs/dpcs_4_2_0_sh_mask.h"
85 #include "mmhub/mmhub_2_3_0_offset.h"
86 #include "mmhub/mmhub_2_3_0_sh_mask.h"
87
88
89 #define regDCHUBBUB_DEBUG_CTRL_0 0x04d6
90 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2
91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
92 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
93
94 #include "reg_helper.h"
95 #include "dce/dmub_abm.h"
96 #include "dce/dmub_psr.h"
97 #include "dce/dce_aux.h"
98 #include "dce/dce_i2c.h"
99 #include "dce/dmub_replay.h"
100
101 #include "dml/dcn30/display_mode_vba_30.h"
102 #include "vm_helper.h"
103 #include "dcn20/dcn20_vmid.h"
104
105 #include "link_enc_cfg.h"
106
107 #define DC_LOGGER \
108 dc->ctx->logger
109 #define DC_LOGGER_INIT(logger)
110
111 enum dcn31_clk_src_array_id {
112 DCN31_CLK_SRC_PLL0,
113 DCN31_CLK_SRC_PLL1,
114 DCN31_CLK_SRC_PLL2,
115 DCN31_CLK_SRC_PLL3,
116 DCN31_CLK_SRC_PLL4,
117 DCN30_CLK_SRC_TOTAL
118 };
119
120 /* begin *********************
121 * macros to expend register list macro defined in HW object header file
122 */
123
124 /* DCN */
125 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
126
127 #define BASE(seg) BASE_INNER(seg)
128
129 #define SR(reg_name)\
130 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
131 reg ## reg_name
132
133 #define SRI(reg_name, block, id)\
134 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 reg ## block ## id ## _ ## reg_name
136
137 #define SRI2(reg_name, block, id)\
138 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
139 reg ## reg_name
140
141 #define SRIR(var_name, reg_name, block, id)\
142 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
144
145 #define SRII(reg_name, block, id)\
146 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
148
149 #define SRII_MPC_RMU(reg_name, block, id)\
150 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
152
153 #define SRII_DWB(reg_name, temp_name, block, id)\
154 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
155 reg ## block ## id ## _ ## temp_name
156
157 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
158 .field_name = reg_name ## __ ## field_name ## post_fix
159
160 #define DCCG_SRII(reg_name, block, id)\
161 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define VUPDATE_SRII(reg_name, block, id)\
165 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
166 reg ## reg_name ## _ ## block ## id
167
168 /* NBIO */
169 #define NBIO_BASE_INNER(seg) \
170 NBIO_BASE__INST0_SEG ## seg
171
172 #define NBIO_BASE(seg) \
173 NBIO_BASE_INNER(seg)
174
175 #define NBIO_SR(reg_name)\
176 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
177 regBIF_BX1_ ## reg_name
178
179 /* MMHUB */
180 #define MMHUB_BASE_INNER(seg) \
181 MMHUB_BASE__INST0_SEG ## seg
182
183 #define MMHUB_BASE(seg) \
184 MMHUB_BASE_INNER(seg)
185
186 #define MMHUB_SR(reg_name)\
187 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
188 mm ## reg_name
189
190 /* CLOCK */
191 #define CLK_BASE_INNER(seg) \
192 CLK_BASE__INST0_SEG ## seg
193
194 #define CLK_BASE(seg) \
195 CLK_BASE_INNER(seg)
196
197 #define CLK_SRI(reg_name, block, inst)\
198 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
199 reg ## block ## _ ## inst ## _ ## reg_name
200
201
202 static const struct bios_registers bios_regs = {
203 NBIO_SR(BIOS_SCRATCH_3),
204 NBIO_SR(BIOS_SCRATCH_6)
205 };
206
207 #define clk_src_regs(index, pllid)\
208 [index] = {\
209 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
210 }
211
212 static const struct dce110_clk_src_regs clk_src_regs[] = {
213 clk_src_regs(0, A),
214 clk_src_regs(1, B),
215 clk_src_regs(2, C),
216 clk_src_regs(3, D),
217 clk_src_regs(4, E)
218 };
219 /*pll_id being rempped in dmub, in driver it is logical instance*/
220 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
221 clk_src_regs(0, A),
222 clk_src_regs(1, B),
223 clk_src_regs(2, F),
224 clk_src_regs(3, G),
225 clk_src_regs(4, E)
226 };
227
228 static const struct dce110_clk_src_shift cs_shift = {
229 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
230 };
231
232 static const struct dce110_clk_src_mask cs_mask = {
233 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
234 };
235
236 #define abm_regs(id)\
237 [id] = {\
238 ABM_DCN302_REG_LIST(id)\
239 }
240
241 static const struct dce_abm_registers abm_regs[] = {
242 abm_regs(0),
243 abm_regs(1),
244 abm_regs(2),
245 abm_regs(3),
246 };
247
248 static const struct dce_abm_shift abm_shift = {
249 ABM_MASK_SH_LIST_DCN30(__SHIFT)
250 };
251
252 static const struct dce_abm_mask abm_mask = {
253 ABM_MASK_SH_LIST_DCN30(_MASK)
254 };
255
256 #define audio_regs(id)\
257 [id] = {\
258 AUD_COMMON_REG_LIST(id)\
259 }
260
261 static const struct dce_audio_registers audio_regs[] = {
262 audio_regs(0),
263 audio_regs(1),
264 audio_regs(2),
265 audio_regs(3),
266 audio_regs(4),
267 audio_regs(5),
268 audio_regs(6)
269 };
270
271 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
272 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
273 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
274 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
275
276 static const struct dce_audio_shift audio_shift = {
277 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
278 };
279
280 static const struct dce_audio_mask audio_mask = {
281 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
282 };
283
284 #define vpg_regs(id)\
285 [id] = {\
286 VPG_DCN31_REG_LIST(id)\
287 }
288
289 static const struct dcn31_vpg_registers vpg_regs[] = {
290 vpg_regs(0),
291 vpg_regs(1),
292 vpg_regs(2),
293 vpg_regs(3),
294 vpg_regs(4),
295 vpg_regs(5),
296 vpg_regs(6),
297 vpg_regs(7),
298 vpg_regs(8),
299 vpg_regs(9),
300 };
301
302 static const struct dcn31_vpg_shift vpg_shift = {
303 DCN31_VPG_MASK_SH_LIST(__SHIFT)
304 };
305
306 static const struct dcn31_vpg_mask vpg_mask = {
307 DCN31_VPG_MASK_SH_LIST(_MASK)
308 };
309
310 #define afmt_regs(id)\
311 [id] = {\
312 AFMT_DCN31_REG_LIST(id)\
313 }
314
315 static const struct dcn31_afmt_registers afmt_regs[] = {
316 afmt_regs(0),
317 afmt_regs(1),
318 afmt_regs(2),
319 afmt_regs(3),
320 afmt_regs(4),
321 afmt_regs(5)
322 };
323
324 static const struct dcn31_afmt_shift afmt_shift = {
325 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
326 };
327
328 static const struct dcn31_afmt_mask afmt_mask = {
329 DCN31_AFMT_MASK_SH_LIST(_MASK)
330 };
331
332 #define apg_regs(id)\
333 [id] = {\
334 APG_DCN31_REG_LIST(id)\
335 }
336
337 static const struct dcn31_apg_registers apg_regs[] = {
338 apg_regs(0),
339 apg_regs(1),
340 apg_regs(2),
341 apg_regs(3)
342 };
343
344 static const struct dcn31_apg_shift apg_shift = {
345 DCN31_APG_MASK_SH_LIST(__SHIFT)
346 };
347
348 static const struct dcn31_apg_mask apg_mask = {
349 DCN31_APG_MASK_SH_LIST(_MASK)
350 };
351
352 #define stream_enc_regs(id)\
353 [id] = {\
354 SE_DCN3_REG_LIST(id)\
355 }
356
357 /* Some encoders won't be initialized here - but they're logical, not physical. */
358 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
359 stream_enc_regs(0),
360 stream_enc_regs(1),
361 stream_enc_regs(2),
362 stream_enc_regs(3),
363 stream_enc_regs(4)
364 };
365
366 static const struct dcn10_stream_encoder_shift se_shift = {
367 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
368 };
369
370 static const struct dcn10_stream_encoder_mask se_mask = {
371 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
372 };
373
374
375 #define aux_regs(id)\
376 [id] = {\
377 DCN2_AUX_REG_LIST(id)\
378 }
379
380 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
381 aux_regs(0),
382 aux_regs(1),
383 aux_regs(2),
384 aux_regs(3),
385 aux_regs(4)
386 };
387
388 #define hpd_regs(id)\
389 [id] = {\
390 HPD_REG_LIST(id)\
391 }
392
393 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
394 hpd_regs(0),
395 hpd_regs(1),
396 hpd_regs(2),
397 hpd_regs(3),
398 hpd_regs(4)
399 };
400
401 #define link_regs(id, phyid)\
402 [id] = {\
403 LE_DCN31_REG_LIST(id), \
404 UNIPHY_DCN2_REG_LIST(phyid), \
405 DPCS_DCN31_REG_LIST(id), \
406 }
407
408 static const struct dce110_aux_registers_shift aux_shift = {
409 DCN_AUX_MASK_SH_LIST(__SHIFT)
410 };
411
412 static const struct dce110_aux_registers_mask aux_mask = {
413 DCN_AUX_MASK_SH_LIST(_MASK)
414 };
415
416 static const struct dcn10_link_enc_registers link_enc_regs[] = {
417 link_regs(0, A),
418 link_regs(1, B),
419 link_regs(2, C),
420 link_regs(3, D),
421 link_regs(4, E)
422 };
423
424 static const struct dcn10_link_enc_shift le_shift = {
425 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
426 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
427 };
428
429 static const struct dcn10_link_enc_mask le_mask = {
430 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
431 DPCS_DCN31_MASK_SH_LIST(_MASK)
432 };
433
434 #define hpo_dp_stream_encoder_reg_list(id)\
435 [id] = {\
436 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
437 }
438
439 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
440 hpo_dp_stream_encoder_reg_list(0),
441 hpo_dp_stream_encoder_reg_list(1),
442 hpo_dp_stream_encoder_reg_list(2),
443 hpo_dp_stream_encoder_reg_list(3),
444 };
445
446 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
447 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
448 };
449
450 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
451 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
452 };
453
454 #define hpo_dp_link_encoder_reg_list(id)\
455 [id] = {\
456 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
457 DCN3_1_RDPCSTX_REG_LIST(0),\
458 DCN3_1_RDPCSTX_REG_LIST(1),\
459 DCN3_1_RDPCSTX_REG_LIST(2),\
460 DCN3_1_RDPCSTX_REG_LIST(3),\
461 DCN3_1_RDPCSTX_REG_LIST(4)\
462 }
463
464 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
465 hpo_dp_link_encoder_reg_list(0),
466 hpo_dp_link_encoder_reg_list(1),
467 };
468
469 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
470 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
471 };
472
473 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
474 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
475 };
476
477 #define dpp_regs(id)\
478 [id] = {\
479 DPP_REG_LIST_DCN30(id),\
480 }
481
482 static const struct dcn3_dpp_registers dpp_regs[] = {
483 dpp_regs(0),
484 dpp_regs(1),
485 dpp_regs(2),
486 dpp_regs(3)
487 };
488
489 static const struct dcn3_dpp_shift tf_shift = {
490 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
491 };
492
493 static const struct dcn3_dpp_mask tf_mask = {
494 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
495 };
496
497 #define opp_regs(id)\
498 [id] = {\
499 OPP_REG_LIST_DCN30(id),\
500 }
501
502 static const struct dcn20_opp_registers opp_regs[] = {
503 opp_regs(0),
504 opp_regs(1),
505 opp_regs(2),
506 opp_regs(3)
507 };
508
509 static const struct dcn20_opp_shift opp_shift = {
510 OPP_MASK_SH_LIST_DCN20(__SHIFT)
511 };
512
513 static const struct dcn20_opp_mask opp_mask = {
514 OPP_MASK_SH_LIST_DCN20(_MASK)
515 };
516
517 #define aux_engine_regs(id)\
518 [id] = {\
519 AUX_COMMON_REG_LIST0(id), \
520 .AUXN_IMPCAL = 0, \
521 .AUXP_IMPCAL = 0, \
522 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
523 }
524
525 static const struct dce110_aux_registers aux_engine_regs[] = {
526 aux_engine_regs(0),
527 aux_engine_regs(1),
528 aux_engine_regs(2),
529 aux_engine_regs(3),
530 aux_engine_regs(4)
531 };
532
533 #define dwbc_regs_dcn3(id)\
534 [id] = {\
535 DWBC_COMMON_REG_LIST_DCN30(id),\
536 }
537
538 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
539 dwbc_regs_dcn3(0),
540 };
541
542 static const struct dcn30_dwbc_shift dwbc30_shift = {
543 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
544 };
545
546 static const struct dcn30_dwbc_mask dwbc30_mask = {
547 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
548 };
549
550 #define mcif_wb_regs_dcn3(id)\
551 [id] = {\
552 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
553 }
554
555 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
556 mcif_wb_regs_dcn3(0)
557 };
558
559 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
560 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
561 };
562
563 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
564 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
565 };
566
567 #define dsc_regsDCN20(id)\
568 [id] = {\
569 DSC_REG_LIST_DCN20(id)\
570 }
571
572 static const struct dcn20_dsc_registers dsc_regs[] = {
573 dsc_regsDCN20(0),
574 dsc_regsDCN20(1),
575 dsc_regsDCN20(2)
576 };
577
578 static const struct dcn20_dsc_shift dsc_shift = {
579 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
580 };
581
582 static const struct dcn20_dsc_mask dsc_mask = {
583 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
584 };
585
586 static const struct dcn30_mpc_registers mpc_regs = {
587 MPC_REG_LIST_DCN3_0(0),
588 MPC_REG_LIST_DCN3_0(1),
589 MPC_REG_LIST_DCN3_0(2),
590 MPC_REG_LIST_DCN3_0(3),
591 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
592 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
593 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
594 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
595 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
596 MPC_RMU_REG_LIST_DCN3AG(0),
597 MPC_RMU_REG_LIST_DCN3AG(1),
598 //MPC_RMU_REG_LIST_DCN3AG(2),
599 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
600 };
601
602 static const struct dcn30_mpc_shift mpc_shift = {
603 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
604 };
605
606 static const struct dcn30_mpc_mask mpc_mask = {
607 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
608 };
609
610 #define optc_regs(id)\
611 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
612
613 static const struct dcn_optc_registers optc_regs[] = {
614 optc_regs(0),
615 optc_regs(1),
616 optc_regs(2),
617 optc_regs(3)
618 };
619
620 static const struct dcn_optc_shift optc_shift = {
621 OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
622 };
623
624 static const struct dcn_optc_mask optc_mask = {
625 OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
626 };
627
628 #define hubp_regs(id)\
629 [id] = {\
630 HUBP_REG_LIST_DCN30(id)\
631 }
632
633 static const struct dcn_hubp2_registers hubp_regs[] = {
634 hubp_regs(0),
635 hubp_regs(1),
636 hubp_regs(2),
637 hubp_regs(3)
638 };
639
640
641 static const struct dcn_hubp2_shift hubp_shift = {
642 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
643 };
644
645 static const struct dcn_hubp2_mask hubp_mask = {
646 HUBP_MASK_SH_LIST_DCN31(_MASK)
647 };
648 static const struct dcn_hubbub_registers hubbub_reg = {
649 HUBBUB_REG_LIST_DCN31(0)
650 };
651
652 static const struct dcn_hubbub_shift hubbub_shift = {
653 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
654 };
655
656 static const struct dcn_hubbub_mask hubbub_mask = {
657 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
658 };
659
660 static const struct dccg_registers dccg_regs = {
661 DCCG_REG_LIST_DCN31()
662 };
663
664 static const struct dccg_shift dccg_shift = {
665 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
666 };
667
668 static const struct dccg_mask dccg_mask = {
669 DCCG_MASK_SH_LIST_DCN31(_MASK)
670 };
671
672
673 #define SRII2(reg_name_pre, reg_name_post, id)\
674 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
675 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
676 reg ## reg_name_pre ## id ## _ ## reg_name_post
677
678
679 #define HWSEQ_DCN31_REG_LIST()\
680 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
681 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
682 SR(DIO_MEM_PWR_CTRL), \
683 SR(ODM_MEM_PWR_CTRL3), \
684 SR(DMU_MEM_PWR_CNTL), \
685 SR(MMHUBBUB_MEM_PWR_CNTL), \
686 SR(DCCG_GATE_DISABLE_CNTL), \
687 SR(DCCG_GATE_DISABLE_CNTL2), \
688 SR(DCFCLK_CNTL),\
689 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
690 SRII(PIXEL_RATE_CNTL, OTG, 0), \
691 SRII(PIXEL_RATE_CNTL, OTG, 1),\
692 SRII(PIXEL_RATE_CNTL, OTG, 2),\
693 SRII(PIXEL_RATE_CNTL, OTG, 3),\
694 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
695 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
696 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
697 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
698 SR(MICROSECOND_TIME_BASE_DIV), \
699 SR(MILLISECOND_TIME_BASE_DIV), \
700 SR(DISPCLK_FREQ_CHANGE_CNTL), \
701 SR(RBBMIF_TIMEOUT_DIS), \
702 SR(RBBMIF_TIMEOUT_DIS_2), \
703 SR(DCHUBBUB_CRC_CTRL), \
704 SR(DPP_TOP0_DPP_CRC_CTRL), \
705 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
706 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
707 SR(MPC_CRC_CTRL), \
708 SR(MPC_CRC_RESULT_GB), \
709 SR(MPC_CRC_RESULT_C), \
710 SR(MPC_CRC_RESULT_AR), \
711 SR(DOMAIN0_PG_CONFIG), \
712 SR(DOMAIN1_PG_CONFIG), \
713 SR(DOMAIN2_PG_CONFIG), \
714 SR(DOMAIN3_PG_CONFIG), \
715 SR(DOMAIN16_PG_CONFIG), \
716 SR(DOMAIN17_PG_CONFIG), \
717 SR(DOMAIN18_PG_CONFIG), \
718 SR(DOMAIN0_PG_STATUS), \
719 SR(DOMAIN1_PG_STATUS), \
720 SR(DOMAIN2_PG_STATUS), \
721 SR(DOMAIN3_PG_STATUS), \
722 SR(DOMAIN16_PG_STATUS), \
723 SR(DOMAIN17_PG_STATUS), \
724 SR(DOMAIN18_PG_STATUS), \
725 SR(D1VGA_CONTROL), \
726 SR(D2VGA_CONTROL), \
727 SR(D3VGA_CONTROL), \
728 SR(D4VGA_CONTROL), \
729 SR(D5VGA_CONTROL), \
730 SR(D6VGA_CONTROL), \
731 SR(DC_IP_REQUEST_CNTL), \
732 SR(AZALIA_AUDIO_DTO), \
733 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
734 SR(HPO_TOP_HW_CONTROL)
735
736 static const struct dce_hwseq_registers hwseq_reg = {
737 HWSEQ_DCN31_REG_LIST()
738 };
739
740 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
741 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
742 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
743 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
744 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
745 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
746 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
747 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
748 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
749 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
750 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
751 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
752 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
753 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
754 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
755 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
756 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
757 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
758 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
759 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
760 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
761 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
762 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
763 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
764 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
765 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
766 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
767 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
768 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
769 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
770 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
771 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
772 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
773 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
774
775 static const struct dce_hwseq_shift hwseq_shift = {
776 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
777 };
778
779 static const struct dce_hwseq_mask hwseq_mask = {
780 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
781 };
782 #define vmid_regs(id)\
783 [id] = {\
784 DCN20_VMID_REG_LIST(id)\
785 }
786
787 static const struct dcn_vmid_registers vmid_regs[] = {
788 vmid_regs(0),
789 vmid_regs(1),
790 vmid_regs(2),
791 vmid_regs(3),
792 vmid_regs(4),
793 vmid_regs(5),
794 vmid_regs(6),
795 vmid_regs(7),
796 vmid_regs(8),
797 vmid_regs(9),
798 vmid_regs(10),
799 vmid_regs(11),
800 vmid_regs(12),
801 vmid_regs(13),
802 vmid_regs(14),
803 vmid_regs(15)
804 };
805
806 static const struct dcn20_vmid_shift vmid_shifts = {
807 DCN20_VMID_MASK_SH_LIST(__SHIFT)
808 };
809
810 static const struct dcn20_vmid_mask vmid_masks = {
811 DCN20_VMID_MASK_SH_LIST(_MASK)
812 };
813
814 static const struct resource_caps res_cap_dcn31 = {
815 .num_timing_generator = 4,
816 .num_opp = 4,
817 .num_video_plane = 4,
818 .num_audio = 5,
819 .num_stream_encoder = 5,
820 .num_dig_link_enc = 5,
821 .num_hpo_dp_stream_encoder = 4,
822 .num_hpo_dp_link_encoder = 2,
823 .num_pll = 5,
824 .num_dwb = 1,
825 .num_ddc = 5,
826 .num_vmid = 16,
827 .num_mpc_3dlut = 2,
828 .num_dsc = 3,
829 };
830
831 static const struct dc_plane_cap plane_cap = {
832 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
833 .per_pixel_alpha = true,
834
835 .pixel_format_support = {
836 .argb8888 = true,
837 .nv12 = true,
838 .fp16 = true,
839 .p010 = true,
840 .ayuv = false,
841 },
842
843 .max_upscale_factor = {
844 .argb8888 = 16000,
845 .nv12 = 16000,
846 .fp16 = 16000
847 },
848
849 // 6:1 downscaling ratio: 1000/6 = 166.666
850 .max_downscale_factor = {
851 .argb8888 = 167,
852 .nv12 = 167,
853 .fp16 = 167
854 },
855 64,
856 64
857 };
858
859 static const struct dc_debug_options debug_defaults_drv = {
860 .disable_dmcu = true,
861 .force_abm_enable = false,
862 .timing_trace = false,
863 .clock_trace = true,
864 .disable_pplib_clock_request = false,
865 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
866 .force_single_disp_pipe_split = false,
867 .disable_dcc = DCC_ENABLE,
868 .vsr_support = true,
869 .performance_trace = false,
870 .max_downscale_src_width = 4096,/*upto true 4K*/
871 .disable_pplib_wm_range = false,
872 .scl_reset_length10 = true,
873 .sanity_checks = true,
874 .underflow_assert_delay_us = 0xFFFFFFFF,
875 .dwb_fi_phase = -1, // -1 = disable,
876 .dmub_command_table = true,
877 .pstate_enabled = true,
878 .use_max_lb = true,
879 .enable_mem_low_power = {
880 .bits = {
881 .vga = true,
882 .i2c = true,
883 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
884 .dscl = true,
885 .cm = true,
886 .mpc = true,
887 .optc = true,
888 .vpg = true,
889 .afmt = true,
890 }
891 },
892 .disable_z10 = true,
893 .enable_legacy_fast_update = true,
894 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
895 .dml_hostvm_override = DML_HOSTVM_OVERRIDE_FALSE,
896 .using_dml2 = false,
897 };
898
899 static const struct dc_panel_config panel_config_defaults = {
900 .psr = {
901 .disable_psr = false,
902 .disallow_psrsu = false,
903 .disallow_replay = false,
904 },
905 .ilr = {
906 .optimize_edp_link_rate = true,
907 },
908 };
909
dcn31_dpp_destroy(struct dpp ** dpp)910 static void dcn31_dpp_destroy(struct dpp **dpp)
911 {
912 kfree(TO_DCN20_DPP(*dpp));
913 *dpp = NULL;
914 }
915
dcn31_dpp_create(struct dc_context * ctx,uint32_t inst)916 static struct dpp *dcn31_dpp_create(
917 struct dc_context *ctx,
918 uint32_t inst)
919 {
920 struct dcn3_dpp *dpp =
921 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
922
923 if (!dpp)
924 return NULL;
925
926 if (dpp3_construct(dpp, ctx, inst,
927 &dpp_regs[inst], &tf_shift, &tf_mask))
928 return &dpp->base;
929
930 BREAK_TO_DEBUGGER();
931 kfree(dpp);
932 return NULL;
933 }
934
dcn31_opp_create(struct dc_context * ctx,uint32_t inst)935 static struct output_pixel_processor *dcn31_opp_create(
936 struct dc_context *ctx, uint32_t inst)
937 {
938 struct dcn20_opp *opp =
939 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
940
941 if (!opp) {
942 BREAK_TO_DEBUGGER();
943 return NULL;
944 }
945
946 dcn20_opp_construct(opp, ctx, inst,
947 &opp_regs[inst], &opp_shift, &opp_mask);
948 return &opp->base;
949 }
950
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)951 static struct dce_aux *dcn31_aux_engine_create(
952 struct dc_context *ctx,
953 uint32_t inst)
954 {
955 struct aux_engine_dce110 *aux_engine =
956 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
957
958 if (!aux_engine)
959 return NULL;
960
961 dce110_aux_engine_construct(aux_engine, ctx, inst,
962 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
963 &aux_engine_regs[inst],
964 &aux_mask,
965 &aux_shift,
966 ctx->dc->caps.extended_aux_timeout_support);
967
968 return &aux_engine->base;
969 }
970 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
971
972 static const struct dce_i2c_registers i2c_hw_regs[] = {
973 i2c_inst_regs(1),
974 i2c_inst_regs(2),
975 i2c_inst_regs(3),
976 i2c_inst_regs(4),
977 i2c_inst_regs(5),
978 };
979
980 static const struct dce_i2c_shift i2c_shifts = {
981 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
982 };
983
984 static const struct dce_i2c_mask i2c_masks = {
985 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
986 };
987
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)988 static struct dce_i2c_hw *dcn31_i2c_hw_create(
989 struct dc_context *ctx,
990 uint32_t inst)
991 {
992 struct dce_i2c_hw *dce_i2c_hw =
993 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
994
995 if (!dce_i2c_hw)
996 return NULL;
997
998 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
999 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1000
1001 return dce_i2c_hw;
1002 }
dcn31_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1003 static struct mpc *dcn31_mpc_create(
1004 struct dc_context *ctx,
1005 int num_mpcc,
1006 int num_rmu)
1007 {
1008 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1009 GFP_KERNEL);
1010
1011 if (!mpc30)
1012 return NULL;
1013
1014 dcn30_mpc_construct(mpc30, ctx,
1015 &mpc_regs,
1016 &mpc_shift,
1017 &mpc_mask,
1018 num_mpcc,
1019 num_rmu);
1020
1021 return &mpc30->base;
1022 }
1023
dcn31_hubbub_create(struct dc_context * ctx)1024 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1025 {
1026 int i;
1027
1028 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1029 GFP_KERNEL);
1030
1031 if (!hubbub3)
1032 return NULL;
1033
1034 hubbub31_construct(hubbub3, ctx,
1035 &hubbub_reg,
1036 &hubbub_shift,
1037 &hubbub_mask,
1038 dcn3_1_ip.det_buffer_size_kbytes,
1039 dcn3_1_ip.pixel_chunk_size_kbytes,
1040 dcn3_1_ip.config_return_buffer_size_in_kbytes);
1041
1042
1043 for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1044 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1045
1046 vmid->ctx = ctx;
1047
1048 vmid->regs = &vmid_regs[i];
1049 vmid->shifts = &vmid_shifts;
1050 vmid->masks = &vmid_masks;
1051 }
1052
1053 return &hubbub3->base;
1054 }
1055
dcn31_timing_generator_create(struct dc_context * ctx,uint32_t instance)1056 static struct timing_generator *dcn31_timing_generator_create(
1057 struct dc_context *ctx,
1058 uint32_t instance)
1059 {
1060 struct optc *tgn10 =
1061 kzalloc(sizeof(struct optc), GFP_KERNEL);
1062
1063 if (!tgn10)
1064 return NULL;
1065
1066 tgn10->base.inst = instance;
1067 tgn10->base.ctx = ctx;
1068
1069 tgn10->tg_regs = &optc_regs[instance];
1070 tgn10->tg_shift = &optc_shift;
1071 tgn10->tg_mask = &optc_mask;
1072
1073 dcn31_timing_generator_init(tgn10);
1074
1075 return &tgn10->base;
1076 }
1077
1078 static const struct encoder_feature_support link_enc_feature = {
1079 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1080 .max_hdmi_pixel_clock = 600000,
1081 .hdmi_ycbcr420_supported = true,
1082 .dp_ycbcr420_supported = true,
1083 .fec_supported = true,
1084 .flags.bits.IS_HBR2_CAPABLE = true,
1085 .flags.bits.IS_HBR3_CAPABLE = true,
1086 .flags.bits.IS_TPS3_CAPABLE = true,
1087 .flags.bits.IS_TPS4_CAPABLE = true
1088 };
1089
dcn31_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1090 static struct link_encoder *dcn31_link_encoder_create(
1091 struct dc_context *ctx,
1092 const struct encoder_init_data *enc_init_data)
1093 {
1094 struct dcn20_link_encoder *enc20 =
1095 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1096
1097 if (!enc20)
1098 return NULL;
1099
1100 dcn31_link_encoder_construct(enc20,
1101 enc_init_data,
1102 &link_enc_feature,
1103 &link_enc_regs[enc_init_data->transmitter],
1104 &link_enc_aux_regs[enc_init_data->channel - 1],
1105 &link_enc_hpd_regs[enc_init_data->hpd_source],
1106 &le_shift,
1107 &le_mask);
1108
1109 return &enc20->enc10.base;
1110 }
1111
1112 /* Create a minimal link encoder object not associated with a particular
1113 * physical connector.
1114 * resource_funcs.link_enc_create_minimal
1115 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1116 static struct link_encoder *dcn31_link_enc_create_minimal(
1117 struct dc_context *ctx, enum engine_id eng_id)
1118 {
1119 struct dcn20_link_encoder *enc20;
1120
1121 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1122 return NULL;
1123
1124 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1125 if (!enc20)
1126 return NULL;
1127
1128 dcn31_link_encoder_construct_minimal(
1129 enc20,
1130 ctx,
1131 &link_enc_feature,
1132 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1133 eng_id);
1134
1135 return &enc20->enc10.base;
1136 }
1137
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1138 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1139 {
1140 struct dcn31_panel_cntl *panel_cntl =
1141 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1142
1143 if (!panel_cntl)
1144 return NULL;
1145
1146 dcn31_panel_cntl_construct(panel_cntl, init_data);
1147
1148 return &panel_cntl->base;
1149 }
1150
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1151 static void read_dce_straps(
1152 struct dc_context *ctx,
1153 struct resource_straps *straps)
1154 {
1155 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1156 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1157
1158 }
1159
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1160 static struct audio *dcn31_create_audio(
1161 struct dc_context *ctx, unsigned int inst)
1162 {
1163 return dce_audio_create(ctx, inst,
1164 &audio_regs[inst], &audio_shift, &audio_mask);
1165 }
1166
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1167 static struct vpg *dcn31_vpg_create(
1168 struct dc_context *ctx,
1169 uint32_t inst)
1170 {
1171 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1172
1173 if (!vpg31)
1174 return NULL;
1175
1176 vpg31_construct(vpg31, ctx, inst,
1177 &vpg_regs[inst],
1178 &vpg_shift,
1179 &vpg_mask);
1180
1181 return &vpg31->base;
1182 }
1183
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1184 static struct afmt *dcn31_afmt_create(
1185 struct dc_context *ctx,
1186 uint32_t inst)
1187 {
1188 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1189
1190 if (!afmt31)
1191 return NULL;
1192
1193 afmt31_construct(afmt31, ctx, inst,
1194 &afmt_regs[inst],
1195 &afmt_shift,
1196 &afmt_mask);
1197
1198 // Light sleep by default, no need to power down here
1199
1200 return &afmt31->base;
1201 }
1202
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1203 static struct apg *dcn31_apg_create(
1204 struct dc_context *ctx,
1205 uint32_t inst)
1206 {
1207 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1208
1209 if (!apg31)
1210 return NULL;
1211
1212 apg31_construct(apg31, ctx, inst,
1213 &apg_regs[inst],
1214 &apg_shift,
1215 &apg_mask);
1216
1217 return &apg31->base;
1218 }
1219
dcn31_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1220 static struct stream_encoder *dcn31_stream_encoder_create(
1221 enum engine_id eng_id,
1222 struct dc_context *ctx)
1223 {
1224 struct dcn10_stream_encoder *enc1;
1225 struct vpg *vpg;
1226 struct afmt *afmt;
1227 int vpg_inst;
1228 int afmt_inst;
1229
1230 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1231 if (eng_id <= ENGINE_ID_DIGF) {
1232 vpg_inst = eng_id;
1233 afmt_inst = eng_id;
1234 } else
1235 return NULL;
1236
1237 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1238 vpg = dcn31_vpg_create(ctx, vpg_inst);
1239 afmt = dcn31_afmt_create(ctx, afmt_inst);
1240
1241 if (!enc1 || !vpg || !afmt) {
1242 kfree(enc1);
1243 kfree(vpg);
1244 kfree(afmt);
1245 return NULL;
1246 }
1247
1248 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1249 eng_id, vpg, afmt,
1250 &stream_enc_regs[eng_id],
1251 &se_shift, &se_mask);
1252
1253 return &enc1->base;
1254 }
1255
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1256 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1257 enum engine_id eng_id,
1258 struct dc_context *ctx)
1259 {
1260 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1261 struct vpg *vpg;
1262 struct apg *apg;
1263 uint32_t hpo_dp_inst;
1264 uint32_t vpg_inst;
1265 uint32_t apg_inst;
1266
1267 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1268 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1269
1270 /* Mapping of VPG register blocks to HPO DP block instance:
1271 * VPG[6] -> HPO_DP[0]
1272 * VPG[7] -> HPO_DP[1]
1273 * VPG[8] -> HPO_DP[2]
1274 * VPG[9] -> HPO_DP[3]
1275 */
1276 vpg_inst = hpo_dp_inst + 6;
1277
1278 /* Mapping of APG register blocks to HPO DP block instance:
1279 * APG[0] -> HPO_DP[0]
1280 * APG[1] -> HPO_DP[1]
1281 * APG[2] -> HPO_DP[2]
1282 * APG[3] -> HPO_DP[3]
1283 */
1284 apg_inst = hpo_dp_inst;
1285
1286 /* allocate HPO stream encoder and create VPG sub-block */
1287 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1288 vpg = dcn31_vpg_create(ctx, vpg_inst);
1289 apg = dcn31_apg_create(ctx, apg_inst);
1290
1291 if (!hpo_dp_enc31 || !vpg || !apg) {
1292 kfree(hpo_dp_enc31);
1293 kfree(vpg);
1294 kfree(apg);
1295 return NULL;
1296 }
1297
1298 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1299 hpo_dp_inst, eng_id, vpg, apg,
1300 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1301 &hpo_dp_se_shift, &hpo_dp_se_mask);
1302
1303 return &hpo_dp_enc31->base;
1304 }
1305
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1306 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1307 uint8_t inst,
1308 struct dc_context *ctx)
1309 {
1310 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1311
1312 /* allocate HPO link encoder */
1313 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1314
1315 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1316 &hpo_dp_link_enc_regs[inst],
1317 &hpo_dp_le_shift, &hpo_dp_le_mask);
1318
1319 return &hpo_dp_enc31->base;
1320 }
1321
dcn31_hwseq_create(struct dc_context * ctx)1322 static struct dce_hwseq *dcn31_hwseq_create(
1323 struct dc_context *ctx)
1324 {
1325 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1326
1327 if (hws) {
1328 hws->ctx = ctx;
1329 hws->regs = &hwseq_reg;
1330 hws->shifts = &hwseq_shift;
1331 hws->masks = &hwseq_mask;
1332 }
1333 return hws;
1334 }
1335 static const struct resource_create_funcs res_create_funcs = {
1336 .read_dce_straps = read_dce_straps,
1337 .create_audio = dcn31_create_audio,
1338 .create_stream_encoder = dcn31_stream_encoder_create,
1339 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1340 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1341 .create_hwseq = dcn31_hwseq_create,
1342 };
1343
dcn31_resource_destruct(struct dcn31_resource_pool * pool)1344 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1345 {
1346 unsigned int i;
1347
1348 for (i = 0; i < pool->base.stream_enc_count; i++) {
1349 if (pool->base.stream_enc[i] != NULL) {
1350 if (pool->base.stream_enc[i]->vpg != NULL) {
1351 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1352 pool->base.stream_enc[i]->vpg = NULL;
1353 }
1354 if (pool->base.stream_enc[i]->afmt != NULL) {
1355 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1356 pool->base.stream_enc[i]->afmt = NULL;
1357 }
1358 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1359 pool->base.stream_enc[i] = NULL;
1360 }
1361 }
1362
1363 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1364 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1365 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1366 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1367 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1368 }
1369 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1370 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1371 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1372 }
1373 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1374 pool->base.hpo_dp_stream_enc[i] = NULL;
1375 }
1376 }
1377
1378 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1379 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1380 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1381 pool->base.hpo_dp_link_enc[i] = NULL;
1382 }
1383 }
1384
1385 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1386 if (pool->base.dscs[i] != NULL)
1387 dcn20_dsc_destroy(&pool->base.dscs[i]);
1388 }
1389
1390 if (pool->base.mpc != NULL) {
1391 kfree(TO_DCN20_MPC(pool->base.mpc));
1392 pool->base.mpc = NULL;
1393 }
1394 if (pool->base.hubbub != NULL) {
1395 kfree(pool->base.hubbub);
1396 pool->base.hubbub = NULL;
1397 }
1398 for (i = 0; i < pool->base.pipe_count; i++) {
1399 if (pool->base.dpps[i] != NULL)
1400 dcn31_dpp_destroy(&pool->base.dpps[i]);
1401
1402 if (pool->base.ipps[i] != NULL)
1403 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1404
1405 if (pool->base.hubps[i] != NULL) {
1406 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1407 pool->base.hubps[i] = NULL;
1408 }
1409
1410 if (pool->base.irqs != NULL) {
1411 dal_irq_service_destroy(&pool->base.irqs);
1412 }
1413 }
1414
1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1416 if (pool->base.engines[i] != NULL)
1417 dce110_engine_destroy(&pool->base.engines[i]);
1418 if (pool->base.hw_i2cs[i] != NULL) {
1419 kfree(pool->base.hw_i2cs[i]);
1420 pool->base.hw_i2cs[i] = NULL;
1421 }
1422 if (pool->base.sw_i2cs[i] != NULL) {
1423 kfree(pool->base.sw_i2cs[i]);
1424 pool->base.sw_i2cs[i] = NULL;
1425 }
1426 }
1427
1428 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1429 if (pool->base.opps[i] != NULL)
1430 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1431 }
1432
1433 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1434 if (pool->base.timing_generators[i] != NULL) {
1435 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1436 pool->base.timing_generators[i] = NULL;
1437 }
1438 }
1439
1440 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1441 if (pool->base.dwbc[i] != NULL) {
1442 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1443 pool->base.dwbc[i] = NULL;
1444 }
1445 if (pool->base.mcif_wb[i] != NULL) {
1446 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1447 pool->base.mcif_wb[i] = NULL;
1448 }
1449 }
1450
1451 for (i = 0; i < pool->base.audio_count; i++) {
1452 if (pool->base.audios[i])
1453 dce_aud_destroy(&pool->base.audios[i]);
1454 }
1455
1456 for (i = 0; i < pool->base.clk_src_count; i++) {
1457 if (pool->base.clock_sources[i] != NULL) {
1458 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1459 pool->base.clock_sources[i] = NULL;
1460 }
1461 }
1462
1463 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1464 if (pool->base.mpc_lut[i] != NULL) {
1465 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1466 pool->base.mpc_lut[i] = NULL;
1467 }
1468 if (pool->base.mpc_shaper[i] != NULL) {
1469 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1470 pool->base.mpc_shaper[i] = NULL;
1471 }
1472 }
1473
1474 if (pool->base.dp_clock_source != NULL) {
1475 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1476 pool->base.dp_clock_source = NULL;
1477 }
1478
1479 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1480 if (pool->base.multiple_abms[i] != NULL)
1481 dce_abm_destroy(&pool->base.multiple_abms[i]);
1482 }
1483
1484 if (pool->base.psr != NULL)
1485 dmub_psr_destroy(&pool->base.psr);
1486
1487 if (pool->base.replay != NULL)
1488 dmub_replay_destroy(&pool->base.replay);
1489
1490 if (pool->base.dccg != NULL)
1491 dcn_dccg_destroy(&pool->base.dccg);
1492 }
1493
dcn31_hubp_create(struct dc_context * ctx,uint32_t inst)1494 static struct hubp *dcn31_hubp_create(
1495 struct dc_context *ctx,
1496 uint32_t inst)
1497 {
1498 struct dcn20_hubp *hubp2 =
1499 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1500
1501 if (!hubp2)
1502 return NULL;
1503
1504 if (hubp31_construct(hubp2, ctx, inst,
1505 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1506 return &hubp2->base;
1507
1508 BREAK_TO_DEBUGGER();
1509 kfree(hubp2);
1510 return NULL;
1511 }
1512
dcn31_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1513 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1514 {
1515 int i;
1516 uint32_t pipe_count = pool->res_cap->num_dwb;
1517
1518 for (i = 0; i < pipe_count; i++) {
1519 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1520 GFP_KERNEL);
1521
1522 if (!dwbc30) {
1523 dm_error("DC: failed to create dwbc30!\n");
1524 return false;
1525 }
1526
1527 dcn30_dwbc_construct(dwbc30, ctx,
1528 &dwbc30_regs[i],
1529 &dwbc30_shift,
1530 &dwbc30_mask,
1531 i);
1532
1533 pool->dwbc[i] = &dwbc30->base;
1534 }
1535 return true;
1536 }
1537
dcn31_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1538 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1539 {
1540 int i;
1541 uint32_t pipe_count = pool->res_cap->num_dwb;
1542
1543 for (i = 0; i < pipe_count; i++) {
1544 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1545 GFP_KERNEL);
1546
1547 if (!mcif_wb30) {
1548 dm_error("DC: failed to create mcif_wb30!\n");
1549 return false;
1550 }
1551
1552 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1553 &mcif_wb30_regs[i],
1554 &mcif_wb30_shift,
1555 &mcif_wb30_mask,
1556 i);
1557
1558 pool->mcif_wb[i] = &mcif_wb30->base;
1559 }
1560 return true;
1561 }
1562
dcn31_dsc_create(struct dc_context * ctx,uint32_t inst)1563 static struct display_stream_compressor *dcn31_dsc_create(
1564 struct dc_context *ctx, uint32_t inst)
1565 {
1566 struct dcn20_dsc *dsc =
1567 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1568
1569 if (!dsc) {
1570 BREAK_TO_DEBUGGER();
1571 return NULL;
1572 }
1573
1574 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1575 return &dsc->base;
1576 }
1577
dcn31_destroy_resource_pool(struct resource_pool ** pool)1578 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1579 {
1580 struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1581
1582 dcn31_resource_destruct(dcn31_pool);
1583 kfree(dcn31_pool);
1584 *pool = NULL;
1585 }
1586
dcn31_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1587 static struct clock_source *dcn31_clock_source_create(
1588 struct dc_context *ctx,
1589 struct dc_bios *bios,
1590 enum clock_source_id id,
1591 const struct dce110_clk_src_regs *regs,
1592 bool dp_clk_src)
1593 {
1594 struct dce110_clk_src *clk_src =
1595 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1596
1597 if (!clk_src)
1598 return NULL;
1599
1600 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1601 regs, &cs_shift, &cs_mask)) {
1602 clk_src->base.dp_clk_src = dp_clk_src;
1603 return &clk_src->base;
1604 }
1605
1606 kfree(clk_src);
1607 BREAK_TO_DEBUGGER();
1608 return NULL;
1609 }
1610
is_dual_plane(enum surface_pixel_format format)1611 static bool is_dual_plane(enum surface_pixel_format format)
1612 {
1613 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1614 }
1615
dcn31x_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1616 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
1617 struct dc_state *context,
1618 display_e2e_pipe_params_st *pipes,
1619 bool fast_validate)
1620 {
1621 uint32_t pipe_cnt;
1622 int i;
1623
1624 dc_assert_fp_enabled();
1625
1626 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1627
1628 for (i = 0; i < pipe_cnt; i++) {
1629 pipes[i].pipe.src.gpuvm = 1;
1630 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
1631 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1632 pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;
1633 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1634 pipes[i].pipe.src.hostvm = false;
1635 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1636 pipes[i].pipe.src.hostvm = true;
1637 }
1638 return pipe_cnt;
1639 }
1640
dcn31_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1641 int dcn31_populate_dml_pipes_from_context(
1642 struct dc *dc, struct dc_state *context,
1643 display_e2e_pipe_params_st *pipes,
1644 bool fast_validate)
1645 {
1646 int i, pipe_cnt;
1647 struct resource_context *res_ctx = &context->res_ctx;
1648 struct pipe_ctx *pipe;
1649 bool upscaled = false;
1650
1651 DC_FP_START();
1652 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1653 DC_FP_END();
1654
1655 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1656 struct dc_crtc_timing *timing;
1657
1658 if (!res_ctx->pipe_ctx[i].stream)
1659 continue;
1660 pipe = &res_ctx->pipe_ctx[i];
1661 timing = &pipe->stream->timing;
1662 if (pipe->plane_state &&
1663 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1664 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1665 upscaled = true;
1666
1667 /*
1668 * Immediate flip can be set dynamically after enabling the plane.
1669 * We need to require support for immediate flip or underflow can be
1670 * intermittently experienced depending on peak b/w requirements.
1671 */
1672 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1673 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1674 pipes[pipe_cnt].pipe.src.gpuvm = true;
1675 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1676 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1677 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1678 DC_FP_START();
1679 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1680 DC_FP_END();
1681
1682
1683 if (pipes[pipe_cnt].dout.dsc_enable) {
1684 switch (timing->display_color_depth) {
1685 case COLOR_DEPTH_888:
1686 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1687 break;
1688 case COLOR_DEPTH_101010:
1689 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1690 break;
1691 case COLOR_DEPTH_121212:
1692 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1693 break;
1694 default:
1695 ASSERT(0);
1696 break;
1697 }
1698 }
1699
1700 pipe_cnt++;
1701 }
1702 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1703 dc->config.enable_4to1MPC = false;
1704 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1705 if (is_dual_plane(pipe->plane_state->format)
1706 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1707 dc->config.enable_4to1MPC = true;
1708 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1709 /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1710 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1711 pipes[0].pipe.src.unbounded_req_mode = true;
1712 }
1713 } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1714 && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1715 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1716 } else if (context->stream_count >= 3 && upscaled) {
1717 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1718 }
1719
1720 return pipe_cnt;
1721 }
1722
dcn31_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)1723 void dcn31_calculate_wm_and_dlg(
1724 struct dc *dc, struct dc_state *context,
1725 display_e2e_pipe_params_st *pipes,
1726 int pipe_cnt,
1727 int vlevel)
1728 {
1729 DC_FP_START();
1730 dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1731 DC_FP_END();
1732 }
1733
1734 void
dcn31_populate_dml_writeback_from_context(struct dc * dc,struct resource_context * res_ctx,display_e2e_pipe_params_st * pipes)1735 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1736 struct resource_context *res_ctx,
1737 display_e2e_pipe_params_st *pipes)
1738 {
1739 DC_FP_START();
1740 dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1741 DC_FP_END();
1742 }
1743
1744 void
dcn31_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1745 dcn31_set_mcif_arb_params(struct dc *dc,
1746 struct dc_state *context,
1747 display_e2e_pipe_params_st *pipes,
1748 int pipe_cnt)
1749 {
1750 DC_FP_START();
1751 dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1752 DC_FP_END();
1753 }
1754
dcn31_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1755 bool dcn31_validate_bandwidth(struct dc *dc,
1756 struct dc_state *context,
1757 bool fast_validate)
1758 {
1759 bool out = false;
1760
1761 BW_VAL_TRACE_SETUP();
1762
1763 int vlevel = 0;
1764 int pipe_cnt = 0;
1765 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1766 DC_LOGGER_INIT(dc->ctx->logger);
1767
1768 BW_VAL_TRACE_COUNT();
1769
1770 DC_FP_START();
1771 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
1772 DC_FP_END();
1773
1774 // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
1775 if (pipe_cnt == 0)
1776 fast_validate = false;
1777
1778 if (!out)
1779 goto validate_fail;
1780
1781 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1782
1783 if (fast_validate) {
1784 BW_VAL_TRACE_SKIP(fast);
1785 goto validate_out;
1786 }
1787 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1788 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1789
1790 BW_VAL_TRACE_END_WATERMARKS();
1791
1792 goto validate_out;
1793
1794 validate_fail:
1795 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1796 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1797
1798 BW_VAL_TRACE_SKIP(fail);
1799 out = false;
1800
1801 validate_out:
1802 kfree(pipes);
1803
1804 BW_VAL_TRACE_FINISH();
1805
1806 return out;
1807 }
1808
dcn31_get_panel_config_defaults(struct dc_panel_config * panel_config)1809 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)
1810 {
1811 *panel_config = panel_config_defaults;
1812 }
1813
1814 static struct dc_cap_funcs cap_funcs = {
1815 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1816 };
1817
1818 static struct resource_funcs dcn31_res_pool_funcs = {
1819 .destroy = dcn31_destroy_resource_pool,
1820 .link_enc_create = dcn31_link_encoder_create,
1821 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1822 .link_encs_assign = link_enc_cfg_link_encs_assign,
1823 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1824 .panel_cntl_create = dcn31_panel_cntl_create,
1825 .validate_bandwidth = dcn31_validate_bandwidth,
1826 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1827 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1828 .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1829 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1830 .release_pipe = dcn20_release_pipe,
1831 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1832 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1833 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1834 .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1835 .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1836 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1837 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1838 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1839 .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1840 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1841 .get_panel_config_defaults = dcn31_get_panel_config_defaults,
1842 };
1843
dcn30_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1844 static struct clock_source *dcn30_clock_source_create(
1845 struct dc_context *ctx,
1846 struct dc_bios *bios,
1847 enum clock_source_id id,
1848 const struct dce110_clk_src_regs *regs,
1849 bool dp_clk_src)
1850 {
1851 struct dce110_clk_src *clk_src =
1852 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1853
1854 if (!clk_src)
1855 return NULL;
1856
1857 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1858 regs, &cs_shift, &cs_mask)) {
1859 clk_src->base.dp_clk_src = dp_clk_src;
1860 return &clk_src->base;
1861 }
1862
1863 BREAK_TO_DEBUGGER();
1864 return NULL;
1865 }
1866
dcn31_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn31_resource_pool * pool)1867 static bool dcn31_resource_construct(
1868 uint8_t num_virtual_links,
1869 struct dc *dc,
1870 struct dcn31_resource_pool *pool)
1871 {
1872 int i;
1873 struct dc_context *ctx = dc->ctx;
1874 struct irq_service_init_data init_data;
1875
1876 ctx->dc_bios->regs = &bios_regs;
1877
1878 pool->base.res_cap = &res_cap_dcn31;
1879
1880 pool->base.funcs = &dcn31_res_pool_funcs;
1881
1882 /*************************************************
1883 * Resource + asic cap harcoding *
1884 *************************************************/
1885 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1886 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1887 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1888 dc->caps.max_downscale_ratio = 600;
1889 dc->caps.i2c_speed_in_khz = 100;
1890 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1891 dc->caps.max_cursor_size = 256;
1892 dc->caps.min_horizontal_blanking_period = 80;
1893 dc->caps.dmdata_alloc_size = 2048;
1894
1895 dc->caps.max_slave_planes = 2;
1896 dc->caps.max_slave_yuv_planes = 2;
1897 dc->caps.max_slave_rgb_planes = 2;
1898 dc->caps.post_blend_color_processing = true;
1899 dc->caps.force_dp_tps4_for_cp2520 = true;
1900 if (dc->config.forceHBR2CP2520)
1901 dc->caps.force_dp_tps4_for_cp2520 = false;
1902 dc->caps.dp_hpo = true;
1903 dc->caps.dp_hdmi21_pcon_support = true;
1904 dc->caps.edp_dsc_support = true;
1905 dc->caps.extended_aux_timeout_support = true;
1906 dc->caps.dmcub_support = true;
1907 dc->caps.is_apu = true;
1908 dc->caps.zstate_support = true;
1909
1910 /* Color pipeline capabilities */
1911 dc->caps.color.dpp.dcn_arch = 1;
1912 dc->caps.color.dpp.input_lut_shared = 0;
1913 dc->caps.color.dpp.icsc = 1;
1914 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1915 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1916 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1917 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1918 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1919 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1920 dc->caps.color.dpp.post_csc = 1;
1921 dc->caps.color.dpp.gamma_corr = 1;
1922 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1923
1924 dc->caps.color.dpp.hw_3d_lut = 1;
1925 dc->caps.color.dpp.ogam_ram = 1;
1926 // no OGAM ROM on DCN301
1927 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1928 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1929 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1930 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1931 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1932 dc->caps.color.dpp.ocsc = 0;
1933
1934 dc->caps.color.mpc.gamut_remap = 1;
1935 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1936 dc->caps.color.mpc.ogam_ram = 1;
1937 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1938 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1939 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1940 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1941 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1942 dc->caps.color.mpc.ocsc = 1;
1943
1944 dc->config.use_old_fixed_vs_sequence = true;
1945
1946 /* Use pipe context based otg sync logic */
1947 dc->config.use_pipe_ctx_sync_logic = true;
1948
1949 /* read VBIOS LTTPR caps */
1950 {
1951 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1952 enum bp_result bp_query_result;
1953 uint8_t is_vbios_lttpr_enable = 0;
1954
1955 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1956 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1957 }
1958
1959 /* interop bit is implicit */
1960 {
1961 dc->caps.vbios_lttpr_aware = true;
1962 }
1963 }
1964
1965 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1966 dc->debug = debug_defaults_drv;
1967
1968 // Init the vm_helper
1969 if (dc->vm_helper)
1970 vm_helper_init(dc->vm_helper, 16);
1971
1972 /*************************************************
1973 * Create resources *
1974 *************************************************/
1975
1976 /* Clock Sources for Pixel Clock*/
1977 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1978 dcn30_clock_source_create(ctx, ctx->dc_bios,
1979 CLOCK_SOURCE_COMBO_PHY_PLL0,
1980 &clk_src_regs[0], false);
1981 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1982 dcn30_clock_source_create(ctx, ctx->dc_bios,
1983 CLOCK_SOURCE_COMBO_PHY_PLL1,
1984 &clk_src_regs[1], false);
1985 /*move phypllx_pixclk_resync to dmub next*/
1986 if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1987 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1988 dcn30_clock_source_create(ctx, ctx->dc_bios,
1989 CLOCK_SOURCE_COMBO_PHY_PLL2,
1990 &clk_src_regs_b0[2], false);
1991 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1992 dcn30_clock_source_create(ctx, ctx->dc_bios,
1993 CLOCK_SOURCE_COMBO_PHY_PLL3,
1994 &clk_src_regs_b0[3], false);
1995 } else {
1996 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1997 dcn30_clock_source_create(ctx, ctx->dc_bios,
1998 CLOCK_SOURCE_COMBO_PHY_PLL2,
1999 &clk_src_regs[2], false);
2000 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2001 dcn30_clock_source_create(ctx, ctx->dc_bios,
2002 CLOCK_SOURCE_COMBO_PHY_PLL3,
2003 &clk_src_regs[3], false);
2004 }
2005
2006 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2007 dcn30_clock_source_create(ctx, ctx->dc_bios,
2008 CLOCK_SOURCE_COMBO_PHY_PLL4,
2009 &clk_src_regs[4], false);
2010
2011 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2012
2013 /* todo: not reuse phy_pll registers */
2014 pool->base.dp_clock_source =
2015 dcn31_clock_source_create(ctx, ctx->dc_bios,
2016 CLOCK_SOURCE_ID_DP_DTO,
2017 &clk_src_regs[0], true);
2018
2019 for (i = 0; i < pool->base.clk_src_count; i++) {
2020 if (pool->base.clock_sources[i] == NULL) {
2021 dm_error("DC: failed to create clock sources!\n");
2022 BREAK_TO_DEBUGGER();
2023 goto create_fail;
2024 }
2025 }
2026
2027 /* TODO: DCCG */
2028 pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2029 if (pool->base.dccg == NULL) {
2030 dm_error("DC: failed to create dccg!\n");
2031 BREAK_TO_DEBUGGER();
2032 goto create_fail;
2033 }
2034
2035 /* TODO: IRQ */
2036 init_data.ctx = dc->ctx;
2037 pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2038 if (!pool->base.irqs)
2039 goto create_fail;
2040
2041 /* HUBBUB */
2042 pool->base.hubbub = dcn31_hubbub_create(ctx);
2043 if (pool->base.hubbub == NULL) {
2044 BREAK_TO_DEBUGGER();
2045 dm_error("DC: failed to create hubbub!\n");
2046 goto create_fail;
2047 }
2048
2049 /* HUBPs, DPPs, OPPs and TGs */
2050 for (i = 0; i < pool->base.pipe_count; i++) {
2051 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2052 if (pool->base.hubps[i] == NULL) {
2053 BREAK_TO_DEBUGGER();
2054 dm_error(
2055 "DC: failed to create hubps!\n");
2056 goto create_fail;
2057 }
2058
2059 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2060 if (pool->base.dpps[i] == NULL) {
2061 BREAK_TO_DEBUGGER();
2062 dm_error(
2063 "DC: failed to create dpps!\n");
2064 goto create_fail;
2065 }
2066 }
2067
2068 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2069 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2070 if (pool->base.opps[i] == NULL) {
2071 BREAK_TO_DEBUGGER();
2072 dm_error(
2073 "DC: failed to create output pixel processor!\n");
2074 goto create_fail;
2075 }
2076 }
2077
2078 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2079 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2080 ctx, i);
2081 if (pool->base.timing_generators[i] == NULL) {
2082 BREAK_TO_DEBUGGER();
2083 dm_error("DC: failed to create tg!\n");
2084 goto create_fail;
2085 }
2086 }
2087 pool->base.timing_generator_count = i;
2088
2089 /* PSR */
2090 pool->base.psr = dmub_psr_create(ctx);
2091 if (pool->base.psr == NULL) {
2092 dm_error("DC: failed to create psr obj!\n");
2093 BREAK_TO_DEBUGGER();
2094 goto create_fail;
2095 }
2096
2097 /* Replay */
2098 pool->base.replay = dmub_replay_create(ctx);
2099 if (pool->base.replay == NULL) {
2100 dm_error("DC: failed to create replay obj!\n");
2101 BREAK_TO_DEBUGGER();
2102 goto create_fail;
2103 }
2104
2105 /* ABM */
2106 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2107 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2108 &abm_regs[i],
2109 &abm_shift,
2110 &abm_mask);
2111 if (pool->base.multiple_abms[i] == NULL) {
2112 dm_error("DC: failed to create abm for pipe %d!\n", i);
2113 BREAK_TO_DEBUGGER();
2114 goto create_fail;
2115 }
2116 }
2117
2118 /* MPC and DSC */
2119 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2120 if (pool->base.mpc == NULL) {
2121 BREAK_TO_DEBUGGER();
2122 dm_error("DC: failed to create mpc!\n");
2123 goto create_fail;
2124 }
2125
2126 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2127 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2128 if (pool->base.dscs[i] == NULL) {
2129 BREAK_TO_DEBUGGER();
2130 dm_error("DC: failed to create display stream compressor %d!\n", i);
2131 goto create_fail;
2132 }
2133 }
2134
2135 /* DWB and MMHUBBUB */
2136 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2137 BREAK_TO_DEBUGGER();
2138 dm_error("DC: failed to create dwbc!\n");
2139 goto create_fail;
2140 }
2141
2142 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2143 BREAK_TO_DEBUGGER();
2144 dm_error("DC: failed to create mcif_wb!\n");
2145 goto create_fail;
2146 }
2147
2148 /* AUX and I2C */
2149 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2150 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2151 if (pool->base.engines[i] == NULL) {
2152 BREAK_TO_DEBUGGER();
2153 dm_error(
2154 "DC:failed to create aux engine!!\n");
2155 goto create_fail;
2156 }
2157 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2158 if (pool->base.hw_i2cs[i] == NULL) {
2159 BREAK_TO_DEBUGGER();
2160 dm_error(
2161 "DC:failed to create hw i2c!!\n");
2162 goto create_fail;
2163 }
2164 pool->base.sw_i2cs[i] = NULL;
2165 }
2166
2167 if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2168 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2169 !dc->debug.dpia_debug.bits.disable_dpia) {
2170 /* YELLOW CARP B0 has 4 DPIA's */
2171 pool->base.usb4_dpia_count = 4;
2172 }
2173
2174 if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)
2175 pool->base.usb4_dpia_count = 4;
2176
2177 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2178 if (!resource_construct(num_virtual_links, dc, &pool->base,
2179 &res_create_funcs))
2180 goto create_fail;
2181
2182 /* HW Sequencer and Plane caps */
2183 dcn31_hw_sequencer_construct(dc);
2184
2185 dc->caps.max_planes = pool->base.pipe_count;
2186
2187 for (i = 0; i < dc->caps.max_planes; ++i)
2188 dc->caps.planes[i] = plane_cap;
2189
2190 dc->cap_funcs = cap_funcs;
2191
2192 dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2193
2194 return true;
2195
2196 create_fail:
2197 dcn31_resource_destruct(pool);
2198
2199 return false;
2200 }
2201
dcn31_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2202 struct resource_pool *dcn31_create_resource_pool(
2203 const struct dc_init_data *init_data,
2204 struct dc *dc)
2205 {
2206 struct dcn31_resource_pool *pool =
2207 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2208
2209 if (!pool)
2210 return NULL;
2211
2212 if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2213 return &pool->base;
2214
2215 BREAK_TO_DEBUGGER();
2216 kfree(pool);
2217 return NULL;
2218 }
2219