1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dcn35_optc.h"
28
29 #include "dcn30/dcn30_optc.h"
30 #include "dcn31/dcn31_optc.h"
31 #include "dcn32/dcn32_optc.h"
32 #include "reg_helper.h"
33 #include "dc.h"
34 #include "dcn_calc_math.h"
35
36 #define REG(reg)\
37 optc1->tg_regs->reg
38
39 #define CTX \
40 optc1->base.ctx
41
42 #undef FN
43 #define FN(reg_name, field_name) \
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
45
46 /**
47 * optc35_set_odm_combine() - Enable CRTC - call ASIC Control Object to enable Timing generator.
48 *
49 * @optc: Output Pipe Timing Combine instance reference.
50 * @opp_id: Output Plane Processor instance ID.
51 * @opp_cnt: Output Plane Processor count.
52 * @timing: Timing parameters used to configure DCN blocks.
53 *
54 * Return: void.
55 */
optc35_set_odm_combine(struct timing_generator * optc,int * opp_id,int opp_cnt,struct dc_crtc_timing * timing)56 static void optc35_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
57 struct dc_crtc_timing *timing)
58 {
59 struct optc *optc1 = DCN10TG_FROM_TG(optc);
60 uint32_t memory_mask = 0;
61 int h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
62 int mpcc_hactive = h_active / opp_cnt;
63 /* Each memory instance is 2048x(314x2) bits to support half line of 4096 */
64 int odm_mem_count = (h_active + 2047) / 2048;
65
66 /*
67 * display <= 4k : 2 memories + 2 pipes
68 * 4k < display <= 8k : 4 memories + 2 pipes
69 * 8k < display <= 12k : 6 memories + 4 pipes
70 */
71 if (opp_cnt == 4) {
72 if (odm_mem_count <= 2)
73 memory_mask = 0x3;
74 else if (odm_mem_count <= 4)
75 memory_mask = 0xf;
76 else
77 memory_mask = 0x3f;
78 } else {
79 if (odm_mem_count <= 2)
80 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
81 else if (odm_mem_count <= 4)
82 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
83 else
84 memory_mask = 0x77;
85 }
86
87 REG_SET(OPTC_MEMORY_CONFIG, 0,
88 OPTC_MEM_SEL, memory_mask);
89
90 if (opp_cnt == 2) {
91 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
92 OPTC_NUM_OF_INPUT_SEGMENT, 1,
93 OPTC_SEG0_SRC_SEL, opp_id[0],
94 OPTC_SEG1_SRC_SEL, opp_id[1]);
95 } else if (opp_cnt == 4) {
96 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
97 OPTC_NUM_OF_INPUT_SEGMENT, 3,
98 OPTC_SEG0_SRC_SEL, opp_id[0],
99 OPTC_SEG1_SRC_SEL, opp_id[1],
100 OPTC_SEG2_SRC_SEL, opp_id[2],
101 OPTC_SEG3_SRC_SEL, opp_id[3]);
102 }
103
104 REG_UPDATE(OPTC_WIDTH_CONTROL,
105 OPTC_SEGMENT_WIDTH, mpcc_hactive);
106
107 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
108 optc1->opp_count = opp_cnt;
109 }
110
optc35_enable_crtc(struct timing_generator * optc)111 static bool optc35_enable_crtc(struct timing_generator *optc)
112 {
113 struct optc *optc1 = DCN10TG_FROM_TG(optc);
114
115 /* opp instance for OTG, 1 to 1 mapping and odm will adjust */
116 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
117 OPTC_SEG0_SRC_SEL, optc->inst);
118
119 /* VTG enable first is for HW workaround */
120 REG_UPDATE(CONTROL,
121 VTG0_ENABLE, 1);
122
123 REG_SEQ_START();
124
125 /* Enable CRTC */
126 REG_UPDATE_2(OTG_CONTROL,
127 OTG_DISABLE_POINT_CNTL, 2,
128 OTG_MASTER_EN, 1);
129
130 REG_SEQ_SUBMIT();
131 REG_SEQ_WAIT_DONE();
132
133 return true;
134 }
135
136 /* disable_crtc */
optc35_disable_crtc(struct timing_generator * optc)137 static bool optc35_disable_crtc(struct timing_generator *optc)
138 {
139 struct optc *optc1 = DCN10TG_FROM_TG(optc);
140
141 REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
142 OPTC_SEG0_SRC_SEL, 0xf,
143 OPTC_SEG1_SRC_SEL, 0xf,
144 OPTC_SEG2_SRC_SEL, 0xf,
145 OPTC_SEG3_SRC_SEL, 0xf,
146 OPTC_NUM_OF_INPUT_SEGMENT, 0);
147
148 REG_UPDATE(OPTC_MEMORY_CONFIG,
149 OPTC_MEM_SEL, 0);
150
151 /* disable otg request until end of the first line
152 * in the vertical blank region
153 */
154 REG_UPDATE(OTG_CONTROL,
155 OTG_MASTER_EN, 0);
156
157 REG_UPDATE(CONTROL,
158 VTG0_ENABLE, 0);
159
160 /* CRTC disabled, so disable clock. */
161 REG_WAIT(OTG_CLOCK_CONTROL,
162 OTG_BUSY, 0,
163 1, 100000);
164 optc1_clear_optc_underflow(optc);
165
166 return true;
167 }
168
optc35_phantom_crtc_post_enable(struct timing_generator * optc)169 static void optc35_phantom_crtc_post_enable(struct timing_generator *optc)
170 {
171 struct optc *optc1 = DCN10TG_FROM_TG(optc);
172
173 /* Disable immediately. */
174 REG_UPDATE_2(OTG_CONTROL, OTG_DISABLE_POINT_CNTL, 0, OTG_MASTER_EN, 0);
175
176 /* CRTC disabled, so disable clock. */
177 REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
178 }
179
optc35_configure_crc(struct timing_generator * optc,const struct crc_params * params)180 static bool optc35_configure_crc(struct timing_generator *optc,
181 const struct crc_params *params)
182 {
183 struct optc *optc1 = DCN10TG_FROM_TG(optc);
184
185 if (!optc1_is_tg_enabled(optc))
186 return false;
187 REG_WRITE(OTG_CRC_CNTL, 0);
188 if (!params->enable)
189 return true;
190 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
191 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
192 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
193 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
194 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
195 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
196 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
197 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
198 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
199 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
200 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
201 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
202 if (optc1->base.ctx->dc->debug.otg_crc_db && optc1->tg_mask->OTG_CRC_WINDOW_DB_EN != 0) {
203 REG_UPDATE_4(OTG_CRC_CNTL,
204 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
205 OTG_CRC0_SELECT, params->selection,
206 OTG_CRC_EN, 1,
207 OTG_CRC_WINDOW_DB_EN, 1);
208 } else
209 REG_UPDATE_3(OTG_CRC_CNTL,
210 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
211 OTG_CRC0_SELECT, params->selection,
212 OTG_CRC_EN, 1);
213 return true;
214 }
215
216 static struct timing_generator_funcs dcn35_tg_funcs = {
217 .validate_timing = optc1_validate_timing,
218 .program_timing = optc1_program_timing,
219 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
220 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
221 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
222 .program_global_sync = optc1_program_global_sync,
223 .enable_crtc = optc35_enable_crtc,
224 .disable_crtc = optc35_disable_crtc,
225 .immediate_disable_crtc = optc31_immediate_disable_crtc,
226 .phantom_crtc_post_enable = optc35_phantom_crtc_post_enable,
227 /* used by enable_timing_synchronization. Not need for FPGA */
228 .is_counter_moving = optc1_is_counter_moving,
229 .get_position = optc1_get_position,
230 .get_frame_count = optc1_get_vblank_counter,
231 .get_scanoutpos = optc1_get_crtc_scanoutpos,
232 .get_otg_active_size = optc1_get_otg_active_size,
233 .set_early_control = optc1_set_early_control,
234 /* used by enable_timing_synchronization. Not need for FPGA */
235 .wait_for_state = optc1_wait_for_state,
236 .set_blank_color = optc3_program_blank_color,
237 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
238 .triplebuffer_lock = optc3_triplebuffer_lock,
239 .triplebuffer_unlock = optc2_triplebuffer_unlock,
240 .enable_reset_trigger = optc1_enable_reset_trigger,
241 .enable_crtc_reset = optc1_enable_crtc_reset,
242 .disable_reset_trigger = optc1_disable_reset_trigger,
243 .lock = optc3_lock,
244 .unlock = optc1_unlock,
245 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
246 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
247 .enable_optc_clock = optc1_enable_optc_clock,
248 .set_drr = optc31_set_drr,
249 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
250 .set_vtotal_min_max = optc1_set_vtotal_min_max,
251 .set_static_screen_control = optc1_set_static_screen_control,
252 .program_stereo = optc1_program_stereo,
253 .is_stereo_left_eye = optc1_is_stereo_left_eye,
254 .tg_init = optc3_tg_init,
255 .is_tg_enabled = optc1_is_tg_enabled,
256 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
257 .clear_optc_underflow = optc1_clear_optc_underflow,
258 .setup_global_swap_lock = NULL,
259 .get_crc = optc1_get_crc,
260 .configure_crc = optc35_configure_crc,
261 .set_dsc_config = optc3_set_dsc_config,
262 .get_dsc_status = optc2_get_dsc_status,
263 .set_dwb_source = NULL,
264 .set_odm_bypass = optc32_set_odm_bypass,
265 .set_odm_combine = optc35_set_odm_combine,
266 .get_optc_source = optc2_get_optc_source,
267 .set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
268 .set_out_mux = optc3_set_out_mux,
269 .set_drr_trigger_window = optc3_set_drr_trigger_window,
270 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
271 .set_gsl = optc2_set_gsl,
272 .set_gsl_source_select = optc2_set_gsl_source_select,
273 .set_vtg_params = optc1_set_vtg_params,
274 .program_manual_trigger = optc2_program_manual_trigger,
275 .setup_manual_trigger = optc2_setup_manual_trigger,
276 .get_hw_timing = optc1_get_hw_timing,
277 .init_odm = optc3_init_odm,
278 };
279
dcn35_timing_generator_init(struct optc * optc1)280 void dcn35_timing_generator_init(struct optc *optc1)
281 {
282 optc1->base.funcs = &dcn35_tg_funcs;
283
284 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
285 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
286
287 optc1->min_h_blank = 32;
288 optc1->min_v_blank = 3;
289 optc1->min_v_blank_interlace = 5;
290 optc1->min_h_sync_width = 4;
291 optc1->min_v_sync_width = 1;
292
293 dcn35_timing_generator_set_fgcg(
294 optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc);
295 }
296
dcn35_timing_generator_set_fgcg(struct optc * optc1,bool enable)297 void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable)
298 {
299 REG_UPDATE(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, !enable);
300 }
301