1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright 2023 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #ifndef __DCN35_DPP_H__
28 #define __DCN35_DPP_H__
29 
30 #include "dcn32/dcn32_dpp.h"
31 
32 #define DPP_REG_LIST_SH_MASK_DCN35(mask_sh)  \
33 	DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \
34 		TF_SF(DPP_TOP0_DPP_CONTROL, DPP_FGCG_REP_DIS, mask_sh)
35 
36 #define DPP_REG_FIELD_LIST_DCN35(type)         \
37 	struct {                               \
38 		DPP_REG_FIELD_LIST_DCN3(type); \
39 		type DPP_FGCG_REP_DIS;         \
40 	}
41 
42 struct dcn35_dpp_shift {
43 	DPP_REG_FIELD_LIST_DCN35(uint8_t);
44 };
45 
46 struct dcn35_dpp_mask {
47 	DPP_REG_FIELD_LIST_DCN35(uint32_t);
48 };
49 
50 bool dpp35_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx,
51 		     uint32_t inst, const struct dcn3_dpp_registers *tf_regs,
52 		     const struct dcn35_dpp_shift *tf_shift,
53 		     const struct dcn35_dpp_mask *tf_mask);
54 
55 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
56 
57 #endif // __DCN35_DPP_H
58