1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "core_types.h"
28 #include "dcn35_dpp.h"
29 #include "reg_helper.h"
30
31 #define REG(reg) dpp->tf_regs->reg
32
33 #define CTX dpp->base.ctx
34
35 #undef FN
36 #define FN(reg_name, field_name) \
37 ((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \
38 ((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name
39
dpp35_construct(struct dcn3_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn3_dpp_registers * tf_regs,const struct dcn35_dpp_shift * tf_shift,const struct dcn35_dpp_mask * tf_mask)40 bool dpp35_construct(struct dcn3_dpp *dpp, struct dc_context *ctx,
41 uint32_t inst, const struct dcn3_dpp_registers *tf_regs,
42 const struct dcn35_dpp_shift *tf_shift,
43 const struct dcn35_dpp_mask *tf_mask)
44 {
45 return dpp32_construct(dpp, ctx, inst, tf_regs,
46 (const struct dcn3_dpp_shift *)(tf_shift),
47 (const struct dcn3_dpp_mask *)(tf_mask));
48 }
49
dpp35_set_fgcg(struct dcn3_dpp * dpp,bool enable)50 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)
51 {
52 REG_UPDATE(DPP_CONTROL, DPP_FGCG_REP_DIS, !enable);
53 }
54