1 /* Copyright 2023 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __VPE_6_1_FW_IF_H_ 26 #define __VPE_6_1_FW_IF_H_ 27 28 /**************** 29 * VPE OP Codes 30 ****************/ 31 enum VPE_CMD_OPCODE { 32 VPE_CMD_OPCODE_NOP = 0x0, 33 VPE_CMD_OPCODE_VPE_DESC = 0x1, 34 VPE_CMD_OPCODE_PLANE_CFG = 0x2, 35 VPE_CMD_OPCODE_VPEP_CFG = 0x3, 36 VPE_CMD_OPCODE_INDIRECT = 0x4, 37 VPE_CMD_OPCODE_FENCE = 0x5, 38 VPE_CMD_OPCODE_TRAP = 0x6, 39 VPE_CMD_OPCODE_REG_WRITE = 0x7, 40 VPE_CMD_OPCODE_POLL_REGMEM = 0x8, 41 VPE_CMD_OPCODE_COND_EXE = 0x9, 42 VPE_CMD_OPCODE_ATOMIC = 0xA, 43 VPE_CMD_OPCODE_PLANE_FILL = 0xB, 44 VPE_CMD_OPCODE_TIMESTAMP = 0xD 45 }; 46 47 /** Generic Command Header 48 * Generic Commands include: 49 * Noop, Fence, Trap, 50 * RegisterWrite, PollRegisterWriteMemory, 51 * SetLocalTimestamp, GetLocalTimestamp 52 * GetGlobalGPUTimestamp */ 53 #define VPE_HEADER_SUB_OPCODE__SHIFT 8 54 #define VPE_HEADER_SUB_OPCODE_MASK 0x0000FF00 55 #define VPE_HEADER_OPCODE__SHIFT 0 56 #define VPE_HEADER_OPCODE_MASK 0x000000FF 57 58 #define VPE_CMD_HEADER(op, subop) \ 59 (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \ 60 ((op << VPE_HEADER_OPCODE__SHIFT) & VPE_HEADER_OPCODE_MASK)) 61 62 63 /*************************** 64 * VPE NOP 65 ***************************/ 66 #define VPE_CMD_NOP_HEADER_COUNT__SHIFT 16 67 #define VPE_CMD_NOP_HEADER_COUNT_MASK 0x00003FFF 68 69 #define VPE_CMD_NOP_HEADER_COUNT(count) \ 70 (((count) & VPE_CMD_NOP_HEADER_COUNT_MASK) << VPE_CMD_NOP_HEADER_COUNT__SHIFT) 71 72 /*************************** 73 * VPE Descriptor 74 ***************************/ 75 #define VPE_DESC_CD__SHIFT 16 76 #define VPE_DESC_CD_MASK 0x000F0000 77 78 #define VPE_DESC_CMD_HEADER(cd) \ 79 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | \ 80 (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) 81 82 /*************************** 83 * VPE Plane Config 84 ***************************/ 85 enum VPE_PLANE_CFG_SUBOP { 86 VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0, 87 VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1, 88 VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x2 89 }; 90 91 #define VPE_PLANE_CFG_ONE_PLANE 0 92 #define VPE_PLANE_CFG_TWO_PLANES 1 93 94 #define VPE_PLANE_CFG_NPS0__SHIFT 16 95 #define VPE_PLANE_CFG_NPS0_MASK 0x00030000 96 97 #define VPE_PLANE_CFG_NPD0__SHIFT 18 98 #define VPE_PLANE_CFG_NPD0_MASK 0x000C0000 99 100 #define VPE_PLANE_CFG_NPS1__SHIFT 20 101 #define VPE_PLANE_CFG_NPS1_MASK 0x00300000 102 103 #define VPE_PLANE_CFG_NPD1__SHIFT 22 104 #define VPE_PLANE_CFG_NPD1_MASK 0x00C00000 105 106 #define VPE_PLANE_CFG_TMZ__SHIFT 16 107 #define VPE_PLANE_CFG_TMZ_MASK 0x00010000 108 109 #define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3 110 #define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8 111 112 #define VPE_PLANE_CFG_ROTATION__SHIFT 0 113 #define VPE_PLANE_CFG_ROTATION_MASK 0x00000003 114 115 #define VPE_PLANE_ADDR_LO__SHIFT 0 116 #define VPE_PLANE_ADDR_LO_MASK 0xFFFFFF00 117 118 #define VPE_PLANE_CFG_PITCH__SHIFT 0 119 #define VPE_PLANE_CFG_PITCH_MASK 0x00003FFF 120 121 #define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16 122 #define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0x3FFF0000 123 #define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0 124 #define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x00003FFF 125 126 127 #define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16 128 #define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x1FFF0000 129 #define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 13 130 #define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0x0000E000 131 #define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0 132 #define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00001FFF 133 134 enum VPE_PLANE_CFG_ELEMENT_SIZE { 135 VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0, 136 VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1, 137 VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2, 138 VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3 139 }; 140 141 #define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \ 142 (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \ 143 (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \ 144 (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \ 145 (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \ 146 (((npd0) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK)) 147 148 149 /************************ 150 * VPEP Config 151 ************************/ 152 enum VPE_VPEP_CFG_SUBOP { 153 VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0, 154 VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1 155 }; 156 157 158 // Direct Config Command Header 159 #define VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT 16 160 #define VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK 0xFFFF0000 161 162 #define VPE_DIR_CFG_CMD_HEADER(subop, arr_sz) \ 163 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, subop) | \ 164 (((arr_sz) << VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT) & VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK)) 165 166 167 #define VPE_DIR_CFG_PKT_REGISTER_OFFSET__SHIFT 2 168 #define VPE_DIR_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC 169 170 #define VPE_DIR_CFG_PKT_DATA_SIZE__SHIFT 20 171 #define VPE_DIR_CFG_PKT_DATA_SIZE_MASK 0xFFF00000 172 173 174 // InDirect Config Command Header 175 #define VPE_IND_CFG_HEADER_NUM_DST__SHIFT 28 176 #define VPE_IND_CFG_HEADER_NUM_DST_MASK 0xF0000000 177 178 #define VPE_IND_CFG_CMD_HEADER(subop, num_dst) \ 179 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, subop) | \ 180 (((num_dst) << VPE_IND_CFG_HEADER_NUM_DST__SHIFT) & VPE_IND_CFG_HEADER_NUM_DST_MASK)) 181 182 // Indirect Buffer Command Header 183 #define VPE_CMD_INDIRECT_HEADER_VMID__SHIFT 16 184 #define VPE_CMD_INDIRECT_HEADER_VMID_MASK 0x0000000F 185 #define VPE_CMD_INDIRECT_HEADER_VMID(vmid) \ 186 (((vmid) & VPE_CMD_INDIRECT_HEADER_VMID_MASK) << VPE_CMD_INDIRECT_HEADER_VMID__SHIFT) 187 188 189 /************************** 190 * Poll Reg/Mem Sub-OpCode 191 **************************/ 192 enum VPE_POLL_REGMEM_SUBOP { 193 VPE_POLL_REGMEM_SUBOP_REGMEM = 0x0, 194 VPE_POLL_REGMEM_SUBOP_REGMEM_WRITE = 0x1 195 }; 196 197 #define VPE_CMD_POLL_REGMEM_HEADER_FUNC__SHIFT 28 198 #define VPE_CMD_POLL_REGMEM_HEADER_FUNC_MASK 0x00000007 199 #define VPE_CMD_POLL_REGMEM_HEADER_FUNC(func) \ 200 (((func) & VPE_CMD_POLL_REGMEM_HEADER_FUNC_MASK) << VPE_CMD_POLL_REGMEM_HEADER_FUNC__SHIFT) 201 202 #define VPE_CMD_POLL_REGMEM_HEADER_MEM__SHIFT 31 203 #define VPE_CMD_POLL_REGMEM_HEADER_MEM_MASK 0x00000001 204 #define VPE_CMD_POLL_REGMEM_HEADER_MEM(mem) \ 205 (((mem) & VPE_CMD_POLL_REGMEM_HEADER_MEM_MASK) << VPE_CMD_POLL_REGMEM_HEADER_MEM__SHIFT) 206 207 #define VPE_CMD_POLL_REGMEM_DW5_INTERVAL__SHIFT 0 208 #define VPE_CMD_POLL_REGMEM_DW5_INTERVAL_MASK 0x0000FFFF 209 #define VPE_CMD_POLL_REGMEM_DW5_INTERVAL(interval) \ 210 (((interval) & VPE_CMD_POLL_REGMEM_DW5_INTERVAL_MASK) << VPE_CMD_POLL_REGMEM_DW5_INTERVAL__SHIFT) 211 212 #define VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT__SHIFT 16 213 #define VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT_MASK 0x00000FFF 214 #define VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(count) \ 215 (((count) & VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT_MASK) << VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT__SHIFT) 216 217 #endif 218