1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * MPC83xx suspend support
4 *
5 * Author: Scott Wood <scottwood@freescale.com>
6 *
7 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
8 */
9
10 #include <linux/pm.h>
11 #include <linux/types.h>
12 #include <linux/ioport.h>
13 #include <linux/interrupt.h>
14 #include <linux/wait.h>
15 #include <linux/sched/signal.h>
16 #include <linux/kthread.h>
17 #include <linux/freezer.h>
18 #include <linux/suspend.h>
19 #include <linux/fsl_devices.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/platform_device.h>
23 #include <linux/export.h>
24
25 #include <asm/reg.h>
26 #include <asm/io.h>
27 #include <asm/time.h>
28 #include <asm/mpc6xx.h>
29 #include <asm/switch_to.h>
30
31 #include <sysdev/fsl_soc.h>
32
33 #define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
34 #define PMCCR1_NEXT_STATE_SHIFT 2
35 #define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
36 #define IMMR_SYSCR_OFFSET 0x100
37 #define IMMR_RCW_OFFSET 0x900
38 #define RCW_PCI_HOST 0x80000000
39
40 void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
41
42 struct mpc83xx_pmc {
43 u32 config;
44 #define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
45 #define PMCCR_SLPEN 1 /* System low power enable */
46
47 u32 event;
48 u32 mask;
49 /* All but PMCI are deep-sleep only */
50 #define PMCER_GPIO 0x100
51 #define PMCER_PCI 0x080
52 #define PMCER_USB 0x040
53 #define PMCER_ETSEC1 0x020
54 #define PMCER_ETSEC2 0x010
55 #define PMCER_TIMER 0x008
56 #define PMCER_INT1 0x004
57 #define PMCER_INT2 0x002
58 #define PMCER_PMCI 0x001
59 #define PMCER_ALL 0x1FF
60
61 /* deep-sleep only */
62 u32 config1;
63 #define PMCCR1_USE_STATE 0x80000000
64 #define PMCCR1_PME_EN 0x00000080
65 #define PMCCR1_ASSERT_PME 0x00000040
66 #define PMCCR1_POWER_OFF 0x00000020
67
68 /* deep-sleep only */
69 u32 config2;
70 };
71
72 struct mpc83xx_rcw {
73 u32 rcwlr;
74 u32 rcwhr;
75 };
76
77 struct mpc83xx_clock {
78 u32 spmr;
79 u32 occr;
80 u32 sccr;
81 };
82
83 struct mpc83xx_syscr {
84 __be32 sgprl;
85 __be32 sgprh;
86 __be32 spridr;
87 __be32 :32;
88 __be32 spcr;
89 __be32 sicrl;
90 __be32 sicrh;
91 };
92
93 struct mpc83xx_saved {
94 u32 sicrl;
95 u32 sicrh;
96 u32 sccr;
97 };
98
99 struct pmc_type {
100 int has_deep_sleep;
101 };
102
103 static int has_deep_sleep, deep_sleeping;
104 static int pmc_irq;
105 static struct mpc83xx_pmc __iomem *pmc_regs;
106 static struct mpc83xx_clock __iomem *clock_regs;
107 static struct mpc83xx_syscr __iomem *syscr_regs;
108 static struct mpc83xx_saved saved_regs;
109 static int is_pci_agent, wake_from_pci;
110 static phys_addr_t immrbase;
111 static int pci_pm_state;
112 static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
113
fsl_deep_sleep(void)114 int fsl_deep_sleep(void)
115 {
116 return deep_sleeping;
117 }
118 EXPORT_SYMBOL(fsl_deep_sleep);
119
mpc83xx_change_state(void)120 static int mpc83xx_change_state(void)
121 {
122 u32 curr_state;
123 u32 reg_cfg1 = in_be32(&pmc_regs->config1);
124
125 if (is_pci_agent) {
126 pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
127 PMCCR1_NEXT_STATE_SHIFT;
128 curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
129
130 if (curr_state != pci_pm_state) {
131 reg_cfg1 &= ~PMCCR1_CURR_STATE;
132 reg_cfg1 |= pci_pm_state;
133 out_be32(&pmc_regs->config1, reg_cfg1);
134
135 wake_up(&agent_wq);
136 return 1;
137 }
138 }
139
140 return 0;
141 }
142
pmc_irq_handler(int irq,void * dev_id)143 static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
144 {
145 u32 event = in_be32(&pmc_regs->event);
146 int ret = IRQ_NONE;
147
148 if (mpc83xx_change_state())
149 ret = IRQ_HANDLED;
150
151 if (event) {
152 out_be32(&pmc_regs->event, event);
153 ret = IRQ_HANDLED;
154 }
155
156 return ret;
157 }
158
mpc83xx_suspend_restore_regs(void)159 static void mpc83xx_suspend_restore_regs(void)
160 {
161 out_be32(&syscr_regs->sicrl, saved_regs.sicrl);
162 out_be32(&syscr_regs->sicrh, saved_regs.sicrh);
163 out_be32(&clock_regs->sccr, saved_regs.sccr);
164 }
165
mpc83xx_suspend_save_regs(void)166 static void mpc83xx_suspend_save_regs(void)
167 {
168 saved_regs.sicrl = in_be32(&syscr_regs->sicrl);
169 saved_regs.sicrh = in_be32(&syscr_regs->sicrh);
170 saved_regs.sccr = in_be32(&clock_regs->sccr);
171 }
172
mpc83xx_suspend_enter(suspend_state_t state)173 static int mpc83xx_suspend_enter(suspend_state_t state)
174 {
175 int ret = -EAGAIN;
176
177 /* Don't go to sleep if there's a race where pci_pm_state changes
178 * between the agent thread checking it and the PM code disabling
179 * interrupts.
180 */
181 if (wake_from_pci) {
182 if (pci_pm_state != (deep_sleeping ? 3 : 2))
183 goto out;
184
185 out_be32(&pmc_regs->config1,
186 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
187 }
188
189 /* Put the system into low-power mode and the RAM
190 * into self-refresh mode once the core goes to
191 * sleep.
192 */
193
194 out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
195
196 /* If it has deep sleep (i.e. it's an 831x or compatible),
197 * disable power to the core upon entering sleep mode. This will
198 * require going through the boot firmware upon a wakeup event.
199 */
200
201 if (deep_sleeping) {
202 mpc83xx_suspend_save_regs();
203
204 out_be32(&pmc_regs->mask, PMCER_ALL);
205
206 out_be32(&pmc_regs->config1,
207 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
208
209 enable_kernel_fp();
210
211 mpc83xx_enter_deep_sleep(immrbase);
212
213 out_be32(&pmc_regs->config1,
214 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
215
216 out_be32(&pmc_regs->mask, PMCER_PMCI);
217
218 mpc83xx_suspend_restore_regs();
219 } else {
220 out_be32(&pmc_regs->mask, PMCER_PMCI);
221
222 mpc6xx_enter_standby();
223 }
224
225 ret = 0;
226
227 out:
228 out_be32(&pmc_regs->config1,
229 in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
230
231 return ret;
232 }
233
mpc83xx_suspend_end(void)234 static void mpc83xx_suspend_end(void)
235 {
236 deep_sleeping = 0;
237 }
238
mpc83xx_suspend_valid(suspend_state_t state)239 static int mpc83xx_suspend_valid(suspend_state_t state)
240 {
241 return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
242 }
243
mpc83xx_suspend_begin(suspend_state_t state)244 static int mpc83xx_suspend_begin(suspend_state_t state)
245 {
246 switch (state) {
247 case PM_SUSPEND_STANDBY:
248 deep_sleeping = 0;
249 return 0;
250
251 case PM_SUSPEND_MEM:
252 if (has_deep_sleep)
253 deep_sleeping = 1;
254
255 return 0;
256
257 default:
258 return -EINVAL;
259 }
260 }
261
agent_thread_fn(void * data)262 static int agent_thread_fn(void *data)
263 {
264 set_freezable();
265
266 while (1) {
267 wait_event_freezable(agent_wq, pci_pm_state >= 2);
268
269 if (signal_pending(current) || pci_pm_state < 2)
270 continue;
271
272 /* With a preemptible kernel (or SMP), this could race with
273 * a userspace-driven suspend request. It's probably best
274 * to avoid mixing the two with such a configuration (or
275 * else fix it by adding a mutex to state_store that we can
276 * synchronize with).
277 */
278
279 wake_from_pci = 1;
280
281 pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
282 PM_SUSPEND_STANDBY);
283
284 wake_from_pci = 0;
285 }
286
287 return 0;
288 }
289
mpc83xx_set_agent(void)290 static void mpc83xx_set_agent(void)
291 {
292 out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
293 out_be32(&pmc_regs->mask, PMCER_PMCI);
294
295 kthread_run(agent_thread_fn, NULL, "PCI power mgt");
296 }
297
mpc83xx_is_pci_agent(void)298 static int mpc83xx_is_pci_agent(void)
299 {
300 struct mpc83xx_rcw __iomem *rcw_regs;
301 int ret;
302
303 rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
304 sizeof(struct mpc83xx_rcw));
305
306 if (!rcw_regs)
307 return -ENOMEM;
308
309 ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
310
311 iounmap(rcw_regs);
312 return ret;
313 }
314
315 static const struct platform_suspend_ops mpc83xx_suspend_ops = {
316 .valid = mpc83xx_suspend_valid,
317 .begin = mpc83xx_suspend_begin,
318 .enter = mpc83xx_suspend_enter,
319 .end = mpc83xx_suspend_end,
320 };
321
322 static struct pmc_type pmc_types[] = {
323 {
324 .has_deep_sleep = 1,
325 },
326 {
327 .has_deep_sleep = 0,
328 }
329 };
330
331 static const struct of_device_id pmc_match[] = {
332 {
333 .compatible = "fsl,mpc8313-pmc",
334 .data = &pmc_types[0],
335 },
336 {
337 .compatible = "fsl,mpc8349-pmc",
338 .data = &pmc_types[1],
339 },
340 {}
341 };
342
pmc_probe(struct platform_device * ofdev)343 static int pmc_probe(struct platform_device *ofdev)
344 {
345 struct device_node *np = ofdev->dev.of_node;
346 struct resource res;
347 const struct pmc_type *type;
348 int ret = 0;
349
350 type = of_device_get_match_data(&ofdev->dev);
351 if (!type)
352 return -EINVAL;
353
354 if (!of_device_is_available(np))
355 return -ENODEV;
356
357 has_deep_sleep = type->has_deep_sleep;
358 immrbase = get_immrbase();
359
360 is_pci_agent = mpc83xx_is_pci_agent();
361 if (is_pci_agent < 0)
362 return is_pci_agent;
363
364 ret = of_address_to_resource(np, 0, &res);
365 if (ret)
366 return -ENODEV;
367
368 pmc_irq = irq_of_parse_and_map(np, 0);
369 if (pmc_irq) {
370 ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
371 "pmc", ofdev);
372
373 if (ret)
374 return -EBUSY;
375 }
376
377 pmc_regs = ioremap(res.start, sizeof(*pmc_regs));
378
379 if (!pmc_regs) {
380 ret = -ENOMEM;
381 goto out;
382 }
383
384 ret = of_address_to_resource(np, 1, &res);
385 if (ret) {
386 ret = -ENODEV;
387 goto out_pmc;
388 }
389
390 clock_regs = ioremap(res.start, sizeof(*clock_regs));
391
392 if (!clock_regs) {
393 ret = -ENOMEM;
394 goto out_pmc;
395 }
396
397 if (has_deep_sleep) {
398 syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
399 sizeof(*syscr_regs));
400 if (!syscr_regs) {
401 ret = -ENOMEM;
402 goto out_syscr;
403 }
404 }
405
406 if (is_pci_agent)
407 mpc83xx_set_agent();
408
409 suspend_set_ops(&mpc83xx_suspend_ops);
410 return 0;
411
412 out_syscr:
413 iounmap(clock_regs);
414 out_pmc:
415 iounmap(pmc_regs);
416 out:
417 if (pmc_irq)
418 free_irq(pmc_irq, ofdev);
419
420 return ret;
421 }
422
423 static struct platform_driver pmc_driver = {
424 .driver = {
425 .name = "mpc83xx-pmc",
426 .of_match_table = pmc_match,
427 .suppress_bind_attrs = true,
428 },
429 .probe = pmc_probe,
430 };
431
432 builtin_platform_driver(pmc_driver);
433