1 /*
2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/clocksource.h>
34 #include <linux/highmem.h>
35 #include <linux/log2.h>
36 #include <linux/ptp_clock_kernel.h>
37 #include <rdma/mlx5-abi.h>
38 #include "lib/eq.h"
39 #include "en.h"
40 #include "clock.h"
41 
42 enum {
43 	MLX5_PIN_MODE_IN		= 0x0,
44 	MLX5_PIN_MODE_OUT		= 0x1,
45 };
46 
47 enum {
48 	MLX5_OUT_PATTERN_PULSE		= 0x0,
49 	MLX5_OUT_PATTERN_PERIODIC	= 0x1,
50 };
51 
52 enum {
53 	MLX5_EVENT_MODE_DISABLE	= 0x0,
54 	MLX5_EVENT_MODE_REPETETIVE	= 0x1,
55 	MLX5_EVENT_MODE_ONCE_TILL_ARM	= 0x2,
56 };
57 
58 enum {
59 	MLX5_MTPPS_FS_ENABLE			= BIT(0x0),
60 	MLX5_MTPPS_FS_PATTERN			= BIT(0x2),
61 	MLX5_MTPPS_FS_PIN_MODE			= BIT(0x3),
62 	MLX5_MTPPS_FS_TIME_STAMP		= BIT(0x4),
63 	MLX5_MTPPS_FS_OUT_PULSE_DURATION	= BIT(0x5),
64 	MLX5_MTPPS_FS_ENH_OUT_PER_ADJ		= BIT(0x7),
65 	MLX5_MTPPS_FS_NPPS_PERIOD               = BIT(0x9),
66 	MLX5_MTPPS_FS_OUT_PULSE_DURATION_NS     = BIT(0xa),
67 };
68 
69 enum {
70 	MLX5_MTUTC_OPERATION_ADJUST_TIME_MIN          = S16_MIN,
71 	MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX          = S16_MAX,
72 	MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN = -200000,
73 	MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX = 200000,
74 };
75 
mlx5_real_time_mode(struct mlx5_core_dev * mdev)76 static bool mlx5_real_time_mode(struct mlx5_core_dev *mdev)
77 {
78 	return (mlx5_is_real_time_rq(mdev) || mlx5_is_real_time_sq(mdev));
79 }
80 
mlx5_npps_real_time_supported(struct mlx5_core_dev * mdev)81 static bool mlx5_npps_real_time_supported(struct mlx5_core_dev *mdev)
82 {
83 	return (mlx5_real_time_mode(mdev) &&
84 		MLX5_CAP_MCAM_FEATURE(mdev, npps_period) &&
85 		MLX5_CAP_MCAM_FEATURE(mdev, out_pulse_duration_ns));
86 }
87 
mlx5_modify_mtutc_allowed(struct mlx5_core_dev * mdev)88 static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev)
89 {
90 	return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify);
91 }
92 
mlx5_ptp_shift_constant(u32 dev_freq_khz)93 static u32 mlx5_ptp_shift_constant(u32 dev_freq_khz)
94 {
95 	/* Optimal shift constant leads to corrections above just 1 scaled ppm.
96 	 *
97 	 * Two sets of equations are needed to derive the optimal shift
98 	 * constant for the cyclecounter.
99 	 *
100 	 *    dev_freq_khz * 1000 / 2^shift_constant = 1 scaled_ppm
101 	 *    ppb = scaled_ppm * 1000 / 2^16
102 	 *
103 	 * Using the two equations together
104 	 *
105 	 *    dev_freq_khz * 1000 / 1 scaled_ppm = 2^shift_constant
106 	 *    dev_freq_khz * 2^16 / 1 ppb = 2^shift_constant
107 	 *    dev_freq_khz = 2^(shift_constant - 16)
108 	 *
109 	 * then yields
110 	 *
111 	 *    shift_constant = ilog2(dev_freq_khz) + 16
112 	 */
113 
114 	return min(ilog2(dev_freq_khz) + 16,
115 		   ilog2((U32_MAX / NSEC_PER_MSEC) * dev_freq_khz));
116 }
117 
mlx5_ptp_getmaxphase(struct ptp_clock_info * ptp)118 static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp)
119 {
120 	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
121 	struct mlx5_core_dev *mdev;
122 
123 	mdev = container_of(clock, struct mlx5_core_dev, clock);
124 
125 	return MLX5_CAP_MCAM_FEATURE(mdev, mtutc_time_adjustment_extended_range) ?
126 		       MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX :
127 			     MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX;
128 }
129 
mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev * mdev,s64 delta)130 static bool mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev *mdev, s64 delta)
131 {
132 	s64 max = mlx5_ptp_getmaxphase(&mdev->clock.ptp_info);
133 
134 	if (delta < -max || delta > max)
135 		return false;
136 
137 	return true;
138 }
139 
mlx5_set_mtutc(struct mlx5_core_dev * dev,u32 * mtutc,u32 size)140 static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size)
141 {
142 	u32 out[MLX5_ST_SZ_DW(mtutc_reg)] = {};
143 
144 	if (!MLX5_CAP_MCAM_REG(dev, mtutc))
145 		return -EOPNOTSUPP;
146 
147 	return mlx5_core_access_reg(dev, mtutc, size, out, sizeof(out),
148 				    MLX5_REG_MTUTC, 0, 1);
149 }
150 
mlx5_read_time(struct mlx5_core_dev * dev,struct ptp_system_timestamp * sts,bool real_time)151 static u64 mlx5_read_time(struct mlx5_core_dev *dev,
152 			  struct ptp_system_timestamp *sts,
153 			  bool real_time)
154 {
155 	u32 timer_h, timer_h1, timer_l;
156 
157 	timer_h = ioread32be(real_time ? &dev->iseg->real_time_h :
158 			     &dev->iseg->internal_timer_h);
159 	ptp_read_system_prets(sts);
160 	timer_l = ioread32be(real_time ? &dev->iseg->real_time_l :
161 			     &dev->iseg->internal_timer_l);
162 	ptp_read_system_postts(sts);
163 	timer_h1 = ioread32be(real_time ? &dev->iseg->real_time_h :
164 			      &dev->iseg->internal_timer_h);
165 	if (timer_h != timer_h1) {
166 		/* wrap around */
167 		ptp_read_system_prets(sts);
168 		timer_l = ioread32be(real_time ? &dev->iseg->real_time_l :
169 				     &dev->iseg->internal_timer_l);
170 		ptp_read_system_postts(sts);
171 	}
172 
173 	return real_time ? REAL_TIME_TO_NS(timer_h1, timer_l) :
174 			   (u64)timer_l | (u64)timer_h1 << 32;
175 }
176 
read_internal_timer(const struct cyclecounter * cc)177 static u64 read_internal_timer(const struct cyclecounter *cc)
178 {
179 	struct mlx5_timer *timer = container_of(cc, struct mlx5_timer, cycles);
180 	struct mlx5_clock *clock = container_of(timer, struct mlx5_clock, timer);
181 	struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev,
182 						  clock);
183 
184 	return mlx5_read_time(mdev, NULL, false) & cc->mask;
185 }
186 
mlx5_update_clock_info_page(struct mlx5_core_dev * mdev)187 static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev)
188 {
189 	struct mlx5_ib_clock_info *clock_info = mdev->clock_info;
190 	struct mlx5_clock *clock = &mdev->clock;
191 	struct mlx5_timer *timer;
192 	u32 sign;
193 
194 	if (!clock_info)
195 		return;
196 
197 	sign = smp_load_acquire(&clock_info->sign);
198 	smp_store_mb(clock_info->sign,
199 		     sign | MLX5_IB_CLOCK_INFO_KERNEL_UPDATING);
200 
201 	timer = &clock->timer;
202 	clock_info->cycles = timer->tc.cycle_last;
203 	clock_info->mult   = timer->cycles.mult;
204 	clock_info->nsec   = timer->tc.nsec;
205 	clock_info->frac   = timer->tc.frac;
206 
207 	smp_store_release(&clock_info->sign,
208 			  sign + MLX5_IB_CLOCK_INFO_KERNEL_UPDATING * 2);
209 }
210 
mlx5_pps_out(struct work_struct * work)211 static void mlx5_pps_out(struct work_struct *work)
212 {
213 	struct mlx5_pps *pps_info = container_of(work, struct mlx5_pps,
214 						 out_work);
215 	struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock,
216 						pps_info);
217 	struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev,
218 						  clock);
219 	u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
220 	unsigned long flags;
221 	int i;
222 
223 	for (i = 0; i < clock->ptp_info.n_pins; i++) {
224 		u64 tstart;
225 
226 		write_seqlock_irqsave(&clock->lock, flags);
227 		tstart = clock->pps_info.start[i];
228 		clock->pps_info.start[i] = 0;
229 		write_sequnlock_irqrestore(&clock->lock, flags);
230 		if (!tstart)
231 			continue;
232 
233 		MLX5_SET(mtpps_reg, in, pin, i);
234 		MLX5_SET64(mtpps_reg, in, time_stamp, tstart);
235 		MLX5_SET(mtpps_reg, in, field_select, MLX5_MTPPS_FS_TIME_STAMP);
236 		mlx5_set_mtpps(mdev, in, sizeof(in));
237 	}
238 }
239 
mlx5_timestamp_overflow(struct work_struct * work)240 static void mlx5_timestamp_overflow(struct work_struct *work)
241 {
242 	struct delayed_work *dwork = to_delayed_work(work);
243 	struct mlx5_core_dev *mdev;
244 	struct mlx5_timer *timer;
245 	struct mlx5_clock *clock;
246 	unsigned long flags;
247 
248 	timer = container_of(dwork, struct mlx5_timer, overflow_work);
249 	clock = container_of(timer, struct mlx5_clock, timer);
250 	mdev = container_of(clock, struct mlx5_core_dev, clock);
251 
252 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
253 		goto out;
254 
255 	write_seqlock_irqsave(&clock->lock, flags);
256 	timecounter_read(&timer->tc);
257 	mlx5_update_clock_info_page(mdev);
258 	write_sequnlock_irqrestore(&clock->lock, flags);
259 
260 out:
261 	schedule_delayed_work(&timer->overflow_work, timer->overflow_period);
262 }
263 
mlx5_ptp_settime_real_time(struct mlx5_core_dev * mdev,const struct timespec64 * ts)264 static int mlx5_ptp_settime_real_time(struct mlx5_core_dev *mdev,
265 				      const struct timespec64 *ts)
266 {
267 	u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {};
268 
269 	if (!mlx5_modify_mtutc_allowed(mdev))
270 		return 0;
271 
272 	if (ts->tv_sec < 0 || ts->tv_sec > U32_MAX ||
273 	    ts->tv_nsec < 0 || ts->tv_nsec > NSEC_PER_SEC)
274 		return -EINVAL;
275 
276 	MLX5_SET(mtutc_reg, in, operation, MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE);
277 	MLX5_SET(mtutc_reg, in, utc_sec, ts->tv_sec);
278 	MLX5_SET(mtutc_reg, in, utc_nsec, ts->tv_nsec);
279 
280 	return mlx5_set_mtutc(mdev, in, sizeof(in));
281 }
282 
mlx5_ptp_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)283 static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts)
284 {
285 	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
286 	struct mlx5_timer *timer = &clock->timer;
287 	struct mlx5_core_dev *mdev;
288 	unsigned long flags;
289 	int err;
290 
291 	mdev = container_of(clock, struct mlx5_core_dev, clock);
292 	err = mlx5_ptp_settime_real_time(mdev, ts);
293 	if (err)
294 		return err;
295 
296 	write_seqlock_irqsave(&clock->lock, flags);
297 	timecounter_init(&timer->tc, &timer->cycles, timespec64_to_ns(ts));
298 	mlx5_update_clock_info_page(mdev);
299 	write_sequnlock_irqrestore(&clock->lock, flags);
300 
301 	return 0;
302 }
303 
304 static
mlx5_ptp_gettimex_real_time(struct mlx5_core_dev * mdev,struct ptp_system_timestamp * sts)305 struct timespec64 mlx5_ptp_gettimex_real_time(struct mlx5_core_dev *mdev,
306 					      struct ptp_system_timestamp *sts)
307 {
308 	struct timespec64 ts;
309 	u64 time;
310 
311 	time = mlx5_read_time(mdev, sts, true);
312 	ts = ns_to_timespec64(time);
313 	return ts;
314 }
315 
mlx5_ptp_gettimex(struct ptp_clock_info * ptp,struct timespec64 * ts,struct ptp_system_timestamp * sts)316 static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
317 			     struct ptp_system_timestamp *sts)
318 {
319 	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
320 	struct mlx5_timer *timer = &clock->timer;
321 	struct mlx5_core_dev *mdev;
322 	unsigned long flags;
323 	u64 cycles, ns;
324 
325 	mdev = container_of(clock, struct mlx5_core_dev, clock);
326 	if (mlx5_real_time_mode(mdev)) {
327 		*ts = mlx5_ptp_gettimex_real_time(mdev, sts);
328 		goto out;
329 	}
330 
331 	write_seqlock_irqsave(&clock->lock, flags);
332 	cycles = mlx5_read_time(mdev, sts, false);
333 	ns = timecounter_cyc2time(&timer->tc, cycles);
334 	write_sequnlock_irqrestore(&clock->lock, flags);
335 	*ts = ns_to_timespec64(ns);
336 out:
337 	return 0;
338 }
339 
mlx5_ptp_adjtime_real_time(struct mlx5_core_dev * mdev,s64 delta)340 static int mlx5_ptp_adjtime_real_time(struct mlx5_core_dev *mdev, s64 delta)
341 {
342 	u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {};
343 
344 	if (!mlx5_modify_mtutc_allowed(mdev))
345 		return 0;
346 
347 	/* HW time adjustment range is checked. If out of range, settime instead */
348 	if (!mlx5_is_mtutc_time_adj_cap(mdev, delta)) {
349 		struct timespec64 ts;
350 		s64 ns;
351 
352 		ts = mlx5_ptp_gettimex_real_time(mdev, NULL);
353 		ns = timespec64_to_ns(&ts) + delta;
354 		ts = ns_to_timespec64(ns);
355 		return mlx5_ptp_settime_real_time(mdev, &ts);
356 	}
357 
358 	MLX5_SET(mtutc_reg, in, operation, MLX5_MTUTC_OPERATION_ADJUST_TIME);
359 	MLX5_SET(mtutc_reg, in, time_adjustment, delta);
360 
361 	return mlx5_set_mtutc(mdev, in, sizeof(in));
362 }
363 
mlx5_ptp_adjtime(struct ptp_clock_info * ptp,s64 delta)364 static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
365 {
366 	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
367 	struct mlx5_timer *timer = &clock->timer;
368 	struct mlx5_core_dev *mdev;
369 	unsigned long flags;
370 	int err;
371 
372 	mdev = container_of(clock, struct mlx5_core_dev, clock);
373 
374 	err = mlx5_ptp_adjtime_real_time(mdev, delta);
375 	if (err)
376 		return err;
377 	write_seqlock_irqsave(&clock->lock, flags);
378 	timecounter_adjtime(&timer->tc, delta);
379 	mlx5_update_clock_info_page(mdev);
380 	write_sequnlock_irqrestore(&clock->lock, flags);
381 
382 	return 0;
383 }
384 
mlx5_ptp_adjphase(struct ptp_clock_info * ptp,s32 delta)385 static int mlx5_ptp_adjphase(struct ptp_clock_info *ptp, s32 delta)
386 {
387 	return mlx5_ptp_adjtime(ptp, delta);
388 }
389 
mlx5_ptp_freq_adj_real_time(struct mlx5_core_dev * mdev,long scaled_ppm)390 static int mlx5_ptp_freq_adj_real_time(struct mlx5_core_dev *mdev, long scaled_ppm)
391 {
392 	u32 in[MLX5_ST_SZ_DW(mtutc_reg)] = {};
393 
394 	if (!mlx5_modify_mtutc_allowed(mdev))
395 		return 0;
396 
397 	MLX5_SET(mtutc_reg, in, operation, MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC);
398 
399 	if (MLX5_CAP_MCAM_FEATURE(mdev, mtutc_freq_adj_units)) {
400 		MLX5_SET(mtutc_reg, in, freq_adj_units,
401 			 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM);
402 		MLX5_SET(mtutc_reg, in, freq_adjustment, scaled_ppm);
403 	} else {
404 		MLX5_SET(mtutc_reg, in, freq_adj_units, MLX5_MTUTC_FREQ_ADJ_UNITS_PPB);
405 		MLX5_SET(mtutc_reg, in, freq_adjustment, scaled_ppm_to_ppb(scaled_ppm));
406 	}
407 
408 	return mlx5_set_mtutc(mdev, in, sizeof(in));
409 }
410 
mlx5_ptp_adjfine(struct ptp_clock_info * ptp,long scaled_ppm)411 static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
412 {
413 	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
414 	struct mlx5_timer *timer = &clock->timer;
415 	struct mlx5_core_dev *mdev;
416 	unsigned long flags;
417 	u32 mult;
418 	int err;
419 
420 	mdev = container_of(clock, struct mlx5_core_dev, clock);
421 
422 	err = mlx5_ptp_freq_adj_real_time(mdev, scaled_ppm);
423 	if (err)
424 		return err;
425 
426 	mult = (u32)adjust_by_scaled_ppm(timer->nominal_c_mult, scaled_ppm);
427 
428 	write_seqlock_irqsave(&clock->lock, flags);
429 	timecounter_read(&timer->tc);
430 	timer->cycles.mult = mult;
431 	mlx5_update_clock_info_page(mdev);
432 	write_sequnlock_irqrestore(&clock->lock, flags);
433 
434 	return 0;
435 }
436 
mlx5_extts_configure(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)437 static int mlx5_extts_configure(struct ptp_clock_info *ptp,
438 				struct ptp_clock_request *rq,
439 				int on)
440 {
441 	struct mlx5_clock *clock =
442 			container_of(ptp, struct mlx5_clock, ptp_info);
443 	struct mlx5_core_dev *mdev =
444 			container_of(clock, struct mlx5_core_dev, clock);
445 	u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
446 	u32 field_select = 0;
447 	u8 pin_mode = 0;
448 	u8 pattern = 0;
449 	int pin = -1;
450 	int err = 0;
451 
452 	if (!MLX5_PPS_CAP(mdev))
453 		return -EOPNOTSUPP;
454 
455 	/* Reject requests with unsupported flags */
456 	if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
457 				PTP_RISING_EDGE |
458 				PTP_FALLING_EDGE |
459 				PTP_STRICT_FLAGS))
460 		return -EOPNOTSUPP;
461 
462 	/* Reject requests to enable time stamping on both edges. */
463 	if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
464 	    (rq->extts.flags & PTP_ENABLE_FEATURE) &&
465 	    (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
466 		return -EOPNOTSUPP;
467 
468 	if (rq->extts.index >= clock->ptp_info.n_pins)
469 		return -EINVAL;
470 
471 	pin = ptp_find_pin(clock->ptp, PTP_PF_EXTTS, rq->extts.index);
472 	if (pin < 0)
473 		return -EBUSY;
474 
475 	if (on) {
476 		pin_mode = MLX5_PIN_MODE_IN;
477 		pattern = !!(rq->extts.flags & PTP_FALLING_EDGE);
478 		field_select = MLX5_MTPPS_FS_PIN_MODE |
479 			       MLX5_MTPPS_FS_PATTERN |
480 			       MLX5_MTPPS_FS_ENABLE;
481 	} else {
482 		field_select = MLX5_MTPPS_FS_ENABLE;
483 	}
484 
485 	MLX5_SET(mtpps_reg, in, pin, pin);
486 	MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
487 	MLX5_SET(mtpps_reg, in, pattern, pattern);
488 	MLX5_SET(mtpps_reg, in, enable, on);
489 	MLX5_SET(mtpps_reg, in, field_select, field_select);
490 
491 	err = mlx5_set_mtpps(mdev, in, sizeof(in));
492 	if (err)
493 		return err;
494 
495 	return mlx5_set_mtppse(mdev, pin, 0,
496 			       MLX5_EVENT_MODE_REPETETIVE & on);
497 }
498 
find_target_cycles(struct mlx5_core_dev * mdev,s64 target_ns)499 static u64 find_target_cycles(struct mlx5_core_dev *mdev, s64 target_ns)
500 {
501 	struct mlx5_clock *clock = &mdev->clock;
502 	u64 cycles_now, cycles_delta;
503 	u64 nsec_now, nsec_delta;
504 	struct mlx5_timer *timer;
505 	unsigned long flags;
506 
507 	timer = &clock->timer;
508 
509 	cycles_now = mlx5_read_time(mdev, NULL, false);
510 	write_seqlock_irqsave(&clock->lock, flags);
511 	nsec_now = timecounter_cyc2time(&timer->tc, cycles_now);
512 	nsec_delta = target_ns - nsec_now;
513 	cycles_delta = div64_u64(nsec_delta << timer->cycles.shift,
514 				 timer->cycles.mult);
515 	write_sequnlock_irqrestore(&clock->lock, flags);
516 
517 	return cycles_now + cycles_delta;
518 }
519 
perout_conf_internal_timer(struct mlx5_core_dev * mdev,s64 sec)520 static u64 perout_conf_internal_timer(struct mlx5_core_dev *mdev, s64 sec)
521 {
522 	struct timespec64 ts = {};
523 	s64 target_ns;
524 
525 	ts.tv_sec = sec;
526 	target_ns = timespec64_to_ns(&ts);
527 
528 	return find_target_cycles(mdev, target_ns);
529 }
530 
perout_conf_real_time(s64 sec,u32 nsec)531 static u64 perout_conf_real_time(s64 sec, u32 nsec)
532 {
533 	return (u64)nsec | (u64)sec << 32;
534 }
535 
perout_conf_1pps(struct mlx5_core_dev * mdev,struct ptp_clock_request * rq,u64 * time_stamp,bool real_time)536 static int perout_conf_1pps(struct mlx5_core_dev *mdev, struct ptp_clock_request *rq,
537 			    u64 *time_stamp, bool real_time)
538 {
539 	struct timespec64 ts;
540 	s64 ns;
541 
542 	ts.tv_nsec = rq->perout.period.nsec;
543 	ts.tv_sec = rq->perout.period.sec;
544 	ns = timespec64_to_ns(&ts);
545 
546 	if ((ns >> 1) != 500000000LL)
547 		return -EINVAL;
548 
549 	*time_stamp = real_time ? perout_conf_real_time(rq->perout.start.sec, 0) :
550 		      perout_conf_internal_timer(mdev, rq->perout.start.sec);
551 
552 	return 0;
553 }
554 
555 #define MLX5_MAX_PULSE_DURATION (BIT(__mlx5_bit_sz(mtpps_reg, out_pulse_duration_ns)) - 1)
mlx5_perout_conf_out_pulse_duration(struct mlx5_core_dev * mdev,struct ptp_clock_request * rq,u32 * out_pulse_duration_ns)556 static int mlx5_perout_conf_out_pulse_duration(struct mlx5_core_dev *mdev,
557 					       struct ptp_clock_request *rq,
558 					       u32 *out_pulse_duration_ns)
559 {
560 	struct mlx5_pps *pps_info = &mdev->clock.pps_info;
561 	u32 out_pulse_duration;
562 	struct timespec64 ts;
563 
564 	if (rq->perout.flags & PTP_PEROUT_DUTY_CYCLE) {
565 		ts.tv_sec = rq->perout.on.sec;
566 		ts.tv_nsec = rq->perout.on.nsec;
567 		out_pulse_duration = (u32)timespec64_to_ns(&ts);
568 	} else {
569 		/* out_pulse_duration_ns should be up to 50% of the
570 		 * pulse period as default
571 		 */
572 		ts.tv_sec = rq->perout.period.sec;
573 		ts.tv_nsec = rq->perout.period.nsec;
574 		out_pulse_duration = (u32)timespec64_to_ns(&ts) >> 1;
575 	}
576 
577 	if (out_pulse_duration < pps_info->min_out_pulse_duration_ns ||
578 	    out_pulse_duration > MLX5_MAX_PULSE_DURATION) {
579 		mlx5_core_err(mdev, "NPPS pulse duration %u is not in [%llu, %lu]\n",
580 			      out_pulse_duration, pps_info->min_out_pulse_duration_ns,
581 			      MLX5_MAX_PULSE_DURATION);
582 		return -EINVAL;
583 	}
584 	*out_pulse_duration_ns = out_pulse_duration;
585 
586 	return 0;
587 }
588 
perout_conf_npps_real_time(struct mlx5_core_dev * mdev,struct ptp_clock_request * rq,u32 * field_select,u32 * out_pulse_duration_ns,u64 * period,u64 * time_stamp)589 static int perout_conf_npps_real_time(struct mlx5_core_dev *mdev, struct ptp_clock_request *rq,
590 				      u32 *field_select, u32 *out_pulse_duration_ns,
591 				      u64 *period, u64 *time_stamp)
592 {
593 	struct mlx5_pps *pps_info = &mdev->clock.pps_info;
594 	struct ptp_clock_time *time = &rq->perout.start;
595 	struct timespec64 ts;
596 
597 	ts.tv_sec = rq->perout.period.sec;
598 	ts.tv_nsec = rq->perout.period.nsec;
599 	if (timespec64_to_ns(&ts) < pps_info->min_npps_period) {
600 		mlx5_core_err(mdev, "NPPS period is lower than minimal npps period %llu\n",
601 			      pps_info->min_npps_period);
602 		return -EINVAL;
603 	}
604 	*period = perout_conf_real_time(rq->perout.period.sec, rq->perout.period.nsec);
605 
606 	if (mlx5_perout_conf_out_pulse_duration(mdev, rq, out_pulse_duration_ns))
607 		return -EINVAL;
608 
609 	*time_stamp = perout_conf_real_time(time->sec, time->nsec);
610 	*field_select |= MLX5_MTPPS_FS_NPPS_PERIOD |
611 			 MLX5_MTPPS_FS_OUT_PULSE_DURATION_NS;
612 
613 	return 0;
614 }
615 
mlx5_perout_verify_flags(struct mlx5_core_dev * mdev,unsigned int flags)616 static bool mlx5_perout_verify_flags(struct mlx5_core_dev *mdev, unsigned int flags)
617 {
618 	return ((!mlx5_npps_real_time_supported(mdev) && flags) ||
619 		(mlx5_npps_real_time_supported(mdev) && flags & ~PTP_PEROUT_DUTY_CYCLE));
620 }
621 
mlx5_perout_configure(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)622 static int mlx5_perout_configure(struct ptp_clock_info *ptp,
623 				 struct ptp_clock_request *rq,
624 				 int on)
625 {
626 	struct mlx5_clock *clock =
627 			container_of(ptp, struct mlx5_clock, ptp_info);
628 	struct mlx5_core_dev *mdev =
629 			container_of(clock, struct mlx5_core_dev, clock);
630 	bool rt_mode = mlx5_real_time_mode(mdev);
631 	u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
632 	u32 out_pulse_duration_ns = 0;
633 	u32 field_select = 0;
634 	u64 npps_period = 0;
635 	u64 time_stamp = 0;
636 	u8 pin_mode = 0;
637 	u8 pattern = 0;
638 	int pin = -1;
639 	int err = 0;
640 
641 	if (!MLX5_PPS_CAP(mdev))
642 		return -EOPNOTSUPP;
643 
644 	/* Reject requests with unsupported flags */
645 	if (mlx5_perout_verify_flags(mdev, rq->perout.flags))
646 		return -EOPNOTSUPP;
647 
648 	if (rq->perout.index >= clock->ptp_info.n_pins)
649 		return -EINVAL;
650 
651 	field_select = MLX5_MTPPS_FS_ENABLE;
652 	pin = ptp_find_pin(clock->ptp, PTP_PF_PEROUT, rq->perout.index);
653 	if (pin < 0)
654 		return -EBUSY;
655 
656 	if (on) {
657 		bool rt_mode = mlx5_real_time_mode(mdev);
658 
659 		pin_mode = MLX5_PIN_MODE_OUT;
660 		pattern = MLX5_OUT_PATTERN_PERIODIC;
661 
662 		if (rt_mode &&  rq->perout.start.sec > U32_MAX)
663 			return -EINVAL;
664 
665 		field_select |= MLX5_MTPPS_FS_PIN_MODE |
666 				MLX5_MTPPS_FS_PATTERN |
667 				MLX5_MTPPS_FS_TIME_STAMP;
668 
669 		if (mlx5_npps_real_time_supported(mdev))
670 			err = perout_conf_npps_real_time(mdev, rq, &field_select,
671 							 &out_pulse_duration_ns, &npps_period,
672 							 &time_stamp);
673 		else
674 			err = perout_conf_1pps(mdev, rq, &time_stamp, rt_mode);
675 		if (err)
676 			return err;
677 	}
678 
679 	MLX5_SET(mtpps_reg, in, pin, pin);
680 	MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
681 	MLX5_SET(mtpps_reg, in, pattern, pattern);
682 	MLX5_SET(mtpps_reg, in, enable, on);
683 	MLX5_SET64(mtpps_reg, in, time_stamp, time_stamp);
684 	MLX5_SET(mtpps_reg, in, field_select, field_select);
685 	MLX5_SET64(mtpps_reg, in, npps_period, npps_period);
686 	MLX5_SET(mtpps_reg, in, out_pulse_duration_ns, out_pulse_duration_ns);
687 	err = mlx5_set_mtpps(mdev, in, sizeof(in));
688 	if (err)
689 		return err;
690 
691 	if (rt_mode)
692 		return 0;
693 
694 	return mlx5_set_mtppse(mdev, pin, 0,
695 			       MLX5_EVENT_MODE_REPETETIVE & on);
696 }
697 
mlx5_pps_configure(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)698 static int mlx5_pps_configure(struct ptp_clock_info *ptp,
699 			      struct ptp_clock_request *rq,
700 			      int on)
701 {
702 	struct mlx5_clock *clock =
703 			container_of(ptp, struct mlx5_clock, ptp_info);
704 
705 	clock->pps_info.enabled = !!on;
706 	return 0;
707 }
708 
mlx5_ptp_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)709 static int mlx5_ptp_enable(struct ptp_clock_info *ptp,
710 			   struct ptp_clock_request *rq,
711 			   int on)
712 {
713 	switch (rq->type) {
714 	case PTP_CLK_REQ_EXTTS:
715 		return mlx5_extts_configure(ptp, rq, on);
716 	case PTP_CLK_REQ_PEROUT:
717 		return mlx5_perout_configure(ptp, rq, on);
718 	case PTP_CLK_REQ_PPS:
719 		return mlx5_pps_configure(ptp, rq, on);
720 	default:
721 		return -EOPNOTSUPP;
722 	}
723 	return 0;
724 }
725 
726 enum {
727 	MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN = BIT(0),
728 	MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT = BIT(1),
729 };
730 
mlx5_ptp_verify(struct ptp_clock_info * ptp,unsigned int pin,enum ptp_pin_function func,unsigned int chan)731 static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
732 			   enum ptp_pin_function func, unsigned int chan)
733 {
734 	struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock,
735 						ptp_info);
736 
737 	switch (func) {
738 	case PTP_PF_NONE:
739 		return 0;
740 	case PTP_PF_EXTTS:
741 		return !(clock->pps_info.pin_caps[pin] &
742 			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN);
743 	case PTP_PF_PEROUT:
744 		return !(clock->pps_info.pin_caps[pin] &
745 			 MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT);
746 	default:
747 		return -EOPNOTSUPP;
748 	}
749 }
750 
751 static const struct ptp_clock_info mlx5_ptp_clock_info = {
752 	.owner		= THIS_MODULE,
753 	.name		= "mlx5_ptp",
754 	.max_adj	= 50000000,
755 	.n_alarm	= 0,
756 	.n_ext_ts	= 0,
757 	.n_per_out	= 0,
758 	.n_pins		= 0,
759 	.pps		= 0,
760 	.adjfine	= mlx5_ptp_adjfine,
761 	.adjphase	= mlx5_ptp_adjphase,
762 	.getmaxphase    = mlx5_ptp_getmaxphase,
763 	.adjtime	= mlx5_ptp_adjtime,
764 	.gettimex64	= mlx5_ptp_gettimex,
765 	.settime64	= mlx5_ptp_settime,
766 	.enable		= NULL,
767 	.verify		= NULL,
768 };
769 
mlx5_query_mtpps_pin_mode(struct mlx5_core_dev * mdev,u8 pin,u32 * mtpps,u32 mtpps_size)770 static int mlx5_query_mtpps_pin_mode(struct mlx5_core_dev *mdev, u8 pin,
771 				     u32 *mtpps, u32 mtpps_size)
772 {
773 	u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {};
774 
775 	MLX5_SET(mtpps_reg, in, pin, pin);
776 
777 	return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
778 				    mtpps_size, MLX5_REG_MTPPS, 0, 0);
779 }
780 
mlx5_get_pps_pin_mode(struct mlx5_clock * clock,u8 pin)781 static int mlx5_get_pps_pin_mode(struct mlx5_clock *clock, u8 pin)
782 {
783 	struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock);
784 
785 	u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {};
786 	u8 mode;
787 	int err;
788 
789 	err = mlx5_query_mtpps_pin_mode(mdev, pin, out, sizeof(out));
790 	if (err || !MLX5_GET(mtpps_reg, out, enable))
791 		return PTP_PF_NONE;
792 
793 	mode = MLX5_GET(mtpps_reg, out, pin_mode);
794 
795 	if (mode == MLX5_PIN_MODE_IN)
796 		return PTP_PF_EXTTS;
797 	else if (mode == MLX5_PIN_MODE_OUT)
798 		return PTP_PF_PEROUT;
799 
800 	return PTP_PF_NONE;
801 }
802 
mlx5_init_pin_config(struct mlx5_clock * clock)803 static void mlx5_init_pin_config(struct mlx5_clock *clock)
804 {
805 	int i;
806 
807 	if (!clock->ptp_info.n_pins)
808 		return;
809 
810 	clock->ptp_info.pin_config =
811 			kcalloc(clock->ptp_info.n_pins,
812 				sizeof(*clock->ptp_info.pin_config),
813 				GFP_KERNEL);
814 	if (!clock->ptp_info.pin_config)
815 		return;
816 	clock->ptp_info.enable = mlx5_ptp_enable;
817 	clock->ptp_info.verify = mlx5_ptp_verify;
818 	clock->ptp_info.pps = 1;
819 
820 	for (i = 0; i < clock->ptp_info.n_pins; i++) {
821 		snprintf(clock->ptp_info.pin_config[i].name,
822 			 sizeof(clock->ptp_info.pin_config[i].name),
823 			 "mlx5_pps%d", i);
824 		clock->ptp_info.pin_config[i].index = i;
825 		clock->ptp_info.pin_config[i].func = mlx5_get_pps_pin_mode(clock, i);
826 		clock->ptp_info.pin_config[i].chan = 0;
827 	}
828 }
829 
mlx5_get_pps_caps(struct mlx5_core_dev * mdev)830 static void mlx5_get_pps_caps(struct mlx5_core_dev *mdev)
831 {
832 	struct mlx5_clock *clock = &mdev->clock;
833 	u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
834 
835 	mlx5_query_mtpps(mdev, out, sizeof(out));
836 
837 	clock->ptp_info.n_pins = MLX5_GET(mtpps_reg, out,
838 					  cap_number_of_pps_pins);
839 	clock->ptp_info.n_ext_ts = MLX5_GET(mtpps_reg, out,
840 					    cap_max_num_of_pps_in_pins);
841 	clock->ptp_info.n_per_out = MLX5_GET(mtpps_reg, out,
842 					     cap_max_num_of_pps_out_pins);
843 
844 	if (MLX5_CAP_MCAM_FEATURE(mdev, npps_period))
845 		clock->pps_info.min_npps_period = 1 << MLX5_GET(mtpps_reg, out,
846 								cap_log_min_npps_period);
847 	if (MLX5_CAP_MCAM_FEATURE(mdev, out_pulse_duration_ns))
848 		clock->pps_info.min_out_pulse_duration_ns = 1 << MLX5_GET(mtpps_reg, out,
849 								cap_log_min_out_pulse_duration_ns);
850 
851 	clock->pps_info.pin_caps[0] = MLX5_GET(mtpps_reg, out, cap_pin_0_mode);
852 	clock->pps_info.pin_caps[1] = MLX5_GET(mtpps_reg, out, cap_pin_1_mode);
853 	clock->pps_info.pin_caps[2] = MLX5_GET(mtpps_reg, out, cap_pin_2_mode);
854 	clock->pps_info.pin_caps[3] = MLX5_GET(mtpps_reg, out, cap_pin_3_mode);
855 	clock->pps_info.pin_caps[4] = MLX5_GET(mtpps_reg, out, cap_pin_4_mode);
856 	clock->pps_info.pin_caps[5] = MLX5_GET(mtpps_reg, out, cap_pin_5_mode);
857 	clock->pps_info.pin_caps[6] = MLX5_GET(mtpps_reg, out, cap_pin_6_mode);
858 	clock->pps_info.pin_caps[7] = MLX5_GET(mtpps_reg, out, cap_pin_7_mode);
859 }
860 
ts_next_sec(struct timespec64 * ts)861 static void ts_next_sec(struct timespec64 *ts)
862 {
863 	ts->tv_sec += 1;
864 	ts->tv_nsec = 0;
865 }
866 
perout_conf_next_event_timer(struct mlx5_core_dev * mdev,struct mlx5_clock * clock)867 static u64 perout_conf_next_event_timer(struct mlx5_core_dev *mdev,
868 					struct mlx5_clock *clock)
869 {
870 	struct timespec64 ts;
871 	s64 target_ns;
872 
873 	mlx5_ptp_gettimex(&clock->ptp_info, &ts, NULL);
874 	ts_next_sec(&ts);
875 	target_ns = timespec64_to_ns(&ts);
876 
877 	return find_target_cycles(mdev, target_ns);
878 }
879 
mlx5_pps_event(struct notifier_block * nb,unsigned long type,void * data)880 static int mlx5_pps_event(struct notifier_block *nb,
881 			  unsigned long type, void *data)
882 {
883 	struct mlx5_clock *clock = mlx5_nb_cof(nb, struct mlx5_clock, pps_nb);
884 	struct ptp_clock_event ptp_event;
885 	struct mlx5_eqe *eqe = data;
886 	int pin = eqe->data.pps.pin;
887 	struct mlx5_core_dev *mdev;
888 	unsigned long flags;
889 	u64 ns;
890 
891 	mdev = container_of(clock, struct mlx5_core_dev, clock);
892 
893 	switch (clock->ptp_info.pin_config[pin].func) {
894 	case PTP_PF_EXTTS:
895 		ptp_event.index = pin;
896 		ptp_event.timestamp = mlx5_real_time_mode(mdev) ?
897 			mlx5_real_time_cyc2time(clock,
898 						be64_to_cpu(eqe->data.pps.time_stamp)) :
899 			mlx5_timecounter_cyc2time(clock,
900 						  be64_to_cpu(eqe->data.pps.time_stamp));
901 		if (clock->pps_info.enabled) {
902 			ptp_event.type = PTP_CLOCK_PPSUSR;
903 			ptp_event.pps_times.ts_real =
904 					ns_to_timespec64(ptp_event.timestamp);
905 		} else {
906 			ptp_event.type = PTP_CLOCK_EXTTS;
907 		}
908 		/* TODOL clock->ptp can be NULL if ptp_clock_register fails */
909 		ptp_clock_event(clock->ptp, &ptp_event);
910 		break;
911 	case PTP_PF_PEROUT:
912 		ns = perout_conf_next_event_timer(mdev, clock);
913 		write_seqlock_irqsave(&clock->lock, flags);
914 		clock->pps_info.start[pin] = ns;
915 		write_sequnlock_irqrestore(&clock->lock, flags);
916 		schedule_work(&clock->pps_info.out_work);
917 		break;
918 	default:
919 		mlx5_core_err(mdev, " Unhandled clock PPS event, func %d\n",
920 			      clock->ptp_info.pin_config[pin].func);
921 	}
922 
923 	return NOTIFY_OK;
924 }
925 
mlx5_timecounter_init(struct mlx5_core_dev * mdev)926 static void mlx5_timecounter_init(struct mlx5_core_dev *mdev)
927 {
928 	struct mlx5_clock *clock = &mdev->clock;
929 	struct mlx5_timer *timer = &clock->timer;
930 	u32 dev_freq;
931 
932 	dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz);
933 	timer->cycles.read = read_internal_timer;
934 	timer->cycles.shift = mlx5_ptp_shift_constant(dev_freq);
935 	timer->cycles.mult = clocksource_khz2mult(dev_freq,
936 						  timer->cycles.shift);
937 	timer->nominal_c_mult = timer->cycles.mult;
938 	timer->cycles.mask = CLOCKSOURCE_MASK(41);
939 
940 	timecounter_init(&timer->tc, &timer->cycles,
941 			 ktime_to_ns(ktime_get_real()));
942 }
943 
mlx5_init_overflow_period(struct mlx5_clock * clock)944 static void mlx5_init_overflow_period(struct mlx5_clock *clock)
945 {
946 	struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock);
947 	struct mlx5_ib_clock_info *clock_info = mdev->clock_info;
948 	struct mlx5_timer *timer = &clock->timer;
949 	u64 overflow_cycles;
950 	u64 frac = 0;
951 	u64 ns;
952 
953 	/* Calculate period in seconds to call the overflow watchdog - to make
954 	 * sure counter is checked at least twice every wrap around.
955 	 * The period is calculated as the minimum between max HW cycles count
956 	 * (The clock source mask) and max amount of cycles that can be
957 	 * multiplied by clock multiplier where the result doesn't exceed
958 	 * 64bits.
959 	 */
960 	overflow_cycles = div64_u64(~0ULL >> 1, timer->cycles.mult);
961 	overflow_cycles = min(overflow_cycles, div_u64(timer->cycles.mask, 3));
962 
963 	ns = cyclecounter_cyc2ns(&timer->cycles, overflow_cycles,
964 				 frac, &frac);
965 	do_div(ns, NSEC_PER_SEC / HZ);
966 	timer->overflow_period = ns;
967 
968 	INIT_DELAYED_WORK(&timer->overflow_work, mlx5_timestamp_overflow);
969 	if (timer->overflow_period)
970 		schedule_delayed_work(&timer->overflow_work, 0);
971 	else
972 		mlx5_core_warn(mdev,
973 			       "invalid overflow period, overflow_work is not scheduled\n");
974 
975 	if (clock_info)
976 		clock_info->overflow_period = timer->overflow_period;
977 }
978 
mlx5_init_clock_info(struct mlx5_core_dev * mdev)979 static void mlx5_init_clock_info(struct mlx5_core_dev *mdev)
980 {
981 	struct mlx5_clock *clock = &mdev->clock;
982 	struct mlx5_ib_clock_info *info;
983 	struct mlx5_timer *timer;
984 
985 	mdev->clock_info = (struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL);
986 	if (!mdev->clock_info) {
987 		mlx5_core_warn(mdev, "Failed to allocate IB clock info page\n");
988 		return;
989 	}
990 
991 	info = mdev->clock_info;
992 	timer = &clock->timer;
993 
994 	info->nsec = timer->tc.nsec;
995 	info->cycles = timer->tc.cycle_last;
996 	info->mask = timer->cycles.mask;
997 	info->mult = timer->nominal_c_mult;
998 	info->shift = timer->cycles.shift;
999 	info->frac = timer->tc.frac;
1000 }
1001 
mlx5_init_timer_clock(struct mlx5_core_dev * mdev)1002 static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev)
1003 {
1004 	struct mlx5_clock *clock = &mdev->clock;
1005 
1006 	mlx5_timecounter_init(mdev);
1007 	mlx5_init_clock_info(mdev);
1008 	mlx5_init_overflow_period(clock);
1009 	clock->ptp_info = mlx5_ptp_clock_info;
1010 
1011 	if (mlx5_real_time_mode(mdev)) {
1012 		struct timespec64 ts;
1013 
1014 		ktime_get_real_ts64(&ts);
1015 		mlx5_ptp_settime(&clock->ptp_info, &ts);
1016 	}
1017 }
1018 
mlx5_init_pps(struct mlx5_core_dev * mdev)1019 static void mlx5_init_pps(struct mlx5_core_dev *mdev)
1020 {
1021 	struct mlx5_clock *clock = &mdev->clock;
1022 
1023 	if (!MLX5_PPS_CAP(mdev))
1024 		return;
1025 
1026 	mlx5_get_pps_caps(mdev);
1027 	mlx5_init_pin_config(clock);
1028 }
1029 
mlx5_init_clock(struct mlx5_core_dev * mdev)1030 void mlx5_init_clock(struct mlx5_core_dev *mdev)
1031 {
1032 	struct mlx5_clock *clock = &mdev->clock;
1033 
1034 	if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) {
1035 		mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n");
1036 		return;
1037 	}
1038 
1039 	seqlock_init(&clock->lock);
1040 	mlx5_init_timer_clock(mdev);
1041 	INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out);
1042 
1043 	/* Configure the PHC */
1044 	clock->ptp_info = mlx5_ptp_clock_info;
1045 
1046 	/* Initialize 1PPS data structures */
1047 	mlx5_init_pps(mdev);
1048 
1049 	clock->ptp = ptp_clock_register(&clock->ptp_info,
1050 					&mdev->pdev->dev);
1051 	if (IS_ERR(clock->ptp)) {
1052 		mlx5_core_warn(mdev, "ptp_clock_register failed %ld\n",
1053 			       PTR_ERR(clock->ptp));
1054 		clock->ptp = NULL;
1055 	}
1056 
1057 	MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT);
1058 	mlx5_eq_notifier_register(mdev, &clock->pps_nb);
1059 }
1060 
mlx5_cleanup_clock(struct mlx5_core_dev * mdev)1061 void mlx5_cleanup_clock(struct mlx5_core_dev *mdev)
1062 {
1063 	struct mlx5_clock *clock = &mdev->clock;
1064 
1065 	if (!MLX5_CAP_GEN(mdev, device_frequency_khz))
1066 		return;
1067 
1068 	mlx5_eq_notifier_unregister(mdev, &clock->pps_nb);
1069 	if (clock->ptp) {
1070 		ptp_clock_unregister(clock->ptp);
1071 		clock->ptp = NULL;
1072 	}
1073 
1074 	cancel_work_sync(&clock->pps_info.out_work);
1075 	cancel_delayed_work_sync(&clock->timer.overflow_work);
1076 
1077 	if (mdev->clock_info) {
1078 		free_page((unsigned long)mdev->clock_info);
1079 		mdev->clock_info = NULL;
1080 	}
1081 
1082 	kfree(clock->ptp_info.pin_config);
1083 }
1084