1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27 
28 #define SMU_13_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30 
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v13_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41 
42 #include "asic_reg/thm/thm_13_0_2_offset.h"
43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_13_0_2_offset.h"
45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
48 
49 /*
50  * DO NOT use these for err/warn/info/debug messages.
51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52  * They are more MGPU friendly.
53  */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58 
59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
63 
64 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
66 
67 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
69 
70 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
72 
73 #define SMU13_VOLTAGE_SCALE 4
74 
75 #define LINK_WIDTH_MAX				6
76 #define LINK_SPEED_MAX				3
77 
78 #define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
81 #define smnPCIE_LC_SPEED_CNTL			0x11140290
82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
84 
85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
86 
87 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
88 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
89 
smu_v13_0_init_microcode(struct smu_context * smu)90 int smu_v13_0_init_microcode(struct smu_context *smu)
91 {
92 	struct amdgpu_device *adev = smu->adev;
93 	char fw_name[30];
94 	char ucode_prefix[30];
95 	int err = 0;
96 	const struct smc_firmware_header_v1_0 *hdr;
97 	const struct common_firmware_header *header;
98 	struct amdgpu_firmware_info *ucode = NULL;
99 
100 	/* doesn't need to load smu firmware in IOV mode */
101 	if (amdgpu_sriov_vf(adev))
102 		return 0;
103 
104 	amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
105 
106 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
107 
108 	err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
109 	if (err)
110 		goto out;
111 
112 	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
113 	amdgpu_ucode_print_smc_hdr(&hdr->header);
114 	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
115 
116 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
117 		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
118 		ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
119 		ucode->fw = adev->pm.fw;
120 		header = (const struct common_firmware_header *)ucode->fw->data;
121 		adev->firmware.fw_size +=
122 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
123 	}
124 
125 out:
126 	if (err)
127 		amdgpu_ucode_release(&adev->pm.fw);
128 	return err;
129 }
130 
smu_v13_0_fini_microcode(struct smu_context * smu)131 void smu_v13_0_fini_microcode(struct smu_context *smu)
132 {
133 	struct amdgpu_device *adev = smu->adev;
134 
135 	amdgpu_ucode_release(&adev->pm.fw);
136 	adev->pm.fw_version = 0;
137 }
138 
smu_v13_0_load_microcode(struct smu_context * smu)139 int smu_v13_0_load_microcode(struct smu_context *smu)
140 {
141 #if 0
142 	struct amdgpu_device *adev = smu->adev;
143 	const uint32_t *src;
144 	const struct smc_firmware_header_v1_0 *hdr;
145 	uint32_t addr_start = MP1_SRAM;
146 	uint32_t i;
147 	uint32_t smc_fw_size;
148 	uint32_t mp1_fw_flags;
149 
150 	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
151 	src = (const uint32_t *)(adev->pm.fw->data +
152 				 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
153 	smc_fw_size = hdr->header.ucode_size_bytes;
154 
155 	for (i = 1; i < smc_fw_size/4 - 1; i++) {
156 		WREG32_PCIE(addr_start, src[i]);
157 		addr_start += 4;
158 	}
159 
160 	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
161 		    1 & MP1_SMN_PUB_CTRL__RESET_MASK);
162 	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
163 		    1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
164 
165 	for (i = 0; i < adev->usec_timeout; i++) {
166 		mp1_fw_flags = RREG32_PCIE(MP1_Public |
167 					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
168 		if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
169 		    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
170 			break;
171 		udelay(1);
172 	}
173 
174 	if (i == adev->usec_timeout)
175 		return -ETIME;
176 #endif
177 
178 	return 0;
179 }
180 
smu_v13_0_init_pptable_microcode(struct smu_context * smu)181 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
182 {
183 	struct amdgpu_device *adev = smu->adev;
184 	struct amdgpu_firmware_info *ucode = NULL;
185 	uint32_t size = 0, pptable_id = 0;
186 	int ret = 0;
187 	void *table;
188 
189 	/* doesn't need to load smu firmware in IOV mode */
190 	if (amdgpu_sriov_vf(adev))
191 		return 0;
192 
193 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
194 		return 0;
195 
196 	if (!adev->scpm_enabled)
197 		return 0;
198 
199 	if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) ||
200 	    (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) ||
201 	    (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)))
202 		return 0;
203 
204 	/* override pptable_id from driver parameter */
205 	if (amdgpu_smu_pptable_id >= 0) {
206 		pptable_id = amdgpu_smu_pptable_id;
207 		dev_info(adev->dev, "override pptable id %d\n", pptable_id);
208 	} else {
209 		pptable_id = smu->smu_table.boot_values.pp_table_id;
210 	}
211 
212 	/* "pptable_id == 0" means vbios carries the pptable. */
213 	if (!pptable_id)
214 		return 0;
215 
216 	ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
217 	if (ret)
218 		return ret;
219 
220 	smu->pptable_firmware.data = table;
221 	smu->pptable_firmware.size = size;
222 
223 	ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
224 	ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
225 	ucode->fw = &smu->pptable_firmware;
226 	adev->firmware.fw_size +=
227 		ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
228 
229 	return 0;
230 }
231 
smu_v13_0_check_fw_status(struct smu_context * smu)232 int smu_v13_0_check_fw_status(struct smu_context *smu)
233 {
234 	struct amdgpu_device *adev = smu->adev;
235 	uint32_t mp1_fw_flags;
236 
237 	switch (adev->ip_versions[MP1_HWIP][0]) {
238 	case IP_VERSION(13, 0, 4):
239 	case IP_VERSION(13, 0, 11):
240 		mp1_fw_flags = RREG32_PCIE(MP1_Public |
241 					   (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
242 		break;
243 	default:
244 		mp1_fw_flags = RREG32_PCIE(MP1_Public |
245 					   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
246 		break;
247 	}
248 
249 	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
250 	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
251 		return 0;
252 
253 	return -EIO;
254 }
255 
smu_v13_0_check_fw_version(struct smu_context * smu)256 int smu_v13_0_check_fw_version(struct smu_context *smu)
257 {
258 	struct amdgpu_device *adev = smu->adev;
259 	uint32_t if_version = 0xff, smu_version = 0xff;
260 	uint8_t smu_program, smu_major, smu_minor, smu_debug;
261 	int ret = 0;
262 
263 	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
264 	if (ret)
265 		return ret;
266 
267 	smu_program = (smu_version >> 24) & 0xff;
268 	smu_major = (smu_version >> 16) & 0xff;
269 	smu_minor = (smu_version >> 8) & 0xff;
270 	smu_debug = (smu_version >> 0) & 0xff;
271 	if (smu->is_apu ||
272 	    adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 6))
273 		adev->pm.fw_version = smu_version;
274 
275 	/* only for dGPU w/ SMU13*/
276 	if (adev->pm.fw)
277 		dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
278 			 smu_program, smu_version, smu_major, smu_minor, smu_debug);
279 
280 	/*
281 	 * 1. if_version mismatch is not critical as our fw is designed
282 	 * to be backward compatible.
283 	 * 2. New fw usually brings some optimizations. But that's visible
284 	 * only on the paired driver.
285 	 * Considering above, we just leave user a verbal message instead
286 	 * of halt driver loading.
287 	 */
288 	if (if_version != smu->smc_driver_if_version) {
289 		dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
290 			 "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
291 			 smu->smc_driver_if_version, if_version,
292 			 smu_program, smu_version, smu_major, smu_minor, smu_debug);
293 		dev_info(adev->dev, "SMU driver if version not matched\n");
294 	}
295 
296 	return ret;
297 }
298 
smu_v13_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)299 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
300 {
301 	struct amdgpu_device *adev = smu->adev;
302 	uint32_t ppt_offset_bytes;
303 	const struct smc_firmware_header_v2_0 *v2;
304 
305 	v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
306 
307 	ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
308 	*size = le32_to_cpu(v2->ppt_size_bytes);
309 	*table = (uint8_t *)v2 + ppt_offset_bytes;
310 
311 	return 0;
312 }
313 
smu_v13_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)314 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
315 				      uint32_t *size, uint32_t pptable_id)
316 {
317 	struct amdgpu_device *adev = smu->adev;
318 	const struct smc_firmware_header_v2_1 *v2_1;
319 	struct smc_soft_pptable_entry *entries;
320 	uint32_t pptable_count = 0;
321 	int i = 0;
322 
323 	v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
324 	entries = (struct smc_soft_pptable_entry *)
325 		((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
326 	pptable_count = le32_to_cpu(v2_1->pptable_count);
327 	for (i = 0; i < pptable_count; i++) {
328 		if (le32_to_cpu(entries[i].id) == pptable_id) {
329 			*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
330 			*size = le32_to_cpu(entries[i].ppt_size_bytes);
331 			break;
332 		}
333 	}
334 
335 	if (i == pptable_count)
336 		return -EINVAL;
337 
338 	return 0;
339 }
340 
smu_v13_0_get_pptable_from_vbios(struct smu_context * smu,void ** table,uint32_t * size)341 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
342 {
343 	struct amdgpu_device *adev = smu->adev;
344 	uint16_t atom_table_size;
345 	uint8_t frev, crev;
346 	int ret, index;
347 
348 	dev_info(adev->dev, "use vbios provided pptable\n");
349 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
350 					    powerplayinfo);
351 
352 	ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
353 					     (uint8_t **)table);
354 	if (ret)
355 		return ret;
356 
357 	if (size)
358 		*size = atom_table_size;
359 
360 	return 0;
361 }
362 
smu_v13_0_get_pptable_from_firmware(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)363 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
364 					void **table,
365 					uint32_t *size,
366 					uint32_t pptable_id)
367 {
368 	const struct smc_firmware_header_v1_0 *hdr;
369 	struct amdgpu_device *adev = smu->adev;
370 	uint16_t version_major, version_minor;
371 	int ret;
372 
373 	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
374 	if (!hdr)
375 		return -EINVAL;
376 
377 	dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
378 
379 	version_major = le16_to_cpu(hdr->header.header_version_major);
380 	version_minor = le16_to_cpu(hdr->header.header_version_minor);
381 	if (version_major != 2) {
382 		dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
383 			version_major, version_minor);
384 		return -EINVAL;
385 	}
386 
387 	switch (version_minor) {
388 	case 0:
389 		ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
390 		break;
391 	case 1:
392 		ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
393 		break;
394 	default:
395 		ret = -EINVAL;
396 		break;
397 	}
398 
399 	return ret;
400 }
401 
smu_v13_0_setup_pptable(struct smu_context * smu)402 int smu_v13_0_setup_pptable(struct smu_context *smu)
403 {
404 	struct amdgpu_device *adev = smu->adev;
405 	uint32_t size = 0, pptable_id = 0;
406 	void *table;
407 	int ret = 0;
408 
409 	/* override pptable_id from driver parameter */
410 	if (amdgpu_smu_pptable_id >= 0) {
411 		pptable_id = amdgpu_smu_pptable_id;
412 		dev_info(adev->dev, "override pptable id %d\n", pptable_id);
413 	} else {
414 		pptable_id = smu->smu_table.boot_values.pp_table_id;
415 	}
416 
417 	/* force using vbios pptable in sriov mode */
418 	if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
419 		ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
420 	else
421 		ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
422 
423 	if (ret)
424 		return ret;
425 
426 	if (!smu->smu_table.power_play_table)
427 		smu->smu_table.power_play_table = table;
428 	if (!smu->smu_table.power_play_table_size)
429 		smu->smu_table.power_play_table_size = size;
430 
431 	return 0;
432 }
433 
smu_v13_0_init_smc_tables(struct smu_context * smu)434 int smu_v13_0_init_smc_tables(struct smu_context *smu)
435 {
436 	struct smu_table_context *smu_table = &smu->smu_table;
437 	struct smu_table *tables = smu_table->tables;
438 	int ret = 0;
439 
440 	smu_table->driver_pptable =
441 		kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
442 	if (!smu_table->driver_pptable) {
443 		ret = -ENOMEM;
444 		goto err0_out;
445 	}
446 
447 	smu_table->max_sustainable_clocks =
448 		kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
449 	if (!smu_table->max_sustainable_clocks) {
450 		ret = -ENOMEM;
451 		goto err1_out;
452 	}
453 
454 	/* Aldebaran does not support OVERDRIVE */
455 	if (tables[SMU_TABLE_OVERDRIVE].size) {
456 		smu_table->overdrive_table =
457 			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
458 		if (!smu_table->overdrive_table) {
459 			ret = -ENOMEM;
460 			goto err2_out;
461 		}
462 
463 		smu_table->boot_overdrive_table =
464 			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
465 		if (!smu_table->boot_overdrive_table) {
466 			ret = -ENOMEM;
467 			goto err3_out;
468 		}
469 
470 		smu_table->user_overdrive_table =
471 			kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
472 		if (!smu_table->user_overdrive_table) {
473 			ret = -ENOMEM;
474 			goto err4_out;
475 		}
476 	}
477 
478 	smu_table->combo_pptable =
479 		kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
480 	if (!smu_table->combo_pptable) {
481 		ret = -ENOMEM;
482 		goto err5_out;
483 	}
484 
485 	return 0;
486 
487 err5_out:
488 	kfree(smu_table->user_overdrive_table);
489 err4_out:
490 	kfree(smu_table->boot_overdrive_table);
491 err3_out:
492 	kfree(smu_table->overdrive_table);
493 err2_out:
494 	kfree(smu_table->max_sustainable_clocks);
495 err1_out:
496 	kfree(smu_table->driver_pptable);
497 err0_out:
498 	return ret;
499 }
500 
smu_v13_0_fini_smc_tables(struct smu_context * smu)501 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
502 {
503 	struct smu_table_context *smu_table = &smu->smu_table;
504 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
505 
506 	kfree(smu_table->gpu_metrics_table);
507 	kfree(smu_table->combo_pptable);
508 	kfree(smu_table->user_overdrive_table);
509 	kfree(smu_table->boot_overdrive_table);
510 	kfree(smu_table->overdrive_table);
511 	kfree(smu_table->max_sustainable_clocks);
512 	kfree(smu_table->driver_pptable);
513 	smu_table->gpu_metrics_table = NULL;
514 	smu_table->combo_pptable = NULL;
515 	smu_table->user_overdrive_table = NULL;
516 	smu_table->boot_overdrive_table = NULL;
517 	smu_table->overdrive_table = NULL;
518 	smu_table->max_sustainable_clocks = NULL;
519 	smu_table->driver_pptable = NULL;
520 	kfree(smu_table->hardcode_pptable);
521 	smu_table->hardcode_pptable = NULL;
522 
523 	kfree(smu_table->ecc_table);
524 	kfree(smu_table->metrics_table);
525 	kfree(smu_table->watermarks_table);
526 	smu_table->ecc_table = NULL;
527 	smu_table->metrics_table = NULL;
528 	smu_table->watermarks_table = NULL;
529 	smu_table->metrics_time = 0;
530 
531 	kfree(smu_dpm->dpm_context);
532 	kfree(smu_dpm->golden_dpm_context);
533 	kfree(smu_dpm->dpm_current_power_state);
534 	kfree(smu_dpm->dpm_request_power_state);
535 	smu_dpm->dpm_context = NULL;
536 	smu_dpm->golden_dpm_context = NULL;
537 	smu_dpm->dpm_context_size = 0;
538 	smu_dpm->dpm_current_power_state = NULL;
539 	smu_dpm->dpm_request_power_state = NULL;
540 
541 	return 0;
542 }
543 
smu_v13_0_init_power(struct smu_context * smu)544 int smu_v13_0_init_power(struct smu_context *smu)
545 {
546 	struct smu_power_context *smu_power = &smu->smu_power;
547 
548 	if (smu_power->power_context || smu_power->power_context_size != 0)
549 		return -EINVAL;
550 
551 	smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
552 					   GFP_KERNEL);
553 	if (!smu_power->power_context)
554 		return -ENOMEM;
555 	smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
556 
557 	return 0;
558 }
559 
smu_v13_0_fini_power(struct smu_context * smu)560 int smu_v13_0_fini_power(struct smu_context *smu)
561 {
562 	struct smu_power_context *smu_power = &smu->smu_power;
563 
564 	if (!smu_power->power_context || smu_power->power_context_size == 0)
565 		return -EINVAL;
566 
567 	kfree(smu_power->power_context);
568 	smu_power->power_context = NULL;
569 	smu_power->power_context_size = 0;
570 
571 	return 0;
572 }
573 
smu_v13_0_get_vbios_bootup_values(struct smu_context * smu)574 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
575 {
576 	int ret, index;
577 	uint16_t size;
578 	uint8_t frev, crev;
579 	struct atom_common_table_header *header;
580 	struct atom_firmware_info_v3_4 *v_3_4;
581 	struct atom_firmware_info_v3_3 *v_3_3;
582 	struct atom_firmware_info_v3_1 *v_3_1;
583 	struct atom_smu_info_v3_6 *smu_info_v3_6;
584 	struct atom_smu_info_v4_0 *smu_info_v4_0;
585 
586 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
587 					    firmwareinfo);
588 
589 	ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
590 					     (uint8_t **)&header);
591 	if (ret)
592 		return ret;
593 
594 	if (header->format_revision != 3) {
595 		dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
596 		return -EINVAL;
597 	}
598 
599 	switch (header->content_revision) {
600 	case 0:
601 	case 1:
602 	case 2:
603 		v_3_1 = (struct atom_firmware_info_v3_1 *)header;
604 		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
605 		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
606 		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
607 		smu->smu_table.boot_values.socclk = 0;
608 		smu->smu_table.boot_values.dcefclk = 0;
609 		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
610 		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
611 		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
612 		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
613 		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
614 		smu->smu_table.boot_values.pp_table_id = 0;
615 		break;
616 	case 3:
617 		v_3_3 = (struct atom_firmware_info_v3_3 *)header;
618 		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
619 		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
620 		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
621 		smu->smu_table.boot_values.socclk = 0;
622 		smu->smu_table.boot_values.dcefclk = 0;
623 		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
624 		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
625 		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
626 		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
627 		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
628 		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
629 		break;
630 	case 4:
631 	default:
632 		v_3_4 = (struct atom_firmware_info_v3_4 *)header;
633 		smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
634 		smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
635 		smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
636 		smu->smu_table.boot_values.socclk = 0;
637 		smu->smu_table.boot_values.dcefclk = 0;
638 		smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
639 		smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
640 		smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
641 		smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
642 		smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
643 		smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
644 		break;
645 	}
646 
647 	smu->smu_table.boot_values.format_revision = header->format_revision;
648 	smu->smu_table.boot_values.content_revision = header->content_revision;
649 
650 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
651 					    smu_info);
652 	if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
653 					    (uint8_t **)&header)) {
654 
655 		if ((frev == 3) && (crev == 6)) {
656 			smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
657 
658 			smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
659 			smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
660 			smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
661 			smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
662 		} else if ((frev == 3) && (crev == 1)) {
663 			return 0;
664 		} else if ((frev == 4) && (crev == 0)) {
665 			smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
666 
667 			smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
668 			smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
669 			smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
670 			smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
671 			smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
672 		} else {
673 			dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
674 						(uint32_t)frev, (uint32_t)crev);
675 		}
676 	}
677 
678 	return 0;
679 }
680 
681 
smu_v13_0_notify_memory_pool_location(struct smu_context * smu)682 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
683 {
684 	struct smu_table_context *smu_table = &smu->smu_table;
685 	struct smu_table *memory_pool = &smu_table->memory_pool;
686 	int ret = 0;
687 	uint64_t address;
688 	uint32_t address_low, address_high;
689 
690 	if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
691 		return ret;
692 
693 	address = memory_pool->mc_address;
694 	address_high = (uint32_t)upper_32_bits(address);
695 	address_low  = (uint32_t)lower_32_bits(address);
696 
697 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
698 					      address_high, NULL);
699 	if (ret)
700 		return ret;
701 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
702 					      address_low, NULL);
703 	if (ret)
704 		return ret;
705 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
706 					      (uint32_t)memory_pool->size, NULL);
707 	if (ret)
708 		return ret;
709 
710 	return ret;
711 }
712 
smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)713 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
714 {
715 	int ret;
716 
717 	ret = smu_cmn_send_smc_msg_with_param(smu,
718 					      SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
719 	if (ret)
720 		dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
721 
722 	return ret;
723 }
724 
smu_v13_0_set_driver_table_location(struct smu_context * smu)725 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
726 {
727 	struct smu_table *driver_table = &smu->smu_table.driver_table;
728 	int ret = 0;
729 
730 	if (driver_table->mc_address) {
731 		ret = smu_cmn_send_smc_msg_with_param(smu,
732 						      SMU_MSG_SetDriverDramAddrHigh,
733 						      upper_32_bits(driver_table->mc_address),
734 						      NULL);
735 		if (!ret)
736 			ret = smu_cmn_send_smc_msg_with_param(smu,
737 							      SMU_MSG_SetDriverDramAddrLow,
738 							      lower_32_bits(driver_table->mc_address),
739 							      NULL);
740 	}
741 
742 	return ret;
743 }
744 
smu_v13_0_set_tool_table_location(struct smu_context * smu)745 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
746 {
747 	int ret = 0;
748 	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
749 
750 	if (tool_table->mc_address) {
751 		ret = smu_cmn_send_smc_msg_with_param(smu,
752 						      SMU_MSG_SetToolsDramAddrHigh,
753 						      upper_32_bits(tool_table->mc_address),
754 						      NULL);
755 		if (!ret)
756 			ret = smu_cmn_send_smc_msg_with_param(smu,
757 							      SMU_MSG_SetToolsDramAddrLow,
758 							      lower_32_bits(tool_table->mc_address),
759 							      NULL);
760 	}
761 
762 	return ret;
763 }
764 
smu_v13_0_init_display_count(struct smu_context * smu,uint32_t count)765 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
766 {
767 	int ret = 0;
768 
769 	if (!smu->pm_enabled)
770 		return ret;
771 
772 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
773 
774 	return ret;
775 }
776 
smu_v13_0_set_allowed_mask(struct smu_context * smu)777 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
778 {
779 	struct smu_feature *feature = &smu->smu_feature;
780 	int ret = 0;
781 	uint32_t feature_mask[2];
782 
783 	if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
784 	    feature->feature_num < 64)
785 		return -EINVAL;
786 
787 	bitmap_to_arr32(feature_mask, feature->allowed, 64);
788 
789 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
790 					      feature_mask[1], NULL);
791 	if (ret)
792 		return ret;
793 
794 	return smu_cmn_send_smc_msg_with_param(smu,
795 					       SMU_MSG_SetAllowedFeaturesMaskLow,
796 					       feature_mask[0],
797 					       NULL);
798 }
799 
smu_v13_0_gfx_off_control(struct smu_context * smu,bool enable)800 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
801 {
802 	int ret = 0;
803 	struct amdgpu_device *adev = smu->adev;
804 
805 	switch (adev->ip_versions[MP1_HWIP][0]) {
806 	case IP_VERSION(13, 0, 0):
807 	case IP_VERSION(13, 0, 1):
808 	case IP_VERSION(13, 0, 3):
809 	case IP_VERSION(13, 0, 4):
810 	case IP_VERSION(13, 0, 5):
811 	case IP_VERSION(13, 0, 7):
812 	case IP_VERSION(13, 0, 8):
813 	case IP_VERSION(13, 0, 10):
814 	case IP_VERSION(13, 0, 11):
815 		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
816 			return 0;
817 		if (enable)
818 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
819 		else
820 			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
821 		break;
822 	default:
823 		break;
824 	}
825 
826 	return ret;
827 }
828 
smu_v13_0_system_features_control(struct smu_context * smu,bool en)829 int smu_v13_0_system_features_control(struct smu_context *smu,
830 				      bool en)
831 {
832 	return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
833 					  SMU_MSG_DisableAllSmuFeatures), NULL);
834 }
835 
smu_v13_0_notify_display_change(struct smu_context * smu)836 int smu_v13_0_notify_display_change(struct smu_context *smu)
837 {
838 	int ret = 0;
839 
840 	if (!amdgpu_device_has_dc_support(smu->adev))
841 		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DALNotPresent, NULL);
842 
843 	return ret;
844 }
845 
846 	static int
smu_v13_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)847 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
848 				    enum smu_clk_type clock_select)
849 {
850 	int ret = 0;
851 	int clk_id;
852 
853 	if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
854 	    (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
855 		return 0;
856 
857 	clk_id = smu_cmn_to_asic_specific_index(smu,
858 						CMN2ASIC_MAPPING_CLK,
859 						clock_select);
860 	if (clk_id < 0)
861 		return -EINVAL;
862 
863 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
864 					      clk_id << 16, clock);
865 	if (ret) {
866 		dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
867 		return ret;
868 	}
869 
870 	if (*clock != 0)
871 		return 0;
872 
873 	/* if DC limit is zero, return AC limit */
874 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
875 					      clk_id << 16, clock);
876 	if (ret) {
877 		dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
878 		return ret;
879 	}
880 
881 	return 0;
882 }
883 
smu_v13_0_init_max_sustainable_clocks(struct smu_context * smu)884 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
885 {
886 	struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
887 		smu->smu_table.max_sustainable_clocks;
888 	int ret = 0;
889 
890 	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
891 	max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
892 	max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
893 	max_sustainable_clocks->display_clock = 0xFFFFFFFF;
894 	max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
895 	max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
896 
897 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
898 		ret = smu_v13_0_get_max_sustainable_clock(smu,
899 							  &(max_sustainable_clocks->uclock),
900 							  SMU_UCLK);
901 		if (ret) {
902 			dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
903 				__func__);
904 			return ret;
905 		}
906 	}
907 
908 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
909 		ret = smu_v13_0_get_max_sustainable_clock(smu,
910 							  &(max_sustainable_clocks->soc_clock),
911 							  SMU_SOCCLK);
912 		if (ret) {
913 			dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
914 				__func__);
915 			return ret;
916 		}
917 	}
918 
919 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
920 		ret = smu_v13_0_get_max_sustainable_clock(smu,
921 							  &(max_sustainable_clocks->dcef_clock),
922 							  SMU_DCEFCLK);
923 		if (ret) {
924 			dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
925 				__func__);
926 			return ret;
927 		}
928 
929 		ret = smu_v13_0_get_max_sustainable_clock(smu,
930 							  &(max_sustainable_clocks->display_clock),
931 							  SMU_DISPCLK);
932 		if (ret) {
933 			dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
934 				__func__);
935 			return ret;
936 		}
937 		ret = smu_v13_0_get_max_sustainable_clock(smu,
938 							  &(max_sustainable_clocks->phy_clock),
939 							  SMU_PHYCLK);
940 		if (ret) {
941 			dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
942 				__func__);
943 			return ret;
944 		}
945 		ret = smu_v13_0_get_max_sustainable_clock(smu,
946 							  &(max_sustainable_clocks->pixel_clock),
947 							  SMU_PIXCLK);
948 		if (ret) {
949 			dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
950 				__func__);
951 			return ret;
952 		}
953 	}
954 
955 	if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
956 		max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
957 
958 	return 0;
959 }
960 
smu_v13_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)961 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
962 				      uint32_t *power_limit)
963 {
964 	int power_src;
965 	int ret = 0;
966 
967 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
968 		return -EINVAL;
969 
970 	power_src = smu_cmn_to_asic_specific_index(smu,
971 						   CMN2ASIC_MAPPING_PWR,
972 						   smu->adev->pm.ac_power ?
973 						   SMU_POWER_SOURCE_AC :
974 						   SMU_POWER_SOURCE_DC);
975 	if (power_src < 0)
976 		return -EINVAL;
977 
978 	ret = smu_cmn_send_smc_msg_with_param(smu,
979 					      SMU_MSG_GetPptLimit,
980 					      power_src << 16,
981 					      power_limit);
982 	if (ret)
983 		dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
984 
985 	return ret;
986 }
987 
smu_v13_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)988 int smu_v13_0_set_power_limit(struct smu_context *smu,
989 			      enum smu_ppt_limit_type limit_type,
990 			      uint32_t limit)
991 {
992 	int ret = 0;
993 
994 	if (limit_type != SMU_DEFAULT_PPT_LIMIT)
995 		return -EINVAL;
996 
997 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
998 		dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
999 		return -EOPNOTSUPP;
1000 	}
1001 
1002 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1003 	if (ret) {
1004 		dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1005 		return ret;
1006 	}
1007 
1008 	smu->current_power_limit = limit;
1009 
1010 	return 0;
1011 }
1012 
smu_v13_0_allow_ih_interrupt(struct smu_context * smu)1013 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1014 {
1015 	return smu_cmn_send_smc_msg(smu,
1016 				    SMU_MSG_AllowIHHostInterrupt,
1017 				    NULL);
1018 }
1019 
smu_v13_0_process_pending_interrupt(struct smu_context * smu)1020 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1021 {
1022 	int ret = 0;
1023 
1024 	if (smu->dc_controlled_by_gpio &&
1025 	    smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1026 		ret = smu_v13_0_allow_ih_interrupt(smu);
1027 
1028 	return ret;
1029 }
1030 
smu_v13_0_enable_thermal_alert(struct smu_context * smu)1031 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1032 {
1033 	int ret = 0;
1034 
1035 	if (!smu->irq_source.num_types)
1036 		return 0;
1037 
1038 	ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1039 	if (ret)
1040 		return ret;
1041 
1042 	return smu_v13_0_process_pending_interrupt(smu);
1043 }
1044 
smu_v13_0_disable_thermal_alert(struct smu_context * smu)1045 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1046 {
1047 	if (!smu->irq_source.num_types)
1048 		return 0;
1049 
1050 	return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1051 }
1052 
convert_to_vddc(uint8_t vid)1053 static uint16_t convert_to_vddc(uint8_t vid)
1054 {
1055 	return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1056 }
1057 
smu_v13_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1058 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1059 {
1060 	struct amdgpu_device *adev = smu->adev;
1061 	uint32_t vdd = 0, val_vid = 0;
1062 
1063 	if (!value)
1064 		return -EINVAL;
1065 	val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1066 		   SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1067 		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1068 
1069 	vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1070 
1071 	*value = vdd;
1072 
1073 	return 0;
1074 
1075 }
1076 
1077 int
smu_v13_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1078 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1079 					struct pp_display_clock_request
1080 					*clock_req)
1081 {
1082 	enum amd_pp_clock_type clk_type = clock_req->clock_type;
1083 	int ret = 0;
1084 	enum smu_clk_type clk_select = 0;
1085 	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1086 
1087 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1088 	    smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1089 		switch (clk_type) {
1090 		case amd_pp_dcef_clock:
1091 			clk_select = SMU_DCEFCLK;
1092 			break;
1093 		case amd_pp_disp_clock:
1094 			clk_select = SMU_DISPCLK;
1095 			break;
1096 		case amd_pp_pixel_clock:
1097 			clk_select = SMU_PIXCLK;
1098 			break;
1099 		case amd_pp_phy_clock:
1100 			clk_select = SMU_PHYCLK;
1101 			break;
1102 		case amd_pp_mem_clock:
1103 			clk_select = SMU_UCLK;
1104 			break;
1105 		default:
1106 			dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1107 			ret = -EINVAL;
1108 			break;
1109 		}
1110 
1111 		if (ret)
1112 			goto failed;
1113 
1114 		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1115 			return 0;
1116 
1117 		ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1118 
1119 		if (clk_select == SMU_UCLK)
1120 			smu->hard_min_uclk_req_from_dal = clk_freq;
1121 	}
1122 
1123 failed:
1124 	return ret;
1125 }
1126 
smu_v13_0_get_fan_control_mode(struct smu_context * smu)1127 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1128 {
1129 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1130 		return AMD_FAN_CTRL_MANUAL;
1131 	else
1132 		return AMD_FAN_CTRL_AUTO;
1133 }
1134 
1135 	static int
smu_v13_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1136 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1137 {
1138 	int ret = 0;
1139 
1140 	if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1141 		return 0;
1142 
1143 	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1144 	if (ret)
1145 		dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1146 			__func__, (auto_fan_control ? "Start" : "Stop"));
1147 
1148 	return ret;
1149 }
1150 
1151 	static int
smu_v13_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1152 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1153 {
1154 	struct amdgpu_device *adev = smu->adev;
1155 
1156 	WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1157 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1158 				   CG_FDO_CTRL2, TMIN, 0));
1159 	WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1160 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1161 				   CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1162 
1163 	return 0;
1164 }
1165 
smu_v13_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1166 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1167 				uint32_t speed)
1168 {
1169 	struct amdgpu_device *adev = smu->adev;
1170 	uint32_t duty100, duty;
1171 	uint64_t tmp64;
1172 
1173 	speed = MIN(speed, 255);
1174 
1175 	if (smu_v13_0_auto_fan_control(smu, 0))
1176 		return -EINVAL;
1177 
1178 	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1179 				CG_FDO_CTRL1, FMAX_DUTY100);
1180 	if (!duty100)
1181 		return -EINVAL;
1182 
1183 	tmp64 = (uint64_t)speed * duty100;
1184 	do_div(tmp64, 255);
1185 	duty = (uint32_t)tmp64;
1186 
1187 	WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1188 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1189 				   CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1190 
1191 	return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1192 }
1193 
1194 	int
smu_v13_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1195 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1196 			       uint32_t mode)
1197 {
1198 	int ret = 0;
1199 
1200 	switch (mode) {
1201 	case AMD_FAN_CTRL_NONE:
1202 		ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1203 		break;
1204 	case AMD_FAN_CTRL_MANUAL:
1205 		ret = smu_v13_0_auto_fan_control(smu, 0);
1206 		break;
1207 	case AMD_FAN_CTRL_AUTO:
1208 		ret = smu_v13_0_auto_fan_control(smu, 1);
1209 		break;
1210 	default:
1211 		break;
1212 	}
1213 
1214 	if (ret) {
1215 		dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1216 		return -EINVAL;
1217 	}
1218 
1219 	return ret;
1220 }
1221 
smu_v13_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1222 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1223 				uint32_t speed)
1224 {
1225 	struct amdgpu_device *adev = smu->adev;
1226 	uint32_t crystal_clock_freq = 2500;
1227 	uint32_t tach_period;
1228 	int ret;
1229 
1230 	if (!speed)
1231 		return -EINVAL;
1232 
1233 	ret = smu_v13_0_auto_fan_control(smu, 0);
1234 	if (ret)
1235 		return ret;
1236 
1237 	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1238 	WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1239 		     REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1240 				   CG_TACH_CTRL, TARGET_PERIOD,
1241 				   tach_period));
1242 
1243 	return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1244 }
1245 
smu_v13_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1246 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1247 			      uint32_t pstate)
1248 {
1249 	int ret = 0;
1250 	ret = smu_cmn_send_smc_msg_with_param(smu,
1251 					      SMU_MSG_SetXgmiMode,
1252 					      pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1253 					      NULL);
1254 	return ret;
1255 }
1256 
smu_v13_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1257 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1258 				   struct amdgpu_irq_src *source,
1259 				   unsigned tyep,
1260 				   enum amdgpu_interrupt_state state)
1261 {
1262 	struct smu_context *smu = adev->powerplay.pp_handle;
1263 	uint32_t low, high;
1264 	uint32_t val = 0;
1265 
1266 	switch (state) {
1267 	case AMDGPU_IRQ_STATE_DISABLE:
1268 		/* For THM irqs */
1269 		val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1270 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1271 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1272 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1273 
1274 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1275 
1276 		/* For MP1 SW irqs */
1277 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1278 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1279 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1280 
1281 		break;
1282 	case AMDGPU_IRQ_STATE_ENABLE:
1283 		/* For THM irqs */
1284 		low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1285 			  smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1286 		high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1287 			   smu->thermal_range.software_shutdown_temp);
1288 
1289 		val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1290 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1291 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1292 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1293 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1294 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1295 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1296 		val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1297 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1298 
1299 		val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1300 		val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1301 		val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1302 		WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1303 
1304 		/* For MP1 SW irqs */
1305 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1306 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1307 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1308 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1309 
1310 		val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1311 		val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1312 		WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1313 
1314 		break;
1315 	default:
1316 		break;
1317 	}
1318 
1319 	return 0;
1320 }
1321 
smu_v13_0_ack_ac_dc_interrupt(struct smu_context * smu)1322 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1323 {
1324 	return smu_cmn_send_smc_msg(smu,
1325 				    SMU_MSG_ReenableAcDcInterrupt,
1326 				    NULL);
1327 }
1328 
1329 #define THM_11_0__SRCID__THM_DIG_THERM_L2H		0		/* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1330 #define THM_11_0__SRCID__THM_DIG_THERM_H2L		1		/* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1331 #define SMUIO_11_0__SRCID__SMUIO_GPIO19			83
1332 
smu_v13_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1333 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1334 				 struct amdgpu_irq_src *source,
1335 				 struct amdgpu_iv_entry *entry)
1336 {
1337 	struct smu_context *smu = adev->powerplay.pp_handle;
1338 	uint32_t client_id = entry->client_id;
1339 	uint32_t src_id = entry->src_id;
1340 	/*
1341 	 * ctxid is used to distinguish different
1342 	 * events for SMCToHost interrupt.
1343 	 */
1344 	uint32_t ctxid = entry->src_data[0];
1345 	uint32_t data;
1346 	uint32_t high;
1347 
1348 	if (client_id == SOC15_IH_CLIENTID_THM) {
1349 		switch (src_id) {
1350 		case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1351 			schedule_delayed_work(&smu->swctf_delayed_work,
1352 					      msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1353 			break;
1354 		case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1355 			dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1356 			break;
1357 		default:
1358 			dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1359 				  src_id);
1360 			break;
1361 		}
1362 	} else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1363 		dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1364 		/*
1365 		 * HW CTF just occurred. Shutdown to prevent further damage.
1366 		 */
1367 		dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1368 		orderly_poweroff(true);
1369 	} else if (client_id == SOC15_IH_CLIENTID_MP1) {
1370 		if (src_id == 0xfe) {
1371 			/* ACK SMUToHost interrupt */
1372 			data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1373 			data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1374 			WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1375 
1376 			switch (ctxid) {
1377 			case 0x3:
1378 				dev_dbg(adev->dev, "Switched to AC mode!\n");
1379 				smu_v13_0_ack_ac_dc_interrupt(smu);
1380 				break;
1381 			case 0x4:
1382 				dev_dbg(adev->dev, "Switched to DC mode!\n");
1383 				smu_v13_0_ack_ac_dc_interrupt(smu);
1384 				break;
1385 			case 0x7:
1386 				/*
1387 				 * Increment the throttle interrupt counter
1388 				 */
1389 				atomic64_inc(&smu->throttle_int_counter);
1390 
1391 				if (!atomic_read(&adev->throttling_logging_enabled))
1392 					return 0;
1393 
1394 				if (__ratelimit(&adev->throttling_logging_rs))
1395 					schedule_work(&smu->throttling_logging_work);
1396 
1397 				break;
1398 			case 0x8:
1399 				high = smu->thermal_range.software_shutdown_temp +
1400 					smu->thermal_range.software_shutdown_temp_offset;
1401 				high = min_t(typeof(high),
1402 					     SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1403 					     high);
1404 				dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1405 							high,
1406 							smu->thermal_range.software_shutdown_temp_offset);
1407 
1408 				data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1409 				data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1410 							DIG_THERM_INTH,
1411 							(high & 0xff));
1412 				data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1413 				WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1414 				break;
1415 			case 0x9:
1416 				high = min_t(typeof(high),
1417 					     SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1418 					     smu->thermal_range.software_shutdown_temp);
1419 				dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1420 
1421 				data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1422 				data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1423 							DIG_THERM_INTH,
1424 							(high & 0xff));
1425 				data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1426 				WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1427 				break;
1428 			}
1429 		}
1430 	}
1431 
1432 	return 0;
1433 }
1434 
1435 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1436 	.set = smu_v13_0_set_irq_state,
1437 	.process = smu_v13_0_irq_process,
1438 };
1439 
smu_v13_0_register_irq_handler(struct smu_context * smu)1440 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1441 {
1442 	struct amdgpu_device *adev = smu->adev;
1443 	struct amdgpu_irq_src *irq_src = &smu->irq_source;
1444 	int ret = 0;
1445 
1446 	if (amdgpu_sriov_vf(adev))
1447 		return 0;
1448 
1449 	irq_src->num_types = 1;
1450 	irq_src->funcs = &smu_v13_0_irq_funcs;
1451 
1452 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1453 				THM_11_0__SRCID__THM_DIG_THERM_L2H,
1454 				irq_src);
1455 	if (ret)
1456 		return ret;
1457 
1458 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1459 				THM_11_0__SRCID__THM_DIG_THERM_H2L,
1460 				irq_src);
1461 	if (ret)
1462 		return ret;
1463 
1464 	/* Register CTF(GPIO_19) interrupt */
1465 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1466 				SMUIO_11_0__SRCID__SMUIO_GPIO19,
1467 				irq_src);
1468 	if (ret)
1469 		return ret;
1470 
1471 	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1472 				0xfe,
1473 				irq_src);
1474 	if (ret)
1475 		return ret;
1476 
1477 	return ret;
1478 }
1479 
smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1480 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1481 					       struct pp_smu_nv_clock_table *max_clocks)
1482 {
1483 	struct smu_table_context *table_context = &smu->smu_table;
1484 	struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1485 
1486 	if (!max_clocks || !table_context->max_sustainable_clocks)
1487 		return -EINVAL;
1488 
1489 	sustainable_clocks = table_context->max_sustainable_clocks;
1490 
1491 	max_clocks->dcfClockInKhz =
1492 		(unsigned int) sustainable_clocks->dcef_clock * 1000;
1493 	max_clocks->displayClockInKhz =
1494 		(unsigned int) sustainable_clocks->display_clock * 1000;
1495 	max_clocks->phyClockInKhz =
1496 		(unsigned int) sustainable_clocks->phy_clock * 1000;
1497 	max_clocks->pixelClockInKhz =
1498 		(unsigned int) sustainable_clocks->pixel_clock * 1000;
1499 	max_clocks->uClockInKhz =
1500 		(unsigned int) sustainable_clocks->uclock * 1000;
1501 	max_clocks->socClockInKhz =
1502 		(unsigned int) sustainable_clocks->soc_clock * 1000;
1503 	max_clocks->dscClockInKhz = 0;
1504 	max_clocks->dppClockInKhz = 0;
1505 	max_clocks->fabricClockInKhz = 0;
1506 
1507 	return 0;
1508 }
1509 
smu_v13_0_set_azalia_d3_pme(struct smu_context * smu)1510 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1511 {
1512 	int ret = 0;
1513 
1514 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1515 
1516 	return ret;
1517 }
1518 
smu_v13_0_wait_for_reset_complete(struct smu_context * smu,uint64_t event_arg)1519 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1520 					     uint64_t event_arg)
1521 {
1522 	int ret = 0;
1523 
1524 	dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1525 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1526 
1527 	return ret;
1528 }
1529 
smu_v13_0_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)1530 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1531 			     uint64_t event_arg)
1532 {
1533 	int ret = -EINVAL;
1534 
1535 	switch (event) {
1536 	case SMU_EVENT_RESET_COMPLETE:
1537 		ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1538 		break;
1539 	default:
1540 		break;
1541 	}
1542 
1543 	return ret;
1544 }
1545 
smu_v13_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1546 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1547 				    uint32_t *min, uint32_t *max)
1548 {
1549 	int ret = 0, clk_id = 0;
1550 	uint32_t param = 0;
1551 	uint32_t clock_limit;
1552 
1553 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1554 		switch (clk_type) {
1555 		case SMU_MCLK:
1556 		case SMU_UCLK:
1557 			clock_limit = smu->smu_table.boot_values.uclk;
1558 			break;
1559 		case SMU_GFXCLK:
1560 		case SMU_SCLK:
1561 			clock_limit = smu->smu_table.boot_values.gfxclk;
1562 			break;
1563 		case SMU_SOCCLK:
1564 			clock_limit = smu->smu_table.boot_values.socclk;
1565 			break;
1566 		default:
1567 			clock_limit = 0;
1568 			break;
1569 		}
1570 
1571 		/* clock in Mhz unit */
1572 		if (min)
1573 			*min = clock_limit / 100;
1574 		if (max)
1575 			*max = clock_limit / 100;
1576 
1577 		return 0;
1578 	}
1579 
1580 	clk_id = smu_cmn_to_asic_specific_index(smu,
1581 						CMN2ASIC_MAPPING_CLK,
1582 						clk_type);
1583 	if (clk_id < 0) {
1584 		ret = -EINVAL;
1585 		goto failed;
1586 	}
1587 	param = (clk_id & 0xffff) << 16;
1588 
1589 	if (max) {
1590 		if (smu->adev->pm.ac_power)
1591 			ret = smu_cmn_send_smc_msg_with_param(smu,
1592 							      SMU_MSG_GetMaxDpmFreq,
1593 							      param,
1594 							      max);
1595 		else
1596 			ret = smu_cmn_send_smc_msg_with_param(smu,
1597 							      SMU_MSG_GetDcModeMaxDpmFreq,
1598 							      param,
1599 							      max);
1600 		if (ret)
1601 			goto failed;
1602 	}
1603 
1604 	if (min) {
1605 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1606 		if (ret)
1607 			goto failed;
1608 	}
1609 
1610 failed:
1611 	return ret;
1612 }
1613 
smu_v13_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1614 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1615 					  enum smu_clk_type clk_type,
1616 					  uint32_t min,
1617 					  uint32_t max)
1618 {
1619 	int ret = 0, clk_id = 0;
1620 	uint32_t param;
1621 
1622 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1623 		return 0;
1624 
1625 	clk_id = smu_cmn_to_asic_specific_index(smu,
1626 						CMN2ASIC_MAPPING_CLK,
1627 						clk_type);
1628 	if (clk_id < 0)
1629 		return clk_id;
1630 
1631 	if (max > 0) {
1632 		param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1633 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1634 						      param, NULL);
1635 		if (ret)
1636 			goto out;
1637 	}
1638 
1639 	if (min > 0) {
1640 		param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1641 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1642 						      param, NULL);
1643 		if (ret)
1644 			goto out;
1645 	}
1646 
1647 out:
1648 	return ret;
1649 }
1650 
smu_v13_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1651 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1652 					  enum smu_clk_type clk_type,
1653 					  uint32_t min,
1654 					  uint32_t max)
1655 {
1656 	int ret = 0, clk_id = 0;
1657 	uint32_t param;
1658 
1659 	if (min <= 0 && max <= 0)
1660 		return -EINVAL;
1661 
1662 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1663 		return 0;
1664 
1665 	clk_id = smu_cmn_to_asic_specific_index(smu,
1666 						CMN2ASIC_MAPPING_CLK,
1667 						clk_type);
1668 	if (clk_id < 0)
1669 		return clk_id;
1670 
1671 	if (max > 0) {
1672 		param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1673 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1674 						      param, NULL);
1675 		if (ret)
1676 			return ret;
1677 	}
1678 
1679 	if (min > 0) {
1680 		param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1681 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1682 						      param, NULL);
1683 		if (ret)
1684 			return ret;
1685 	}
1686 
1687 	return ret;
1688 }
1689 
smu_v13_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1690 int smu_v13_0_set_performance_level(struct smu_context *smu,
1691 				    enum amd_dpm_forced_level level)
1692 {
1693 	struct smu_13_0_dpm_context *dpm_context =
1694 		smu->smu_dpm.dpm_context;
1695 	struct smu_13_0_dpm_table *gfx_table =
1696 		&dpm_context->dpm_tables.gfx_table;
1697 	struct smu_13_0_dpm_table *mem_table =
1698 		&dpm_context->dpm_tables.uclk_table;
1699 	struct smu_13_0_dpm_table *soc_table =
1700 		&dpm_context->dpm_tables.soc_table;
1701 	struct smu_13_0_dpm_table *vclk_table =
1702 		&dpm_context->dpm_tables.vclk_table;
1703 	struct smu_13_0_dpm_table *dclk_table =
1704 		&dpm_context->dpm_tables.dclk_table;
1705 	struct smu_13_0_dpm_table *fclk_table =
1706 		&dpm_context->dpm_tables.fclk_table;
1707 	struct smu_umd_pstate_table *pstate_table =
1708 		&smu->pstate_table;
1709 	struct amdgpu_device *adev = smu->adev;
1710 	uint32_t sclk_min = 0, sclk_max = 0;
1711 	uint32_t mclk_min = 0, mclk_max = 0;
1712 	uint32_t socclk_min = 0, socclk_max = 0;
1713 	uint32_t vclk_min = 0, vclk_max = 0;
1714 	uint32_t dclk_min = 0, dclk_max = 0;
1715 	uint32_t fclk_min = 0, fclk_max = 0;
1716 	int ret = 0, i;
1717 
1718 	switch (level) {
1719 	case AMD_DPM_FORCED_LEVEL_HIGH:
1720 		sclk_min = sclk_max = gfx_table->max;
1721 		mclk_min = mclk_max = mem_table->max;
1722 		socclk_min = socclk_max = soc_table->max;
1723 		vclk_min = vclk_max = vclk_table->max;
1724 		dclk_min = dclk_max = dclk_table->max;
1725 		fclk_min = fclk_max = fclk_table->max;
1726 		break;
1727 	case AMD_DPM_FORCED_LEVEL_LOW:
1728 		sclk_min = sclk_max = gfx_table->min;
1729 		mclk_min = mclk_max = mem_table->min;
1730 		socclk_min = socclk_max = soc_table->min;
1731 		vclk_min = vclk_max = vclk_table->min;
1732 		dclk_min = dclk_max = dclk_table->min;
1733 		fclk_min = fclk_max = fclk_table->min;
1734 		break;
1735 	case AMD_DPM_FORCED_LEVEL_AUTO:
1736 		sclk_min = gfx_table->min;
1737 		sclk_max = gfx_table->max;
1738 		mclk_min = mem_table->min;
1739 		mclk_max = mem_table->max;
1740 		socclk_min = soc_table->min;
1741 		socclk_max = soc_table->max;
1742 		vclk_min = vclk_table->min;
1743 		vclk_max = vclk_table->max;
1744 		dclk_min = dclk_table->min;
1745 		dclk_max = dclk_table->max;
1746 		fclk_min = fclk_table->min;
1747 		fclk_max = fclk_table->max;
1748 		break;
1749 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1750 		sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1751 		mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1752 		socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1753 		vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1754 		dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1755 		fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1756 		break;
1757 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1758 		sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1759 		break;
1760 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1761 		mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1762 		break;
1763 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1764 		sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1765 		mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1766 		socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1767 		vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1768 		dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1769 		fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1770 		break;
1771 	case AMD_DPM_FORCED_LEVEL_MANUAL:
1772 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1773 		return 0;
1774 	default:
1775 		dev_err(adev->dev, "Invalid performance level %d\n", level);
1776 		return -EINVAL;
1777 	}
1778 
1779 	/*
1780 	 * Unset those settings for SMU 13.0.2. As soft limits settings
1781 	 * for those clock domains are not supported.
1782 	 */
1783 	if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1784 		mclk_min = mclk_max = 0;
1785 		socclk_min = socclk_max = 0;
1786 		vclk_min = vclk_max = 0;
1787 		dclk_min = dclk_max = 0;
1788 		fclk_min = fclk_max = 0;
1789 	}
1790 
1791 	if (sclk_min && sclk_max) {
1792 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1793 							    SMU_GFXCLK,
1794 							    sclk_min,
1795 							    sclk_max);
1796 		if (ret)
1797 			return ret;
1798 
1799 		pstate_table->gfxclk_pstate.curr.min = sclk_min;
1800 		pstate_table->gfxclk_pstate.curr.max = sclk_max;
1801 	}
1802 
1803 	if (mclk_min && mclk_max) {
1804 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1805 							    SMU_MCLK,
1806 							    mclk_min,
1807 							    mclk_max);
1808 		if (ret)
1809 			return ret;
1810 
1811 		pstate_table->uclk_pstate.curr.min = mclk_min;
1812 		pstate_table->uclk_pstate.curr.max = mclk_max;
1813 	}
1814 
1815 	if (socclk_min && socclk_max) {
1816 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1817 							    SMU_SOCCLK,
1818 							    socclk_min,
1819 							    socclk_max);
1820 		if (ret)
1821 			return ret;
1822 
1823 		pstate_table->socclk_pstate.curr.min = socclk_min;
1824 		pstate_table->socclk_pstate.curr.max = socclk_max;
1825 	}
1826 
1827 	if (vclk_min && vclk_max) {
1828 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1829 			if (adev->vcn.harvest_config & (1 << i))
1830 				continue;
1831 			ret = smu_v13_0_set_soft_freq_limited_range(smu,
1832 								    i ? SMU_VCLK1 : SMU_VCLK,
1833 								    vclk_min,
1834 								    vclk_max);
1835 			if (ret)
1836 				return ret;
1837 		}
1838 		pstate_table->vclk_pstate.curr.min = vclk_min;
1839 		pstate_table->vclk_pstate.curr.max = vclk_max;
1840 	}
1841 
1842 	if (dclk_min && dclk_max) {
1843 		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1844 			if (adev->vcn.harvest_config & (1 << i))
1845 				continue;
1846 			ret = smu_v13_0_set_soft_freq_limited_range(smu,
1847 								    i ? SMU_DCLK1 : SMU_DCLK,
1848 								    dclk_min,
1849 								    dclk_max);
1850 			if (ret)
1851 				return ret;
1852 		}
1853 		pstate_table->dclk_pstate.curr.min = dclk_min;
1854 		pstate_table->dclk_pstate.curr.max = dclk_max;
1855 	}
1856 
1857 	if (fclk_min && fclk_max) {
1858 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
1859 							    SMU_FCLK,
1860 							    fclk_min,
1861 							    fclk_max);
1862 		if (ret)
1863 			return ret;
1864 
1865 		pstate_table->fclk_pstate.curr.min = fclk_min;
1866 		pstate_table->fclk_pstate.curr.max = fclk_max;
1867 	}
1868 
1869 	return ret;
1870 }
1871 
smu_v13_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1872 int smu_v13_0_set_power_source(struct smu_context *smu,
1873 			       enum smu_power_src_type power_src)
1874 {
1875 	int pwr_source;
1876 
1877 	pwr_source = smu_cmn_to_asic_specific_index(smu,
1878 						    CMN2ASIC_MAPPING_PWR,
1879 						    (uint32_t)power_src);
1880 	if (pwr_source < 0)
1881 		return -EINVAL;
1882 
1883 	return smu_cmn_send_smc_msg_with_param(smu,
1884 					       SMU_MSG_NotifyPowerSource,
1885 					       pwr_source,
1886 					       NULL);
1887 }
1888 
smu_v13_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1889 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1890 				    enum smu_clk_type clk_type, uint16_t level,
1891 				    uint32_t *value)
1892 {
1893 	int ret = 0, clk_id = 0;
1894 	uint32_t param;
1895 
1896 	if (!value)
1897 		return -EINVAL;
1898 
1899 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1900 		return 0;
1901 
1902 	clk_id = smu_cmn_to_asic_specific_index(smu,
1903 						CMN2ASIC_MAPPING_CLK,
1904 						clk_type);
1905 	if (clk_id < 0)
1906 		return clk_id;
1907 
1908 	param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1909 
1910 	ret = smu_cmn_send_smc_msg_with_param(smu,
1911 					      SMU_MSG_GetDpmFreqByIndex,
1912 					      param,
1913 					      value);
1914 	if (ret)
1915 		return ret;
1916 
1917 	*value = *value & 0x7fffffff;
1918 
1919 	return ret;
1920 }
1921 
smu_v13_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1922 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1923 					 enum smu_clk_type clk_type,
1924 					 uint32_t *value)
1925 {
1926 	int ret;
1927 
1928 	ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1929 	/* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1930 	if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1931 		++(*value);
1932 
1933 	return ret;
1934 }
1935 
smu_v13_0_get_fine_grained_status(struct smu_context * smu,enum smu_clk_type clk_type,bool * is_fine_grained_dpm)1936 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1937 					     enum smu_clk_type clk_type,
1938 					     bool *is_fine_grained_dpm)
1939 {
1940 	int ret = 0, clk_id = 0;
1941 	uint32_t param;
1942 	uint32_t value;
1943 
1944 	if (!is_fine_grained_dpm)
1945 		return -EINVAL;
1946 
1947 	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1948 		return 0;
1949 
1950 	clk_id = smu_cmn_to_asic_specific_index(smu,
1951 						CMN2ASIC_MAPPING_CLK,
1952 						clk_type);
1953 	if (clk_id < 0)
1954 		return clk_id;
1955 
1956 	param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1957 
1958 	ret = smu_cmn_send_smc_msg_with_param(smu,
1959 					      SMU_MSG_GetDpmFreqByIndex,
1960 					      param,
1961 					      &value);
1962 	if (ret)
1963 		return ret;
1964 
1965 	/*
1966 	 * BIT31:  1 - Fine grained DPM, 0 - Dicrete DPM
1967 	 * now, we un-support it
1968 	 */
1969 	*is_fine_grained_dpm = value & 0x80000000;
1970 
1971 	return 0;
1972 }
1973 
smu_v13_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_13_0_dpm_table * single_dpm_table)1974 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1975 				   enum smu_clk_type clk_type,
1976 				   struct smu_13_0_dpm_table *single_dpm_table)
1977 {
1978 	int ret = 0;
1979 	uint32_t clk;
1980 	int i;
1981 
1982 	ret = smu_v13_0_get_dpm_level_count(smu,
1983 					    clk_type,
1984 					    &single_dpm_table->count);
1985 	if (ret) {
1986 		dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1987 		return ret;
1988 	}
1989 
1990 	if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
1991 		ret = smu_v13_0_get_fine_grained_status(smu,
1992 							clk_type,
1993 							&single_dpm_table->is_fine_grained);
1994 		if (ret) {
1995 			dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
1996 			return ret;
1997 		}
1998 	}
1999 
2000 	for (i = 0; i < single_dpm_table->count; i++) {
2001 		ret = smu_v13_0_get_dpm_freq_by_index(smu,
2002 						      clk_type,
2003 						      i,
2004 						      &clk);
2005 		if (ret) {
2006 			dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2007 			return ret;
2008 		}
2009 
2010 		single_dpm_table->dpm_levels[i].value = clk;
2011 		single_dpm_table->dpm_levels[i].enabled = true;
2012 
2013 		if (i == 0)
2014 			single_dpm_table->min = clk;
2015 		else if (i == single_dpm_table->count - 1)
2016 			single_dpm_table->max = clk;
2017 	}
2018 
2019 	return 0;
2020 }
2021 
smu_v13_0_get_current_pcie_link_width_level(struct smu_context * smu)2022 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2023 {
2024 	struct amdgpu_device *adev = smu->adev;
2025 
2026 	return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2027 		PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2028 		>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2029 }
2030 
smu_v13_0_get_current_pcie_link_width(struct smu_context * smu)2031 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2032 {
2033 	uint32_t width_level;
2034 
2035 	width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2036 	if (width_level > LINK_WIDTH_MAX)
2037 		width_level = 0;
2038 
2039 	return link_width[width_level];
2040 }
2041 
smu_v13_0_get_current_pcie_link_speed_level(struct smu_context * smu)2042 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2043 {
2044 	struct amdgpu_device *adev = smu->adev;
2045 
2046 	return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2047 		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2048 		>> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2049 }
2050 
smu_v13_0_get_current_pcie_link_speed(struct smu_context * smu)2051 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2052 {
2053 	uint32_t speed_level;
2054 
2055 	speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2056 	if (speed_level > LINK_SPEED_MAX)
2057 		speed_level = 0;
2058 
2059 	return link_speed[speed_level];
2060 }
2061 
smu_v13_0_set_vcn_enable(struct smu_context * smu,bool enable)2062 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2063 			     bool enable)
2064 {
2065 	struct amdgpu_device *adev = smu->adev;
2066 	int i, ret = 0;
2067 
2068 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2069 		if (adev->vcn.harvest_config & (1 << i))
2070 			continue;
2071 
2072 		ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2073 						      SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2074 						      i << 16U, NULL);
2075 		if (ret)
2076 			return ret;
2077 	}
2078 
2079 	return ret;
2080 }
2081 
smu_v13_0_set_jpeg_enable(struct smu_context * smu,bool enable)2082 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2083 			      bool enable)
2084 {
2085 	return smu_cmn_send_smc_msg_with_param(smu, enable ?
2086 					       SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2087 					       0, NULL);
2088 }
2089 
smu_v13_0_run_btc(struct smu_context * smu)2090 int smu_v13_0_run_btc(struct smu_context *smu)
2091 {
2092 	int res;
2093 
2094 	res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2095 	if (res)
2096 		dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2097 
2098 	return res;
2099 }
2100 
smu_v13_0_gpo_control(struct smu_context * smu,bool enablement)2101 int smu_v13_0_gpo_control(struct smu_context *smu,
2102 			  bool enablement)
2103 {
2104 	int res;
2105 
2106 	res = smu_cmn_send_smc_msg_with_param(smu,
2107 					      SMU_MSG_AllowGpo,
2108 					      enablement ? 1 : 0,
2109 					      NULL);
2110 	if (res)
2111 		dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2112 
2113 	return res;
2114 }
2115 
smu_v13_0_deep_sleep_control(struct smu_context * smu,bool enablement)2116 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2117 				 bool enablement)
2118 {
2119 	struct amdgpu_device *adev = smu->adev;
2120 	int ret = 0;
2121 
2122 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2123 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2124 		if (ret) {
2125 			dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2126 			return ret;
2127 		}
2128 	}
2129 
2130 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2131 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2132 		if (ret) {
2133 			dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2134 			return ret;
2135 		}
2136 	}
2137 
2138 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2139 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2140 		if (ret) {
2141 			dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2142 			return ret;
2143 		}
2144 	}
2145 
2146 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2147 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2148 		if (ret) {
2149 			dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2150 			return ret;
2151 		}
2152 	}
2153 
2154 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2155 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2156 		if (ret) {
2157 			dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2158 			return ret;
2159 		}
2160 	}
2161 
2162 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2163 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2164 		if (ret) {
2165 			dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2166 			return ret;
2167 		}
2168 	}
2169 
2170 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2171 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2172 		if (ret) {
2173 			dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2174 			return ret;
2175 		}
2176 	}
2177 
2178 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2179 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2180 		if (ret) {
2181 			dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2182 			return ret;
2183 		}
2184 	}
2185 
2186 	return ret;
2187 }
2188 
smu_v13_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2189 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2190 			      bool enablement)
2191 {
2192 	int ret = 0;
2193 
2194 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2195 		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2196 
2197 	return ret;
2198 }
2199 
smu_v13_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)2200 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2201 				      enum smu_baco_seq baco_seq)
2202 {
2203 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2204 	int ret;
2205 
2206 	ret = smu_cmn_send_smc_msg_with_param(smu,
2207 					      SMU_MSG_ArmD3,
2208 					      baco_seq,
2209 					      NULL);
2210 	if (ret)
2211 		return ret;
2212 
2213 	if (baco_seq == BACO_SEQ_BAMACO ||
2214 	    baco_seq == BACO_SEQ_BACO)
2215 		smu_baco->state = SMU_BACO_STATE_ENTER;
2216 	else
2217 		smu_baco->state = SMU_BACO_STATE_EXIT;
2218 
2219 	return 0;
2220 }
2221 
smu_v13_0_baco_is_support(struct smu_context * smu)2222 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2223 {
2224 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2225 
2226 	if (amdgpu_sriov_vf(smu->adev) ||
2227 	    !smu_baco->platform_support)
2228 		return false;
2229 
2230 	/* return true if ASIC is in BACO state already */
2231 	if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2232 		return true;
2233 
2234 	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2235 	    !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2236 		return false;
2237 
2238 	return true;
2239 }
2240 
smu_v13_0_baco_get_state(struct smu_context * smu)2241 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2242 {
2243 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2244 
2245 	return smu_baco->state;
2246 }
2247 
smu_v13_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)2248 int smu_v13_0_baco_set_state(struct smu_context *smu,
2249 			     enum smu_baco_state state)
2250 {
2251 	struct smu_baco_context *smu_baco = &smu->smu_baco;
2252 	struct amdgpu_device *adev = smu->adev;
2253 	int ret = 0;
2254 
2255 	if (smu_v13_0_baco_get_state(smu) == state)
2256 		return 0;
2257 
2258 	if (state == SMU_BACO_STATE_ENTER) {
2259 		ret = smu_cmn_send_smc_msg_with_param(smu,
2260 						      SMU_MSG_EnterBaco,
2261 						      (smu_baco->maco_support && amdgpu_runtime_pm != 1) ?
2262 						      BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2263 						      NULL);
2264 	} else {
2265 		ret = smu_cmn_send_smc_msg(smu,
2266 					   SMU_MSG_ExitBaco,
2267 					   NULL);
2268 		if (ret)
2269 			return ret;
2270 
2271 		/* clear vbios scratch 6 and 7 for coming asic reinit */
2272 		WREG32(adev->bios_scratch_reg_offset + 6, 0);
2273 		WREG32(adev->bios_scratch_reg_offset + 7, 0);
2274 	}
2275 
2276 	if (!ret)
2277 		smu_baco->state = state;
2278 
2279 	return ret;
2280 }
2281 
smu_v13_0_baco_enter(struct smu_context * smu)2282 int smu_v13_0_baco_enter(struct smu_context *smu)
2283 {
2284 	int ret = 0;
2285 
2286 	ret = smu_v13_0_baco_set_state(smu,
2287 				       SMU_BACO_STATE_ENTER);
2288 	if (ret)
2289 		return ret;
2290 
2291 	msleep(10);
2292 
2293 	return ret;
2294 }
2295 
smu_v13_0_baco_exit(struct smu_context * smu)2296 int smu_v13_0_baco_exit(struct smu_context *smu)
2297 {
2298 	return smu_v13_0_baco_set_state(smu,
2299 					SMU_BACO_STATE_EXIT);
2300 }
2301 
smu_v13_0_set_gfx_power_up_by_imu(struct smu_context * smu)2302 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2303 {
2304 	uint16_t index;
2305 
2306 	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2307 					       SMU_MSG_EnableGfxImu);
2308 	/* Param 1 to tell PMFW to enable GFXOFF feature */
2309 	return smu_cmn_send_msg_without_waiting(smu, index, 1);
2310 }
2311 
smu_v13_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2312 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2313 				enum PP_OD_DPM_TABLE_COMMAND type,
2314 				long input[], uint32_t size)
2315 {
2316 	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2317 	int ret = 0;
2318 
2319 	/* Only allowed in manual mode */
2320 	if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2321 		return -EINVAL;
2322 
2323 	switch (type) {
2324 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
2325 		if (size != 2) {
2326 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2327 			return -EINVAL;
2328 		}
2329 
2330 		if (input[0] == 0) {
2331 			if (input[1] < smu->gfx_default_hard_min_freq) {
2332 				dev_warn(smu->adev->dev,
2333 					 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2334 					 input[1], smu->gfx_default_hard_min_freq);
2335 				return -EINVAL;
2336 			}
2337 			smu->gfx_actual_hard_min_freq = input[1];
2338 		} else if (input[0] == 1) {
2339 			if (input[1] > smu->gfx_default_soft_max_freq) {
2340 				dev_warn(smu->adev->dev,
2341 					 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2342 					 input[1], smu->gfx_default_soft_max_freq);
2343 				return -EINVAL;
2344 			}
2345 			smu->gfx_actual_soft_max_freq = input[1];
2346 		} else {
2347 			return -EINVAL;
2348 		}
2349 		break;
2350 	case PP_OD_RESTORE_DEFAULT_TABLE:
2351 		if (size != 0) {
2352 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2353 			return -EINVAL;
2354 		}
2355 		smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2356 		smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2357 		break;
2358 	case PP_OD_COMMIT_DPM_TABLE:
2359 		if (size != 0) {
2360 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
2361 			return -EINVAL;
2362 		}
2363 		if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2364 			dev_err(smu->adev->dev,
2365 				"The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2366 				smu->gfx_actual_hard_min_freq,
2367 				smu->gfx_actual_soft_max_freq);
2368 			return -EINVAL;
2369 		}
2370 
2371 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2372 						      smu->gfx_actual_hard_min_freq,
2373 						      NULL);
2374 		if (ret) {
2375 			dev_err(smu->adev->dev, "Set hard min sclk failed!");
2376 			return ret;
2377 		}
2378 
2379 		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2380 						      smu->gfx_actual_soft_max_freq,
2381 						      NULL);
2382 		if (ret) {
2383 			dev_err(smu->adev->dev, "Set soft max sclk failed!");
2384 			return ret;
2385 		}
2386 		break;
2387 	default:
2388 		return -ENOSYS;
2389 	}
2390 
2391 	return ret;
2392 }
2393 
smu_v13_0_set_default_dpm_tables(struct smu_context * smu)2394 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2395 {
2396 	struct smu_table_context *smu_table = &smu->smu_table;
2397 
2398 	return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2399 				    smu_table->clocks_table, false);
2400 }
2401 
smu_v13_0_set_smu_mailbox_registers(struct smu_context * smu)2402 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2403 {
2404 	struct amdgpu_device *adev = smu->adev;
2405 
2406 	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2407 	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2408 	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2409 }
2410 
smu_v13_0_mode1_reset(struct smu_context * smu)2411 int smu_v13_0_mode1_reset(struct smu_context *smu)
2412 {
2413 	int ret = 0;
2414 
2415 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2416 	if (!ret)
2417 		msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2418 
2419 	return ret;
2420 }
2421 
smu_v13_0_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)2422 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2423 				     uint32_t pcie_gen_cap,
2424 				     uint32_t pcie_width_cap)
2425 {
2426 	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2427 	struct smu_13_0_pcie_table *pcie_table =
2428 				&dpm_context->dpm_tables.pcie_table;
2429 	int num_of_levels = pcie_table->num_of_link_levels;
2430 	uint32_t smu_pcie_arg;
2431 	int ret, i;
2432 
2433 	if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2434 		if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2435 			pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2436 
2437 		if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2438 			pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2439 
2440 		/* Force all levels to use the same settings */
2441 		for (i = 0; i < num_of_levels; i++) {
2442 			pcie_table->pcie_gen[i] = pcie_gen_cap;
2443 			pcie_table->pcie_lane[i] = pcie_width_cap;
2444 		}
2445 	} else {
2446 		for (i = 0; i < num_of_levels; i++) {
2447 			if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2448 				pcie_table->pcie_gen[i] = pcie_gen_cap;
2449 			if (pcie_table->pcie_lane[i] > pcie_width_cap)
2450 				pcie_table->pcie_lane[i] = pcie_width_cap;
2451 		}
2452 	}
2453 
2454 	for (i = 0; i < num_of_levels; i++) {
2455 		smu_pcie_arg = i << 16;
2456 		smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2457 		smu_pcie_arg |= pcie_table->pcie_lane[i];
2458 
2459 		ret = smu_cmn_send_smc_msg_with_param(smu,
2460 						      SMU_MSG_OverridePcieParameters,
2461 						      smu_pcie_arg,
2462 						      NULL);
2463 		if (ret)
2464 			return ret;
2465 	}
2466 
2467 	return 0;
2468 }
2469