1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 enum ftr_type {
19 FTR_EXACT, /* Use a predefined safe value */
20 FTR_LOWER_SAFE, /* Smaller value is safe */
21 FTR_HIGHER_SAFE, /* Bigger value is safe */
22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
23 FTR_END, /* Mark the last ftr bits */
24 };
25
26 #define FTR_SIGNED true /* Value should be treated as signed */
27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
28
29 struct reg_ftr_bits {
30 char *name;
31 bool sign;
32 enum ftr_type type;
33 uint8_t shift;
34 uint64_t mask;
35 /*
36 * For FTR_EXACT, safe_val is used as the exact safe value.
37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
38 */
39 int64_t safe_val;
40 };
41
42 struct test_feature_reg {
43 uint32_t reg;
44 const struct reg_ftr_bits *ftr_bits;
45 };
46
47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
48 { \
49 .name = #NAME, \
50 .sign = SIGNED, \
51 .type = TYPE, \
52 .shift = SHIFT, \
53 .mask = MASK, \
54 .safe_val = SAFE_VAL, \
55 }
56
57 #define REG_FTR_BITS(type, reg, field, safe_val) \
58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
59 reg##_##field##_MASK, safe_val)
60
61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
63 reg##_##field##_MASK, safe_val)
64
65 #define REG_FTR_END \
66 { \
67 .type = FTR_END, \
68 }
69
70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
75 REG_FTR_END,
76 };
77
78 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
79 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3),
80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8),
81 REG_FTR_END,
82 };
83
84 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
100 REG_FTR_END,
101 };
102
103 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
116 REG_FTR_END,
117 };
118
119 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
123 REG_FTR_END,
124 };
125
126 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
131 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),
132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1),
133 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1),
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1),
135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1),
136 REG_FTR_END,
137 };
138
139 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
143 REG_FTR_END,
144 };
145
146 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
149 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1),
150 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1),
151 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1),
152 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
153 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
154 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
157 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
158 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
159 REG_FTR_END,
160 };
161
162 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
166 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
168 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
169 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
170 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
171 REG_FTR_END,
172 };
173
174 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
175 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
176 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
182 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
183 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
184 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
185 REG_FTR_END,
186 };
187
188 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
189 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
190 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
195 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
196 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
197 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
198 REG_FTR_END,
199 };
200
201 #define TEST_REG(id, table) \
202 { \
203 .reg = id, \
204 .ftr_bits = &((table)[0]), \
205 }
206
207 static struct test_feature_reg test_regs[] = {
208 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
209 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
210 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
211 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
212 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
213 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
214 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1),
215 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
216 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
217 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
218 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
219 };
220
221 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
222
guest_code(void)223 static void guest_code(void)
224 {
225 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
226 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
227 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
228 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
229 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
230 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
231 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
232 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
233 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
234 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
235 GUEST_REG_SYNC(SYS_CTR_EL0);
236 GUEST_REG_SYNC(SYS_MIDR_EL1);
237 GUEST_REG_SYNC(SYS_REVIDR_EL1);
238 GUEST_REG_SYNC(SYS_AIDR_EL1);
239
240 GUEST_DONE();
241 }
242
243 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)244 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
245 {
246 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
247
248 if (ftr_bits->sign == FTR_UNSIGNED) {
249 switch (ftr_bits->type) {
250 case FTR_EXACT:
251 ftr = ftr_bits->safe_val;
252 break;
253 case FTR_LOWER_SAFE:
254 if (ftr > ftr_bits->safe_val)
255 ftr--;
256 break;
257 case FTR_HIGHER_SAFE:
258 if (ftr < ftr_max)
259 ftr++;
260 break;
261 case FTR_HIGHER_OR_ZERO_SAFE:
262 if (ftr == ftr_max)
263 ftr = 0;
264 else if (ftr != 0)
265 ftr++;
266 break;
267 default:
268 break;
269 }
270 } else if (ftr != ftr_max) {
271 switch (ftr_bits->type) {
272 case FTR_EXACT:
273 ftr = ftr_bits->safe_val;
274 break;
275 case FTR_LOWER_SAFE:
276 if (ftr > ftr_bits->safe_val)
277 ftr--;
278 break;
279 case FTR_HIGHER_SAFE:
280 if (ftr < ftr_max - 1)
281 ftr++;
282 break;
283 case FTR_HIGHER_OR_ZERO_SAFE:
284 if (ftr != 0 && ftr != ftr_max - 1)
285 ftr++;
286 break;
287 default:
288 break;
289 }
290 }
291
292 return ftr;
293 }
294
295 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)296 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
297 {
298 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
299
300 if (ftr_bits->sign == FTR_UNSIGNED) {
301 switch (ftr_bits->type) {
302 case FTR_EXACT:
303 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
304 break;
305 case FTR_LOWER_SAFE:
306 ftr++;
307 break;
308 case FTR_HIGHER_SAFE:
309 ftr--;
310 break;
311 case FTR_HIGHER_OR_ZERO_SAFE:
312 if (ftr == 0)
313 ftr = ftr_max;
314 else
315 ftr--;
316 break;
317 default:
318 break;
319 }
320 } else if (ftr != ftr_max) {
321 switch (ftr_bits->type) {
322 case FTR_EXACT:
323 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
324 break;
325 case FTR_LOWER_SAFE:
326 ftr++;
327 break;
328 case FTR_HIGHER_SAFE:
329 ftr--;
330 break;
331 case FTR_HIGHER_OR_ZERO_SAFE:
332 if (ftr == 0)
333 ftr = ftr_max - 1;
334 else
335 ftr--;
336 break;
337 default:
338 break;
339 }
340 } else {
341 ftr = 0;
342 }
343
344 return ftr;
345 }
346
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)347 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
348 const struct reg_ftr_bits *ftr_bits)
349 {
350 uint8_t shift = ftr_bits->shift;
351 uint64_t mask = ftr_bits->mask;
352 uint64_t val, new_val, ftr;
353
354 val = vcpu_get_reg(vcpu, reg);
355 ftr = (val & mask) >> shift;
356
357 ftr = get_safe_value(ftr_bits, ftr);
358
359 ftr <<= shift;
360 val &= ~mask;
361 val |= ftr;
362
363 vcpu_set_reg(vcpu, reg, val);
364 new_val = vcpu_get_reg(vcpu, reg);
365 TEST_ASSERT_EQ(new_val, val);
366
367 return new_val;
368 }
369
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)370 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
371 const struct reg_ftr_bits *ftr_bits)
372 {
373 uint8_t shift = ftr_bits->shift;
374 uint64_t mask = ftr_bits->mask;
375 uint64_t val, old_val, ftr;
376 int r;
377
378 val = vcpu_get_reg(vcpu, reg);
379 ftr = (val & mask) >> shift;
380
381 ftr = get_invalid_value(ftr_bits, ftr);
382
383 old_val = val;
384 ftr <<= shift;
385 val &= ~mask;
386 val |= ftr;
387
388 r = __vcpu_set_reg(vcpu, reg, val);
389 TEST_ASSERT(r < 0 && errno == EINVAL,
390 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
391
392 val = vcpu_get_reg(vcpu, reg);
393 TEST_ASSERT_EQ(val, old_val);
394 }
395
396 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
397
398 #define encoding_to_range_idx(encoding) \
399 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \
400 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \
401 sys_reg_Op2(encoding))
402
403
test_vm_ftr_id_regs(struct kvm_vcpu * vcpu,bool aarch64_only)404 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
405 {
406 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
407 struct reg_mask_range range = {
408 .addr = (__u64)masks,
409 };
410 int ret;
411
412 /* KVM should return error when reserved field is not zero */
413 range.reserved[0] = 1;
414 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
415 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
416
417 /* Get writable masks for feature ID registers */
418 memset(range.reserved, 0, sizeof(range.reserved));
419 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
420
421 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
422 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
423 uint32_t reg_id = test_regs[i].reg;
424 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
425 int idx;
426
427 /* Get the index to masks array for the idreg */
428 idx = encoding_to_range_idx(reg_id);
429
430 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
431 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
432 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
433 ksft_test_result_skip("%s on AARCH64 only system\n",
434 ftr_bits[j].name);
435 continue;
436 }
437
438 /* Make sure the feature field is writable */
439 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
440
441 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
442
443 test_reg_vals[idx] = test_reg_set_success(vcpu, reg,
444 &ftr_bits[j]);
445
446 ksft_test_result_pass("%s\n", ftr_bits[j].name);
447 }
448 }
449 }
450
451 #define MPAM_IDREG_TEST 6
test_user_set_mpam_reg(struct kvm_vcpu * vcpu)452 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
453 {
454 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
455 struct reg_mask_range range = {
456 .addr = (__u64)masks,
457 };
458 uint64_t val;
459 int idx, err;
460
461 /*
462 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero,
463 * check that if it can be set to 1, (i.e. it is supported by the
464 * hardware), that it can't be set to other values.
465 */
466
467 /* Get writable masks for feature ID registers */
468 memset(range.reserved, 0, sizeof(range.reserved));
469 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
470
471 /* Writeable? Nothing to test! */
472 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1);
473 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) {
474 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n");
475 return;
476 }
477
478 /* Get the id register value */
479 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
480
481 /* Try to set MPAM=0. This should always be possible. */
482 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
483 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0);
484 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
485 if (err)
486 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n");
487 else
488 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n");
489
490 /* Try to set MPAM=1 */
491 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
492 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1);
493 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
494 if (err)
495 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n");
496 else
497 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n");
498
499 /* Try to set MPAM=2 */
500 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
501 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2);
502 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
503 if (err)
504 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n");
505 else
506 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n");
507
508 /* And again for ID_AA64PFR1_EL1.MPAM_frac */
509 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
510 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) {
511 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n");
512 return;
513 }
514
515 /* Get the id register value */
516 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
517
518 /* Try to set MPAM_frac=0. This should always be possible. */
519 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
520 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0);
521 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
522 if (err)
523 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n");
524 else
525 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n");
526
527 /* Try to set MPAM_frac=1 */
528 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
529 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1);
530 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
531 if (err)
532 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n");
533 else
534 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n");
535
536 /* Try to set MPAM_frac=2 */
537 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
538 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2);
539 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
540 if (err)
541 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n");
542 else
543 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n");
544 }
545
test_guest_reg_read(struct kvm_vcpu * vcpu)546 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
547 {
548 bool done = false;
549 struct ucall uc;
550
551 while (!done) {
552 vcpu_run(vcpu);
553
554 switch (get_ucall(vcpu, &uc)) {
555 case UCALL_ABORT:
556 REPORT_GUEST_ASSERT(uc);
557 break;
558 case UCALL_SYNC:
559 /* Make sure the written values are seen by guest */
560 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])],
561 uc.args[3]);
562 break;
563 case UCALL_DONE:
564 done = true;
565 break;
566 default:
567 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
568 }
569 }
570 }
571
572 /* Politely lifted from arch/arm64/include/asm/cache.h */
573 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
574 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
575 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
576 #define CLIDR_CTYPE(clidr, level) \
577 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
578
test_clidr(struct kvm_vcpu * vcpu)579 static void test_clidr(struct kvm_vcpu *vcpu)
580 {
581 uint64_t clidr;
582 int level;
583
584 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
585
586 /* find the first empty level in the cache hierarchy */
587 for (level = 1; level < 7; level++) {
588 if (!CLIDR_CTYPE(clidr, level))
589 break;
590 }
591
592 /*
593 * If you have a mind-boggling 7 levels of cache, congratulations, you
594 * get to fix this.
595 */
596 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy");
597
598 /* stick in a unified cache level */
599 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level);
600
601 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr);
602 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr;
603 }
604
test_ctr(struct kvm_vcpu * vcpu)605 static void test_ctr(struct kvm_vcpu *vcpu)
606 {
607 u64 ctr;
608
609 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
610 ctr &= ~CTR_EL0_DIC_MASK;
611 if (ctr & CTR_EL0_IminLine_MASK)
612 ctr--;
613
614 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr);
615 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr;
616 }
617
test_id_reg(struct kvm_vcpu * vcpu,u32 id)618 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id)
619 {
620 u64 val;
621
622 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id));
623 val++;
624 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val);
625 test_reg_vals[encoding_to_range_idx(id)] = val;
626 }
627
test_vcpu_ftr_id_regs(struct kvm_vcpu * vcpu)628 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
629 {
630 test_clidr(vcpu);
631 test_ctr(vcpu);
632
633 test_id_reg(vcpu, SYS_MPIDR_EL1);
634 ksft_test_result_pass("%s\n", __func__);
635 }
636
test_vcpu_non_ftr_id_regs(struct kvm_vcpu * vcpu)637 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu)
638 {
639 test_id_reg(vcpu, SYS_MIDR_EL1);
640 test_id_reg(vcpu, SYS_REVIDR_EL1);
641 test_id_reg(vcpu, SYS_AIDR_EL1);
642
643 ksft_test_result_pass("%s\n", __func__);
644 }
645
test_assert_id_reg_unchanged(struct kvm_vcpu * vcpu,uint32_t encoding)646 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
647 {
648 size_t idx = encoding_to_range_idx(encoding);
649 uint64_t observed;
650
651 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
652 TEST_ASSERT_EQ(test_reg_vals[idx], observed);
653 }
654
test_reset_preserves_id_regs(struct kvm_vcpu * vcpu)655 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)
656 {
657 /*
658 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an
659 * architectural reset of the vCPU.
660 */
661 aarch64_vcpu_setup(vcpu, NULL);
662
663 for (int i = 0; i < ARRAY_SIZE(test_regs); i++)
664 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg);
665
666 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1);
667 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1);
668 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0);
669 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1);
670 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1);
671 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1);
672
673 ksft_test_result_pass("%s\n", __func__);
674 }
675
main(void)676 int main(void)
677 {
678 struct kvm_vcpu *vcpu;
679 struct kvm_vm *vm;
680 bool aarch64_only;
681 uint64_t val, el0;
682 int test_cnt;
683
684 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
685 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS));
686
687 vm = vm_create(1);
688 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0);
689 vcpu = vm_vcpu_add(vm, 0, guest_code);
690
691 /* Check for AARCH64 only system */
692 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
693 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
694 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP);
695
696 ksft_print_header();
697
698 test_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
699 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
700 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
701 ARRAY_SIZE(ftr_id_aa64pfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr0_el1) +
702 ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr2_el1) +
703 ARRAY_SIZE(ftr_id_aa64zfr0_el1) - ARRAY_SIZE(test_regs) + 3 +
704 MPAM_IDREG_TEST;
705
706 ksft_set_plan(test_cnt);
707
708 test_vm_ftr_id_regs(vcpu, aarch64_only);
709 test_vcpu_ftr_id_regs(vcpu);
710 test_vcpu_non_ftr_id_regs(vcpu);
711 test_user_set_mpam_reg(vcpu);
712
713 test_guest_reg_read(vcpu);
714
715 test_reset_preserves_id_regs(vcpu);
716
717 kvm_vm_free(vm);
718
719 ksft_finished();
720 }
721