1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2022 Intel Corporation
4 //
5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
6 //
7
8 /*
9 * Hardware interface for audio DSP on Meteorlake.
10 */
11
12 #include <linux/debugfs.h>
13 #include <linux/firmware.h>
14 #include <linux/string_choices.h>
15 #include <sound/sof/ipc4/header.h>
16 #include <trace/events/sof_intel.h>
17 #include "../ipc4-priv.h"
18 #include "../ops.h"
19 #include "hda.h"
20 #include "hda-ipc.h"
21 #include "../sof-audio.h"
22 #include "mtl.h"
23 #include "telemetry.h"
24
25 static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = {
26 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
27 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
29 {"fw_regs", HDA_DSP_BAR, MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
30 };
31
mtl_ipc_host_done(struct snd_sof_dev * sdev)32 static void mtl_ipc_host_done(struct snd_sof_dev *sdev)
33 {
34 /*
35 * clear busy interrupt to tell dsp controller this interrupt has been accepted,
36 * not trigger it again
37 */
38 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR,
39 MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY);
40 /*
41 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp
42 */
43 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA,
44 MTL_DSP_REG_HFIPCXTDA_BUSY, 0);
45 }
46
mtl_ipc_dsp_done(struct snd_sof_dev * sdev)47 static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev)
48 {
49 /*
50 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it,
51 * don't send more reply to host
52 */
53 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA,
54 MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE);
55
56 /* unmask Done interrupt */
57 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
58 MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE);
59 }
60
61 /* Check if an IPC IRQ occurred */
mtl_dsp_check_ipc_irq(struct snd_sof_dev * sdev)62 bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev)
63 {
64 u32 irq_status;
65 u32 hfintipptr;
66
67 if (sdev->dspless_mode_selected)
68 return false;
69
70 /* read Interrupt IP Pointer */
71 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
72 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
73
74 trace_sof_intel_hda_irq_ipc_check(sdev, irq_status);
75
76 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC))
77 return true;
78
79 return false;
80 }
81 EXPORT_SYMBOL_NS(mtl_dsp_check_ipc_irq, "SND_SOC_SOF_INTEL_MTL");
82
83 /* Check if an SDW IRQ occurred */
mtl_dsp_check_sdw_irq(struct snd_sof_dev * sdev)84 static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
85 {
86 u32 irq_status;
87 u32 hfintipptr;
88
89 /* read Interrupt IP Pointer */
90 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
91 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS);
92
93 if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW))
94 return true;
95
96 return false;
97 }
98
mtl_ipc_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)99 static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
100 {
101 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
102 struct sof_ipc4_msg *msg_data = msg->msg_data;
103
104 if (hda_ipc4_tx_is_busy(sdev)) {
105 hdev->delayed_ipc_tx_msg = msg;
106 return 0;
107 }
108
109 hdev->delayed_ipc_tx_msg = NULL;
110
111 /* send the message via mailbox */
112 if (msg_data->data_size)
113 sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,
114 msg_data->data_size);
115
116 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY,
117 msg_data->extension);
118 snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR,
119 msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY);
120
121 hda_dsp_ipc4_schedule_d0i3_work(hdev, msg);
122
123 return 0;
124 }
125
mtl_enable_ipc_interrupts(struct snd_sof_dev * sdev)126 void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev)
127 {
128 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
129 const struct sof_intel_dsp_desc *chip = hda->desc;
130
131 if (sdev->dspless_mode_selected)
132 return;
133
134 /* enable IPC DONE and BUSY interrupts */
135 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
136 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE,
137 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE);
138 }
139
mtl_disable_ipc_interrupts(struct snd_sof_dev * sdev)140 void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev)
141 {
142 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
143 const struct sof_intel_dsp_desc *chip = hda->desc;
144
145 if (sdev->dspless_mode_selected)
146 return;
147
148 /* disable IPC DONE and BUSY interrupts */
149 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
150 MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0);
151 }
152 EXPORT_SYMBOL_NS(mtl_disable_ipc_interrupts, "SND_SOC_SOF_INTEL_MTL");
153
mtl_enable_sdw_irq(struct snd_sof_dev * sdev,bool enable)154 static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
155 {
156 u32 hipcie;
157 u32 mask;
158 u32 val;
159 int ret;
160
161 if (sdev->dspless_mode_selected)
162 return;
163
164 /* Enable/Disable SoundWire interrupt */
165 mask = MTL_DSP_REG_HfSNDWIE_IE_MASK;
166 if (enable)
167 val = mask;
168 else
169 val = 0;
170
171 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val);
172
173 /* check if operation was successful */
174 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,
175 (hipcie & mask) == val,
176 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
177 if (ret < 0)
178 dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n",
179 str_enable_disable(enable));
180 }
181
mtl_enable_interrupts(struct snd_sof_dev * sdev,bool enable)182 int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable)
183 {
184 u32 hfintipptr;
185 u32 irqinten;
186 u32 hipcie;
187 u32 mask;
188 u32 val;
189 int ret;
190
191 if (sdev->dspless_mode_selected)
192 return 0;
193
194 /* read Interrupt IP Pointer */
195 hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;
196
197 /* Enable/Disable Host IPC and SOUNDWIRE */
198 mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;
199 if (enable)
200 val = mask;
201 else
202 val = 0;
203
204 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val);
205
206 /* check if operation was successful */
207 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,
208 (irqinten & mask) == val,
209 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
210 if (ret < 0) {
211 dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n",
212 str_enable_disable(enable));
213 return ret;
214 }
215
216 /* Enable/Disable Host IPC interrupt*/
217 mask = MTL_DSP_REG_HfHIPCIE_IE_MASK;
218 if (enable)
219 val = mask;
220 else
221 val = 0;
222
223 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val);
224
225 /* check if operation was successful */
226 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,
227 (hipcie & mask) == val,
228 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);
229 if (ret < 0) {
230 dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n",
231 str_enable_disable(enable));
232 return ret;
233 }
234
235 return ret;
236 }
237 EXPORT_SYMBOL_NS(mtl_enable_interrupts, "SND_SOC_SOF_INTEL_MTL");
238
239 /* pre fw run operations */
mtl_dsp_pre_fw_run(struct snd_sof_dev * sdev)240 static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev)
241 {
242 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
243 u32 dsphfpwrsts;
244 u32 dsphfdsscs;
245 u32 cpa;
246 u32 pgs;
247 int ret;
248 u32 dsppwrctl;
249 u32 dsppwrsts;
250 const struct sof_intel_dsp_desc *chip;
251
252 chip = get_chip_info(sdev->pdata);
253 if (chip->hw_ip_version > SOF_INTEL_ACE_2_0) {
254 dsppwrctl = PTL_HFPWRCTL2;
255 dsppwrsts = PTL_HFPWRSTS2;
256 } else {
257 dsppwrctl = MTL_HFPWRCTL;
258 dsppwrsts = MTL_HFPWRSTS;
259 }
260
261 /* Set the DSP subsystem power on */
262 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
263 MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK);
264
265 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
266 usleep_range(1000, 1010);
267
268 /* poll with timeout to check if operation successful */
269 cpa = MTL_HFDSSCS_CPA_MASK;
270 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
271 (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
272 HDA_DSP_RESET_TIMEOUT_US);
273 if (ret < 0) {
274 dev_err(sdev->dev, "failed to enable DSP subsystem\n");
275 return ret;
276 }
277
278 /* Power up gated-DSP-0 domain in order to access the DSP shim register block. */
279 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, dsppwrctl,
280 MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG);
281
282 usleep_range(1000, 1010);
283
284 /* poll with timeout to check if operation successful */
285 pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;
286 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, dsppwrsts, dsphfpwrsts,
287 (dsphfpwrsts & pgs) == pgs,
288 HDA_DSP_REG_POLL_INTERVAL_US,
289 HDA_DSP_RESET_TIMEOUT_US);
290 if (ret < 0)
291 dev_err(sdev->dev, "failed to power up gated DSP domain\n");
292
293 /* if SoundWire is used, make sure it is not power-gated */
294 if (hdev->info.handle && hdev->info.link_mask > 0)
295 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,
296 MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1));
297
298 return ret;
299 }
300
mtl_dsp_post_fw_run(struct snd_sof_dev * sdev)301 static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
302 {
303 int ret;
304
305 if (sdev->first_boot) {
306 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
307
308 ret = hda_sdw_startup(sdev);
309 if (ret < 0) {
310 dev_err(sdev->dev, "could not startup SoundWire links\n");
311 return ret;
312 }
313
314 /* Check if IMR boot is usable */
315 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) {
316 hdev->imrboot_supported = true;
317 debugfs_create_bool("skip_imr_boot",
318 0644, sdev->debugfs_root,
319 &hdev->skip_imr_boot);
320 }
321 }
322
323 hda_sdw_int_enable(sdev, true);
324 return 0;
325 }
326
mtl_dsp_dump(struct snd_sof_dev * sdev,u32 flags)327 static void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
328 {
329 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
330 u32 fwsts;
331 u32 fwlec;
332
333 hda_dsp_get_state(sdev, level);
334 fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);
335 fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR);
336
337 if (fwsts != 0xffffffff)
338 dev_err(sdev->dev, "Firmware state: %#x, status/error code: %#x\n",
339 fwsts, fwlec);
340
341 sof_ipc4_intel_dump_telemetry_state(sdev, flags);
342 }
343
mtl_dsp_primary_core_is_enabled(struct snd_sof_dev * sdev)344 static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev)
345 {
346 int val;
347
348 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE);
349 if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK)
350 return true;
351
352 return false;
353 }
354
mtl_dsp_core_power_up(struct snd_sof_dev * sdev,int core)355 static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core)
356 {
357 unsigned int cpa;
358 u32 dspcxctl;
359 int ret;
360
361 /* Only the primary core can be powered up by the host */
362 if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev))
363 return 0;
364
365 /* Program the owner of the IP & shim registers (10: Host CPU) */
366 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
367 MTL_DSP2CXCTL_PRIMARY_CORE_OSEL,
368 0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT);
369
370 /* enable SPA bit */
371 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
372 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK,
373 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK);
374
375 /* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */
376 usleep_range(1000, 1010);
377
378 /* poll with timeout to check if operation successful */
379 cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK;
380 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
381 (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,
382 HDA_DSP_RESET_TIMEOUT_US);
383 if (ret < 0) {
384 dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n",
385 __func__);
386 return ret;
387 }
388
389 /* set primary core mask and refcount to 1 */
390 sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE);
391 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1;
392
393 return 0;
394 }
395
mtl_dsp_core_power_down(struct snd_sof_dev * sdev,int core)396 static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core)
397 {
398 u32 dspcxctl;
399 int ret;
400
401 /* Only the primary core can be powered down by the host */
402 if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev))
403 return 0;
404
405 /* disable SPA bit */
406 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,
407 MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0);
408
409 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
410 usleep_range(1000, 1010);
411
412 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,
413 !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK),
414 HDA_DSP_REG_POLL_INTERVAL_US,
415 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
416 if (ret < 0) {
417 dev_err(sdev->dev, "failed to power down primary core\n");
418 return ret;
419 }
420
421 sdev->enabled_cores_mask = 0;
422 sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0;
423
424 return 0;
425 }
426
mtl_power_down_dsp(struct snd_sof_dev * sdev)427 int mtl_power_down_dsp(struct snd_sof_dev *sdev)
428 {
429 u32 dsphfdsscs, cpa;
430 int ret;
431
432 /* first power down core */
433 ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
434 if (ret) {
435 dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);
436 return ret;
437 }
438
439 /* Set the DSP subsystem power down */
440 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,
441 MTL_HFDSSCS_SPA_MASK, 0);
442
443 /* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */
444 usleep_range(1000, 1010);
445
446 /* poll with timeout to check if operation successful */
447 cpa = MTL_HFDSSCS_CPA_MASK;
448 dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);
449 return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,
450 (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,
451 HDA_DSP_RESET_TIMEOUT_US);
452 }
453 EXPORT_SYMBOL_NS(mtl_power_down_dsp, "SND_SOC_SOF_INTEL_MTL");
454
mtl_dsp_cl_init(struct snd_sof_dev * sdev,int stream_tag,bool imr_boot)455 int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
456 {
457 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
458 const struct sof_intel_dsp_desc *chip = hda->desc;
459 unsigned int status, target_status;
460 u32 ipc_hdr, flags;
461 char *dump_msg;
462 int ret;
463
464 /* step 1: purge FW request */
465 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
466 if (!imr_boot)
467 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
468
469 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
470
471 /* step 2: power up primary core */
472 ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
473 if (ret < 0) {
474 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
475 dev_err(sdev->dev, "dsp core 0/1 power up failed\n");
476 goto err;
477 }
478
479 dev_dbg(sdev->dev, "Primary core power up successful\n");
480
481 /* step 3: wait for IPC DONE bit from ROM */
482 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, chip->ipc_ack, status,
483 ((status & chip->ipc_ack_mask) == chip->ipc_ack_mask),
484 HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_INIT_TIMEOUT_US);
485 if (ret < 0) {
486 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
487 dev_err(sdev->dev, "timeout waiting for purge IPC done\n");
488 goto err;
489 }
490
491 /* set DONE bit to clear the reply IPC message */
492 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, chip->ipc_ack, chip->ipc_ack_mask,
493 chip->ipc_ack_mask);
494
495 /* step 4: enable interrupts */
496 ret = mtl_enable_interrupts(sdev, true);
497 if (ret < 0) {
498 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
499 dev_err(sdev->dev, "%s: failed to enable interrupts\n", __func__);
500 goto err;
501 }
502
503 mtl_enable_ipc_interrupts(sdev);
504
505 if (chip->rom_status_reg == MTL_DSP_ROM_STS) {
506 /*
507 * Workaround: when the ROM status register is pointing to
508 * the SRAM window (MTL_DSP_ROM_STS) the platform cannot catch
509 * ROM_INIT_DONE because of a very short timing window.
510 * Follow the recommendations and skip target state waiting.
511 */
512 return 0;
513 }
514
515 /*
516 * step 7:
517 * - Cold/Full boot: wait for ROM init to proceed to download the firmware
518 * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)
519 */
520 if (imr_boot)
521 target_status = FSR_STATE_FW_ENTERED;
522 else
523 target_status = FSR_STATE_INIT_DONE;
524
525 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
526 chip->rom_status_reg, status,
527 (FSR_TO_STATE_CODE(status) == target_status),
528 HDA_DSP_REG_POLL_INTERVAL_US,
529 chip->rom_init_timeout *
530 USEC_PER_MSEC);
531
532 if (!ret)
533 return 0;
534
535 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
536 dev_err(sdev->dev,
537 "%s: timeout with rom_status_reg (%#x) read\n",
538 __func__, chip->rom_status_reg);
539
540 err:
541 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL;
542
543 /* after max boot attempts make sure that the dump is printed */
544 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
545 flags &= ~SOF_DBG_DUMP_OPTIONAL;
546
547 dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d",
548 hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS);
549 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
550 mtl_enable_interrupts(sdev, false);
551 mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
552
553 kfree(dump_msg);
554 return ret;
555 }
556 EXPORT_SYMBOL_NS(mtl_dsp_cl_init, "SND_SOC_SOF_INTEL_MTL");
557
mtl_ipc_irq_thread(int irq,void * context)558 static irqreturn_t mtl_ipc_irq_thread(int irq, void *context)
559 {
560 struct sof_ipc4_msg notification_data = {{ 0 }};
561 struct snd_sof_dev *sdev = context;
562 bool ack_received = false;
563 bool ipc_irq = false;
564 u32 hipcida;
565 u32 hipctdr;
566
567 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
568 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
569
570 /* reply message from DSP */
571 if (hipcida & MTL_DSP_REG_HFIPCXIDA_DONE) {
572 /* DSP received the message */
573 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,
574 MTL_DSP_REG_HFIPCXCTL_DONE, 0);
575
576 mtl_ipc_dsp_done(sdev);
577
578 ipc_irq = true;
579 ack_received = true;
580 }
581
582 if (hipctdr & MTL_DSP_REG_HFIPCXTDR_BUSY) {
583 /* Message from DSP (reply or notification) */
584 u32 extension = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
585 u32 primary = hipctdr & MTL_DSP_REG_HFIPCXTDR_MSG_MASK;
586
587 /*
588 * ACE fw sends a new fw ipc message to host to
589 * notify the status of the last host ipc message
590 */
591 if (primary & SOF_IPC4_MSG_DIR_MASK) {
592 /* Reply received */
593 if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
594 struct sof_ipc4_msg *data = sdev->ipc->msg.reply_data;
595
596 data->primary = primary;
597 data->extension = extension;
598
599 spin_lock_irq(&sdev->ipc_lock);
600
601 snd_sof_ipc_get_reply(sdev);
602 mtl_ipc_host_done(sdev);
603 snd_sof_ipc_reply(sdev, data->primary);
604
605 spin_unlock_irq(&sdev->ipc_lock);
606 } else {
607 dev_dbg_ratelimited(sdev->dev,
608 "IPC reply before FW_READY: %#x|%#x\n",
609 primary, extension);
610 }
611 } else {
612 /* Notification received */
613 notification_data.primary = primary;
614 notification_data.extension = extension;
615
616 sdev->ipc->msg.rx_data = ¬ification_data;
617 snd_sof_ipc_msgs_rx(sdev);
618 sdev->ipc->msg.rx_data = NULL;
619
620 mtl_ipc_host_done(sdev);
621 }
622
623 ipc_irq = true;
624 }
625
626 if (!ipc_irq) {
627 /* This interrupt is not shared so no need to return IRQ_NONE. */
628 dev_dbg_ratelimited(sdev->dev, "nothing to do in IPC IRQ thread\n");
629 }
630
631 if (ack_received) {
632 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
633
634 if (hdev->delayed_ipc_tx_msg)
635 mtl_ipc_send_msg(sdev, hdev->delayed_ipc_tx_msg);
636 }
637
638 return IRQ_HANDLED;
639 }
640
mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev * sdev)641 static int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
642 {
643 return MTL_DSP_MBOX_UPLINK_OFFSET;
644 }
645
mtl_dsp_ipc_get_window_offset(struct snd_sof_dev * sdev,u32 id)646 static int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
647 {
648 return MTL_SRAM_WINDOW_OFFSET(id);
649 }
650
mtl_ipc_dump(struct snd_sof_dev * sdev)651 static void mtl_ipc_dump(struct snd_sof_dev *sdev)
652 {
653 u32 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl;
654
655 hipcidr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR);
656 hipcidd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY);
657 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA);
658 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR);
659 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDDY);
660 hipctda = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA);
661 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL);
662
663 dev_err(sdev->dev,
664 "Host IPC initiator: %#x|%#x|%#x, target: %#x|%#x|%#x, ctl: %#x\n",
665 hipcidr, hipcidd, hipcida, hipctdr, hipctdd, hipctda, hipcctl);
666 }
667
mtl_dsp_disable_interrupts(struct snd_sof_dev * sdev)668 static int mtl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
669 {
670 mtl_enable_sdw_irq(sdev, false);
671 mtl_disable_ipc_interrupts(sdev);
672 return mtl_enable_interrupts(sdev, false);
673 }
674
mtl_dsp_core_get(struct snd_sof_dev * sdev,int core)675 static int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core)
676 {
677 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
678
679 if (core == SOF_DSP_PRIMARY_CORE)
680 return mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);
681
682 if (pm_ops->set_core_state)
683 return pm_ops->set_core_state(sdev, core, true);
684
685 return 0;
686 }
687
mtl_dsp_core_put(struct snd_sof_dev * sdev,int core)688 static int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core)
689 {
690 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
691 int ret;
692
693 if (pm_ops->set_core_state) {
694 ret = pm_ops->set_core_state(sdev, core, false);
695 if (ret < 0)
696 return ret;
697 }
698
699 if (core == SOF_DSP_PRIMARY_CORE)
700 return mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);
701
702 return 0;
703 }
704
sof_mtl_set_ops(struct snd_sof_dev * sdev,struct snd_sof_dsp_ops * dsp_ops)705 int sof_mtl_set_ops(struct snd_sof_dev *sdev, struct snd_sof_dsp_ops *dsp_ops)
706 {
707 struct sof_ipc4_fw_data *ipc4_data;
708
709 /* common defaults */
710 memcpy(dsp_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
711
712 /* shutdown */
713 dsp_ops->shutdown = hda_dsp_shutdown;
714
715 /* doorbell */
716 dsp_ops->irq_thread = mtl_ipc_irq_thread;
717
718 /* ipc */
719 dsp_ops->send_msg = mtl_ipc_send_msg;
720 dsp_ops->get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
721 dsp_ops->get_window_offset = mtl_dsp_ipc_get_window_offset;
722
723 /* debug */
724 dsp_ops->debug_map = mtl_dsp_debugfs;
725 dsp_ops->debug_map_count = ARRAY_SIZE(mtl_dsp_debugfs);
726 dsp_ops->dbg_dump = mtl_dsp_dump;
727 dsp_ops->ipc_dump = mtl_ipc_dump;
728
729 /* pre/post fw run */
730 dsp_ops->pre_fw_run = mtl_dsp_pre_fw_run;
731 dsp_ops->post_fw_run = mtl_dsp_post_fw_run;
732
733 /* parse platform specific extended manifest */
734 dsp_ops->parse_platform_ext_manifest = NULL;
735
736 /* dsp core get/put */
737 dsp_ops->core_get = mtl_dsp_core_get;
738 dsp_ops->core_put = mtl_dsp_core_put;
739
740 sdev->private = kzalloc(sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
741 if (!sdev->private)
742 return -ENOMEM;
743
744 ipc4_data = sdev->private;
745 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
746
747 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
748
749 ipc4_data->fw_context_save = true;
750
751 /* External library loading support */
752 ipc4_data->load_library = hda_dsp_ipc4_load_library;
753
754 dsp_ops->set_power_state = hda_dsp_set_power_state_ipc4;
755
756 /* set DAI ops */
757 hda_set_dai_drv_ops(sdev, dsp_ops);
758
759 return 0;
760 }
761 EXPORT_SYMBOL_NS(sof_mtl_set_ops, "SND_SOC_SOF_INTEL_MTL");
762
763 const struct sof_intel_dsp_desc mtl_chip_info = {
764 .cores_num = 3,
765 .init_core_mask = BIT(0),
766 .host_managed_cores_mask = BIT(0),
767 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
768 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
769 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
770 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
771 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
772 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
773 .rom_init_timeout = 300,
774 .ssp_count = MTL_SSP_COUNT,
775 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
776 .sdw_shim_base = SDW_SHIM_BASE_ACE,
777 .sdw_alh_base = SDW_ALH_BASE_ACE,
778 .d0i3_offset = MTL_HDA_VS_D0I3C,
779 .read_sdw_lcount = hda_sdw_check_lcount_common,
780 .enable_sdw_irq = mtl_enable_sdw_irq,
781 .check_sdw_irq = mtl_dsp_check_sdw_irq,
782 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
783 .sdw_process_wakeen = hda_sdw_process_wakeen_common,
784 .check_ipc_irq = mtl_dsp_check_ipc_irq,
785 .cl_init = mtl_dsp_cl_init,
786 .power_down_dsp = mtl_power_down_dsp,
787 .disable_interrupts = mtl_dsp_disable_interrupts,
788 .hw_ip_version = SOF_INTEL_ACE_1_0,
789 };
790
791 const struct sof_intel_dsp_desc arl_s_chip_info = {
792 .cores_num = 2,
793 .init_core_mask = BIT(0),
794 .host_managed_cores_mask = BIT(0),
795 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
796 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
797 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
798 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
799 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
800 .rom_status_reg = MTL_DSP_REG_HFFLGPXQWY,
801 .rom_init_timeout = 300,
802 .ssp_count = MTL_SSP_COUNT,
803 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
804 .sdw_shim_base = SDW_SHIM_BASE_ACE,
805 .sdw_alh_base = SDW_ALH_BASE_ACE,
806 .d0i3_offset = MTL_HDA_VS_D0I3C,
807 .read_sdw_lcount = hda_sdw_check_lcount_common,
808 .enable_sdw_irq = mtl_enable_sdw_irq,
809 .check_sdw_irq = mtl_dsp_check_sdw_irq,
810 .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
811 .sdw_process_wakeen = hda_sdw_process_wakeen_common,
812 .check_ipc_irq = mtl_dsp_check_ipc_irq,
813 .cl_init = mtl_dsp_cl_init,
814 .power_down_dsp = mtl_power_down_dsp,
815 .disable_interrupts = mtl_dsp_disable_interrupts,
816 .hw_ip_version = SOF_INTEL_ACE_1_0,
817 };
818