1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
3 // Copyright 2018 Tempo Semiconductor, Inc.
4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
5
6 #include <linux/kernel.h>
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/regmap.h>
10 #include <linux/i2c.h>
11 #include <linux/err.h>
12 #include <linux/string.h>
13 #include <linux/string_choices.h>
14 #include <linux/module.h>
15 #include <linux/delay.h>
16 #include <linux/mutex.h>
17
18 #include <sound/tlv.h>
19 #include <sound/pcm_params.h>
20 #include <sound/pcm.h>
21 #include <sound/soc.h>
22 #include <sound/soc-dapm.h>
23
24 #include "tscs454.h"
25
26 static const unsigned int PLL_44_1K_RATE = (44100 * 256);
27
28 #define COEFF_SIZE 3
29 #define BIQUAD_COEFF_COUNT 5
30 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
31
32 #define COEFF_RAM_MAX_ADDR 0xcd
33 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
34 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
35
36 enum {
37 TSCS454_DAI1_ID,
38 TSCS454_DAI2_ID,
39 TSCS454_DAI3_ID,
40 TSCS454_DAI_COUNT,
41 };
42
43 struct pll {
44 int id;
45 unsigned int users;
46 struct mutex lock;
47 };
48
pll_init(struct pll * pll,int id)49 static inline void pll_init(struct pll *pll, int id)
50 {
51 pll->id = id;
52 mutex_init(&pll->lock);
53 }
54
55 struct internal_rate {
56 struct pll *pll;
57 };
58
59 struct aif {
60 unsigned int id;
61 bool provider;
62 struct pll *pll;
63 };
64
aif_init(struct aif * aif,unsigned int id)65 static inline void aif_init(struct aif *aif, unsigned int id)
66 {
67 aif->id = id;
68 }
69
70 struct coeff_ram {
71 u8 cache[COEFF_RAM_SIZE];
72 bool synced;
73 struct mutex lock;
74 };
75
init_coeff_ram_cache(u8 * cache)76 static inline void init_coeff_ram_cache(u8 *cache)
77 {
78 static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
79 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
80 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
81 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
82 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
83 int i;
84
85 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
86 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
87 }
88
coeff_ram_init(struct coeff_ram * ram)89 static inline void coeff_ram_init(struct coeff_ram *ram)
90 {
91 init_coeff_ram_cache(ram->cache);
92 mutex_init(&ram->lock);
93 }
94
95 struct aifs_status {
96 u8 streams;
97 };
98
set_aif_status_active(struct aifs_status * status,int aif_id,bool playback)99 static inline void set_aif_status_active(struct aifs_status *status,
100 int aif_id, bool playback)
101 {
102 u8 mask = 0x01 << (aif_id * 2 + !playback);
103
104 status->streams |= mask;
105 }
106
set_aif_status_inactive(struct aifs_status * status,int aif_id,bool playback)107 static inline void set_aif_status_inactive(struct aifs_status *status,
108 int aif_id, bool playback)
109 {
110 u8 mask = ~(0x01 << (aif_id * 2 + !playback));
111
112 status->streams &= mask;
113 }
114
aifs_active(struct aifs_status * status)115 static bool aifs_active(struct aifs_status *status)
116 {
117 return status->streams;
118 }
119
aif_active(struct aifs_status * status,int aif_id)120 static bool aif_active(struct aifs_status *status, int aif_id)
121 {
122 return (0x03 << aif_id * 2) & status->streams;
123 }
124
125 struct tscs454 {
126 struct regmap *regmap;
127 struct aif aifs[TSCS454_DAI_COUNT];
128
129 struct aifs_status aifs_status;
130 struct mutex aifs_status_lock;
131
132 struct pll pll1;
133 struct pll pll2;
134 struct internal_rate internal_rate;
135
136 struct coeff_ram dac_ram;
137 struct coeff_ram spk_ram;
138 struct coeff_ram sub_ram;
139
140 struct clk *sysclk;
141 int sysclk_src_id;
142 unsigned int bclk_freq;
143 };
144
145 struct coeff_ram_ctl {
146 unsigned int addr;
147 struct soc_bytes_ext bytes_ext;
148 };
149
150 static const struct reg_sequence tscs454_patch[] = {
151 /* Assign ASRC out of the box so DAI 1 just works */
152 { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
153 { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
154 { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
155 { R_TDMCTL0, FV_TDMMD_256 },
156 { VIRT_ADDR(0x0A, 0x13), 1 << 3 },
157 };
158
tscs454_volatile(struct device * dev,unsigned int reg)159 static bool tscs454_volatile(struct device *dev, unsigned int reg)
160 {
161 switch (reg) {
162 case R_PLLSTAT:
163
164 case R_SPKCRRDL:
165 case R_SPKCRRDM:
166 case R_SPKCRRDH:
167 case R_SPKCRS:
168
169 case R_DACCRRDL:
170 case R_DACCRRDM:
171 case R_DACCRRDH:
172 case R_DACCRS:
173
174 case R_SUBCRRDL:
175 case R_SUBCRRDM:
176 case R_SUBCRRDH:
177 case R_SUBCRS:
178 return true;
179 default:
180 return false;
181 }
182 }
183
tscs454_writable(struct device * dev,unsigned int reg)184 static bool tscs454_writable(struct device *dev, unsigned int reg)
185 {
186 switch (reg) {
187 case R_SPKCRRDL:
188 case R_SPKCRRDM:
189 case R_SPKCRRDH:
190
191 case R_DACCRRDL:
192 case R_DACCRRDM:
193 case R_DACCRRDH:
194
195 case R_SUBCRRDL:
196 case R_SUBCRRDM:
197 case R_SUBCRRDH:
198 return false;
199 default:
200 return true;
201 }
202 }
203
tscs454_readable(struct device * dev,unsigned int reg)204 static bool tscs454_readable(struct device *dev, unsigned int reg)
205 {
206 switch (reg) {
207 case R_SPKCRWDL:
208 case R_SPKCRWDM:
209 case R_SPKCRWDH:
210
211 case R_DACCRWDL:
212 case R_DACCRWDM:
213 case R_DACCRWDH:
214
215 case R_SUBCRWDL:
216 case R_SUBCRWDM:
217 case R_SUBCRWDH:
218 return false;
219 default:
220 return true;
221 }
222 }
223
tscs454_precious(struct device * dev,unsigned int reg)224 static bool tscs454_precious(struct device *dev, unsigned int reg)
225 {
226 switch (reg) {
227 case R_SPKCRWDL:
228 case R_SPKCRWDM:
229 case R_SPKCRWDH:
230 case R_SPKCRRDL:
231 case R_SPKCRRDM:
232 case R_SPKCRRDH:
233
234 case R_DACCRWDL:
235 case R_DACCRWDM:
236 case R_DACCRWDH:
237 case R_DACCRRDL:
238 case R_DACCRRDM:
239 case R_DACCRRDH:
240
241 case R_SUBCRWDL:
242 case R_SUBCRWDM:
243 case R_SUBCRWDH:
244 case R_SUBCRRDL:
245 case R_SUBCRRDM:
246 case R_SUBCRRDH:
247 return true;
248 default:
249 return false;
250 }
251 }
252
253 static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
254 .name = "Pages",
255 .range_min = VIRT_BASE,
256 .range_max = VIRT_ADDR(0xFE, 0x02),
257 .selector_reg = R_PAGESEL,
258 .selector_mask = 0xff,
259 .selector_shift = 0,
260 .window_start = 0,
261 .window_len = 0x100,
262 };
263
264 static struct regmap_config const tscs454_regmap_cfg = {
265 .reg_bits = 8,
266 .val_bits = 8,
267 .writeable_reg = tscs454_writable,
268 .readable_reg = tscs454_readable,
269 .volatile_reg = tscs454_volatile,
270 .precious_reg = tscs454_precious,
271 .ranges = &tscs454_regmap_range_cfg,
272 .num_ranges = 1,
273 .max_register = VIRT_ADDR(0xFE, 0x02),
274 .cache_type = REGCACHE_RBTREE,
275 };
276
tscs454_data_init(struct tscs454 * tscs454,struct i2c_client * i2c)277 static inline int tscs454_data_init(struct tscs454 *tscs454,
278 struct i2c_client *i2c)
279 {
280 int i;
281 int ret;
282
283 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
284 if (IS_ERR(tscs454->regmap)) {
285 ret = PTR_ERR(tscs454->regmap);
286 return ret;
287 }
288
289 for (i = 0; i < TSCS454_DAI_COUNT; i++)
290 aif_init(&tscs454->aifs[i], i);
291
292 mutex_init(&tscs454->aifs_status_lock);
293 pll_init(&tscs454->pll1, 1);
294 pll_init(&tscs454->pll2, 2);
295
296 coeff_ram_init(&tscs454->dac_ram);
297 coeff_ram_init(&tscs454->spk_ram);
298 coeff_ram_init(&tscs454->sub_ram);
299
300 return 0;
301 }
302
303 struct reg_setting {
304 unsigned int addr;
305 unsigned int val;
306 };
307
coeff_ram_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)308 static int coeff_ram_get(struct snd_kcontrol *kcontrol,
309 struct snd_ctl_elem_value *ucontrol)
310 {
311 struct snd_soc_component *component =
312 snd_soc_kcontrol_component(kcontrol);
313 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
314 struct coeff_ram_ctl *ctl =
315 (struct coeff_ram_ctl *)kcontrol->private_value;
316 struct soc_bytes_ext *params = &ctl->bytes_ext;
317 u8 *coeff_ram;
318 struct mutex *coeff_ram_lock;
319
320 if (strstr(kcontrol->id.name, "DAC")) {
321 coeff_ram = tscs454->dac_ram.cache;
322 coeff_ram_lock = &tscs454->dac_ram.lock;
323 } else if (strstr(kcontrol->id.name, "Speaker")) {
324 coeff_ram = tscs454->spk_ram.cache;
325 coeff_ram_lock = &tscs454->spk_ram.lock;
326 } else if (strstr(kcontrol->id.name, "Sub")) {
327 coeff_ram = tscs454->sub_ram.cache;
328 coeff_ram_lock = &tscs454->sub_ram.lock;
329 } else {
330 return -EINVAL;
331 }
332
333 mutex_lock(coeff_ram_lock);
334
335 memcpy(ucontrol->value.bytes.data,
336 &coeff_ram[ctl->addr * COEFF_SIZE], params->max);
337
338 mutex_unlock(coeff_ram_lock);
339
340 return 0;
341 }
342
343 #define DACCRSTAT_MAX_TRYS 10
write_coeff_ram(struct snd_soc_component * component,u8 * coeff_ram,unsigned int r_stat,unsigned int r_addr,unsigned int r_wr,unsigned int coeff_addr,unsigned int coeff_cnt)344 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
345 unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
346 unsigned int coeff_addr, unsigned int coeff_cnt)
347 {
348 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
349 unsigned int val;
350 int cnt;
351 int trys;
352 int ret;
353
354 for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
355
356 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
357 val = snd_soc_component_read(component, r_stat);
358 if (!val)
359 break;
360 }
361
362 if (trys == DACCRSTAT_MAX_TRYS) {
363 ret = -EIO;
364 dev_err(component->dev,
365 "Coefficient write error (%d)\n", ret);
366 return ret;
367 }
368
369 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
370 if (ret < 0) {
371 dev_err(component->dev,
372 "Failed to write dac ram address (%d)\n", ret);
373 return ret;
374 }
375
376 ret = regmap_bulk_write(tscs454->regmap, r_wr,
377 &coeff_ram[coeff_addr * COEFF_SIZE],
378 COEFF_SIZE);
379 if (ret < 0) {
380 dev_err(component->dev,
381 "Failed to write dac ram (%d)\n", ret);
382 return ret;
383 }
384 }
385
386 return 0;
387 }
388
coeff_ram_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)389 static int coeff_ram_put(struct snd_kcontrol *kcontrol,
390 struct snd_ctl_elem_value *ucontrol)
391 {
392 struct snd_soc_component *component =
393 snd_soc_kcontrol_component(kcontrol);
394 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
395 struct coeff_ram_ctl *ctl =
396 (struct coeff_ram_ctl *)kcontrol->private_value;
397 struct soc_bytes_ext *params = &ctl->bytes_ext;
398 unsigned int coeff_cnt = params->max / COEFF_SIZE;
399 u8 *coeff_ram;
400 struct mutex *coeff_ram_lock;
401 bool *coeff_ram_synced;
402 unsigned int r_stat;
403 unsigned int r_addr;
404 unsigned int r_wr;
405 unsigned int val;
406 int ret;
407
408 if (strstr(kcontrol->id.name, "DAC")) {
409 coeff_ram = tscs454->dac_ram.cache;
410 coeff_ram_lock = &tscs454->dac_ram.lock;
411 coeff_ram_synced = &tscs454->dac_ram.synced;
412 r_stat = R_DACCRS;
413 r_addr = R_DACCRADD;
414 r_wr = R_DACCRWDL;
415 } else if (strstr(kcontrol->id.name, "Speaker")) {
416 coeff_ram = tscs454->spk_ram.cache;
417 coeff_ram_lock = &tscs454->spk_ram.lock;
418 coeff_ram_synced = &tscs454->spk_ram.synced;
419 r_stat = R_SPKCRS;
420 r_addr = R_SPKCRADD;
421 r_wr = R_SPKCRWDL;
422 } else if (strstr(kcontrol->id.name, "Sub")) {
423 coeff_ram = tscs454->sub_ram.cache;
424 coeff_ram_lock = &tscs454->sub_ram.lock;
425 coeff_ram_synced = &tscs454->sub_ram.synced;
426 r_stat = R_SUBCRS;
427 r_addr = R_SUBCRADD;
428 r_wr = R_SUBCRWDL;
429 } else {
430 return -EINVAL;
431 }
432
433 mutex_lock(coeff_ram_lock);
434
435 *coeff_ram_synced = false;
436
437 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
438 ucontrol->value.bytes.data, params->max);
439
440 mutex_lock(&tscs454->pll1.lock);
441 mutex_lock(&tscs454->pll2.lock);
442
443 val = snd_soc_component_read(component, R_PLLSTAT);
444 if (val) { /* PLLs locked */
445 ret = write_coeff_ram(component, coeff_ram,
446 r_stat, r_addr, r_wr,
447 ctl->addr, coeff_cnt);
448 if (ret < 0) {
449 dev_err(component->dev,
450 "Failed to flush coeff ram cache (%d)\n", ret);
451 goto exit;
452 }
453 *coeff_ram_synced = true;
454 }
455
456 ret = 0;
457 exit:
458 mutex_unlock(&tscs454->pll2.lock);
459 mutex_unlock(&tscs454->pll1.lock);
460 mutex_unlock(coeff_ram_lock);
461
462 return ret;
463 }
464
coeff_ram_sync(struct snd_soc_component * component,struct tscs454 * tscs454)465 static inline int coeff_ram_sync(struct snd_soc_component *component,
466 struct tscs454 *tscs454)
467 {
468 int ret;
469
470 mutex_lock(&tscs454->dac_ram.lock);
471 if (!tscs454->dac_ram.synced) {
472 ret = write_coeff_ram(component, tscs454->dac_ram.cache,
473 R_DACCRS, R_DACCRADD, R_DACCRWDL,
474 0x00, COEFF_RAM_COEFF_COUNT);
475 if (ret < 0) {
476 mutex_unlock(&tscs454->dac_ram.lock);
477 return ret;
478 }
479 }
480 mutex_unlock(&tscs454->dac_ram.lock);
481
482 mutex_lock(&tscs454->spk_ram.lock);
483 if (!tscs454->spk_ram.synced) {
484 ret = write_coeff_ram(component, tscs454->spk_ram.cache,
485 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
486 0x00, COEFF_RAM_COEFF_COUNT);
487 if (ret < 0) {
488 mutex_unlock(&tscs454->spk_ram.lock);
489 return ret;
490 }
491 }
492 mutex_unlock(&tscs454->spk_ram.lock);
493
494 mutex_lock(&tscs454->sub_ram.lock);
495 if (!tscs454->sub_ram.synced) {
496 ret = write_coeff_ram(component, tscs454->sub_ram.cache,
497 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
498 0x00, COEFF_RAM_COEFF_COUNT);
499 if (ret < 0) {
500 mutex_unlock(&tscs454->sub_ram.lock);
501 return ret;
502 }
503 }
504 mutex_unlock(&tscs454->sub_ram.lock);
505
506 return 0;
507 }
508
509 #define PLL_REG_SETTINGS_COUNT 11
510 struct pll_ctl {
511 int freq_in;
512 struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
513 };
514
515 #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h) \
516 { \
517 .freq_in = f, \
518 .settings = { \
519 {R_PLL1CTL, c1}, \
520 {R_PLL1RDIV, r1}, \
521 {R_PLL1ODIV, o1}, \
522 {R_PLL1FDIVL, f1l}, \
523 {R_PLL1FDIVH, f1h}, \
524 {R_PLL2CTL, c2}, \
525 {R_PLL2RDIV, r2}, \
526 {R_PLL2ODIV, o2}, \
527 {R_PLL2FDIVL, f2l}, \
528 {R_PLL2FDIVH, f2h}, \
529 {R_TIMEBASE, t}, \
530 }, \
531 }
532
533 static const struct pll_ctl pll_ctls[] = {
534 PLL_CTL(1411200, 0x05,
535 0xB9, 0x07, 0x02, 0xC3, 0x04,
536 0x5A, 0x02, 0x03, 0xE0, 0x01),
537 PLL_CTL(1536000, 0x05,
538 0x5A, 0x02, 0x03, 0xE0, 0x01,
539 0x5A, 0x02, 0x03, 0xB9, 0x01),
540 PLL_CTL(2822400, 0x0A,
541 0x63, 0x07, 0x04, 0xC3, 0x04,
542 0x62, 0x07, 0x03, 0x48, 0x03),
543 PLL_CTL(3072000, 0x0B,
544 0x62, 0x07, 0x03, 0x48, 0x03,
545 0x5A, 0x04, 0x03, 0xB9, 0x01),
546 PLL_CTL(5644800, 0x15,
547 0x63, 0x0E, 0x04, 0xC3, 0x04,
548 0x5A, 0x08, 0x03, 0xE0, 0x01),
549 PLL_CTL(6144000, 0x17,
550 0x5A, 0x08, 0x03, 0xE0, 0x01,
551 0x5A, 0x08, 0x03, 0xB9, 0x01),
552 PLL_CTL(12000000, 0x2E,
553 0x5B, 0x19, 0x03, 0x00, 0x03,
554 0x6A, 0x19, 0x05, 0x98, 0x04),
555 PLL_CTL(19200000, 0x4A,
556 0x53, 0x14, 0x03, 0x80, 0x01,
557 0x5A, 0x19, 0x03, 0xB9, 0x01),
558 PLL_CTL(22000000, 0x55,
559 0x6A, 0x37, 0x05, 0x00, 0x06,
560 0x62, 0x26, 0x03, 0x49, 0x02),
561 PLL_CTL(22579200, 0x57,
562 0x62, 0x31, 0x03, 0x20, 0x03,
563 0x53, 0x1D, 0x03, 0xB3, 0x01),
564 PLL_CTL(24000000, 0x5D,
565 0x53, 0x19, 0x03, 0x80, 0x01,
566 0x5B, 0x19, 0x05, 0x4C, 0x02),
567 PLL_CTL(24576000, 0x5F,
568 0x53, 0x1D, 0x03, 0xB3, 0x01,
569 0x62, 0x40, 0x03, 0x72, 0x03),
570 PLL_CTL(27000000, 0x68,
571 0x62, 0x4B, 0x03, 0x00, 0x04,
572 0x6A, 0x7D, 0x03, 0x20, 0x06),
573 PLL_CTL(36000000, 0x8C,
574 0x5B, 0x4B, 0x03, 0x00, 0x03,
575 0x6A, 0x7D, 0x03, 0x98, 0x04),
576 PLL_CTL(11289600, 0x2B,
577 0x6A, 0x31, 0x03, 0x40, 0x06,
578 0x5A, 0x12, 0x03, 0x1C, 0x02),
579 PLL_CTL(26000000, 0x65,
580 0x63, 0x41, 0x05, 0x00, 0x06,
581 0x5A, 0x26, 0x03, 0xEF, 0x01),
582 PLL_CTL(12288000, 0x2F,
583 0x5A, 0x12, 0x03, 0x1C, 0x02,
584 0x62, 0x20, 0x03, 0x72, 0x03),
585 PLL_CTL(40000000, 0x9B,
586 0xA2, 0x7D, 0x03, 0x80, 0x04,
587 0x63, 0x7D, 0x05, 0xE4, 0x06),
588 PLL_CTL(512000, 0x01,
589 0x62, 0x01, 0x03, 0xD0, 0x02,
590 0x5B, 0x01, 0x04, 0x72, 0x03),
591 PLL_CTL(705600, 0x02,
592 0x62, 0x02, 0x03, 0x15, 0x04,
593 0x62, 0x01, 0x04, 0x80, 0x02),
594 PLL_CTL(1024000, 0x03,
595 0x62, 0x02, 0x03, 0xD0, 0x02,
596 0x5B, 0x02, 0x04, 0x72, 0x03),
597 PLL_CTL(2048000, 0x07,
598 0x62, 0x04, 0x03, 0xD0, 0x02,
599 0x5B, 0x04, 0x04, 0x72, 0x03),
600 PLL_CTL(2400000, 0x08,
601 0x62, 0x05, 0x03, 0x00, 0x03,
602 0x63, 0x05, 0x05, 0x98, 0x04),
603 };
604
get_pll_ctl(unsigned long freq_in)605 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
606 {
607 int i;
608 struct pll_ctl const *pll_ctl = NULL;
609
610 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
611 if (pll_ctls[i].freq_in == freq_in) {
612 pll_ctl = &pll_ctls[i];
613 break;
614 }
615
616 return pll_ctl;
617 }
618
619 enum {
620 PLL_INPUT_XTAL = 0,
621 PLL_INPUT_MCLK1,
622 PLL_INPUT_MCLK2,
623 PLL_INPUT_BCLK,
624 };
625
set_sysclk(struct snd_soc_component * component)626 static int set_sysclk(struct snd_soc_component *component)
627 {
628 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
629 struct pll_ctl const *pll_ctl;
630 unsigned long freq;
631 int i;
632 int ret;
633
634 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
635 freq = clk_get_rate(tscs454->sysclk);
636 else
637 freq = tscs454->bclk_freq;
638 pll_ctl = get_pll_ctl(freq);
639 if (!pll_ctl) {
640 ret = -EINVAL;
641 dev_err(component->dev,
642 "Invalid PLL input %lu (%d)\n", freq, ret);
643 return ret;
644 }
645
646 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
647 ret = snd_soc_component_write(component,
648 pll_ctl->settings[i].addr,
649 pll_ctl->settings[i].val);
650 if (ret < 0) {
651 dev_err(component->dev,
652 "Failed to set pll setting (%d)\n",
653 ret);
654 return ret;
655 }
656 }
657
658 return 0;
659 }
660
reserve_pll(struct pll * pll)661 static inline void reserve_pll(struct pll *pll)
662 {
663 mutex_lock(&pll->lock);
664 pll->users++;
665 mutex_unlock(&pll->lock);
666 }
667
free_pll(struct pll * pll)668 static inline void free_pll(struct pll *pll)
669 {
670 mutex_lock(&pll->lock);
671 pll->users--;
672 mutex_unlock(&pll->lock);
673 }
674
pll_connected(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)675 static int pll_connected(struct snd_soc_dapm_widget *source,
676 struct snd_soc_dapm_widget *sink)
677 {
678 struct snd_soc_component *component =
679 snd_soc_dapm_to_component(source->dapm);
680 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
681 int users;
682
683 if (strstr(source->name, "PLL 1")) {
684 mutex_lock(&tscs454->pll1.lock);
685 users = tscs454->pll1.users;
686 mutex_unlock(&tscs454->pll1.lock);
687 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
688 users);
689 } else {
690 mutex_lock(&tscs454->pll2.lock);
691 users = tscs454->pll2.users;
692 mutex_unlock(&tscs454->pll2.lock);
693 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
694 users);
695 }
696
697 return users;
698 }
699
700 /*
701 * PLL must be enabled after power up and must be disabled before power down
702 * for proper clock switching.
703 */
pll_power_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)704 static int pll_power_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706 {
707 struct snd_soc_component *component =
708 snd_soc_dapm_to_component(w->dapm);
709 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
710 bool enable;
711 bool pll1;
712 unsigned int msk;
713 unsigned int val;
714 int ret;
715
716 if (strstr(w->name, "PLL 1"))
717 pll1 = true;
718 else
719 pll1 = false;
720
721 msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
722
723 if (event == SND_SOC_DAPM_POST_PMU)
724 enable = true;
725 else
726 enable = false;
727
728 if (enable)
729 val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
730 else
731 /*
732 * FV_PLL1CLKEN_DISABLE and FV_PLL2CLKEN_DISABLE are
733 * identical zero vzalues, there is no need to test
734 * the PLL index
735 */
736 val = FV_PLL1CLKEN_DISABLE;
737
738 ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
739 if (ret < 0) {
740 dev_err(component->dev, "Failed to %s PLL %d (%d)\n",
741 str_enable_disable(enable), pll1 ? 1 : 2, ret);
742 return ret;
743 }
744
745 if (enable) {
746 msleep(20); // Wait for lock
747 ret = coeff_ram_sync(component, tscs454);
748 if (ret < 0) {
749 dev_err(component->dev,
750 "Failed to sync coeff ram (%d)\n", ret);
751 return ret;
752 }
753 }
754
755 return 0;
756 }
757
aif_set_provider(struct snd_soc_component * component,unsigned int aif_id,bool provider)758 static inline int aif_set_provider(struct snd_soc_component *component,
759 unsigned int aif_id, bool provider)
760 {
761 unsigned int reg;
762 unsigned int mask;
763 unsigned int val;
764 int ret;
765
766 switch (aif_id) {
767 case TSCS454_DAI1_ID:
768 reg = R_I2SP1CTL;
769 break;
770 case TSCS454_DAI2_ID:
771 reg = R_I2SP2CTL;
772 break;
773 case TSCS454_DAI3_ID:
774 reg = R_I2SP3CTL;
775 break;
776 default:
777 ret = -ENODEV;
778 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
779 return ret;
780 }
781 mask = FM_I2SPCTL_PORTMS;
782 val = provider ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
783
784 ret = snd_soc_component_update_bits(component, reg, mask, val);
785 if (ret < 0) {
786 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
787 aif_id, provider ? "provider" : "consumer", ret);
788 return ret;
789 }
790
791 return 0;
792 }
793
794 static inline
aif_prepare(struct snd_soc_component * component,struct aif * aif)795 int aif_prepare(struct snd_soc_component *component, struct aif *aif)
796 {
797 int ret;
798
799 ret = aif_set_provider(component, aif->id, aif->provider);
800 if (ret < 0)
801 return ret;
802
803 return 0;
804 }
805
aif_free(struct snd_soc_component * component,struct aif * aif,bool playback)806 static inline int aif_free(struct snd_soc_component *component,
807 struct aif *aif, bool playback)
808 {
809 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
810
811 mutex_lock(&tscs454->aifs_status_lock);
812
813 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
814
815 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
816
817 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
818 aif->id, tscs454->aifs_status.streams);
819
820 if (!aif_active(&tscs454->aifs_status, aif->id)) {
821 /* Do config in slave mode */
822 aif_set_provider(component, aif->id, false);
823 dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
824 aif->pll->id, aif->id);
825 free_pll(aif->pll);
826 }
827
828 if (!aifs_active(&tscs454->aifs_status)) {
829 dev_dbg(component->dev, "Freeing pll %d from ir\n",
830 tscs454->internal_rate.pll->id);
831 free_pll(tscs454->internal_rate.pll);
832 }
833
834 mutex_unlock(&tscs454->aifs_status_lock);
835
836 return 0;
837 }
838
839 /* R_PLLCTL PG 0 ADDR 0x15 */
840 static char const * const bclk_sel_txt[] = {
841 "BCLK 1", "BCLK 2", "BCLK 3"};
842
843 static struct soc_enum const bclk_sel_enum =
844 SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
845 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
846
847 /* R_ISRC PG 0 ADDR 0x16 */
848 static char const * const isrc_br_txt[] = {
849 "44.1kHz", "48kHz"};
850
851 static struct soc_enum const isrc_br_enum =
852 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
853 ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
854
855 static char const * const isrc_bm_txt[] = {
856 "0.25x", "0.5x", "1.0x", "2.0x"};
857
858 static struct soc_enum const isrc_bm_enum =
859 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
860 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
861
862 /* R_SCLKCTL PG 0 ADDR 0x18 */
863 static char const * const modular_rate_txt[] = {
864 "Reserved", "Half", "Full", "Auto",};
865
866 static struct soc_enum const adc_modular_rate_enum =
867 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
868 ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
869
870 static struct soc_enum const dac_modular_rate_enum =
871 SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
872 ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
873
874 /* R_I2SIDCTL PG 0 ADDR 0x38 */
875 static char const * const data_ctrl_txt[] = {
876 "L/R", "L/L", "R/R", "R/L"};
877
878 static struct soc_enum const data_in_ctrl_enums[] = {
879 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
880 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
881 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
882 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
883 SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
884 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
885 };
886
887 /* R_I2SODCTL PG 0 ADDR 0x39 */
888 static struct soc_enum const data_out_ctrl_enums[] = {
889 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
890 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
891 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
892 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
893 SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
894 ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
895 };
896
897 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
898 static char const * const asrc_mux_txt[] = {
899 "None", "DAI 1", "DAI 2", "DAI 3"};
900
901 static struct soc_enum const asrc_in_mux_enum =
902 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
903 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
904
905 static char const * const dai_mux_txt[] = {
906 "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
907 "DMic 2", "ClassD", "DAC", "Sub"};
908
909 static struct soc_enum const dai2_mux_enum =
910 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
911 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
912
913 static struct snd_kcontrol_new const dai2_mux_dapm_enum =
914 SOC_DAPM_ENUM("DAI 2 Mux", dai2_mux_enum);
915
916 static struct soc_enum const dai1_mux_enum =
917 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
918 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
919
920 static struct snd_kcontrol_new const dai1_mux_dapm_enum =
921 SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
922
923 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
924 static struct soc_enum const asrc_out_mux_enum =
925 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
926 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
927
928 static struct soc_enum const dac_mux_enum =
929 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
930 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
931
932 static struct snd_kcontrol_new const dac_mux_dapm_enum =
933 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
934
935 static struct soc_enum const dai3_mux_enum =
936 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
937 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
938
939 static struct snd_kcontrol_new const dai3_mux_dapm_enum =
940 SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
941
942 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
943 static char const * const sub_mux_txt[] = {
944 "CH 0", "CH 1", "CH 0 + 1",
945 "CH 2", "CH 3", "CH 2 + 3",
946 "CH 4", "CH 5", "CH 4 + 5",
947 "ADC/DMic 1 Left", "ADC/DMic 1 Right",
948 "ADC/DMic 1 Left Plus Right",
949 "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
950 "ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
951
952 static struct soc_enum const sub_mux_enum =
953 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
954 ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
955
956 static struct snd_kcontrol_new const sub_mux_dapm_enum =
957 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
958
959 static struct soc_enum const classd_mux_enum =
960 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
961 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
962
963 static struct snd_kcontrol_new const classd_mux_dapm_enum =
964 SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
965
966 /* R_HSDCTL1 PG 1 ADDR 0x01 */
967 static char const * const jack_type_txt[] = {
968 "3 Terminal", "4 Terminal"};
969
970 static struct soc_enum const hp_jack_type_enum =
971 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
972 ARRAY_SIZE(jack_type_txt), jack_type_txt);
973
974 static char const * const hs_det_pol_txt[] = {
975 "Rising", "Falling"};
976
977 static struct soc_enum const hs_det_pol_enum =
978 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
979 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
980
981 /* R_HSDCTL1 PG 1 ADDR 0x02 */
982 static char const * const hs_mic_bias_force_txt[] = {
983 "Off", "Ring", "Sleeve"};
984
985 static struct soc_enum const hs_mic_bias_force_enum =
986 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
987 ARRAY_SIZE(hs_mic_bias_force_txt),
988 hs_mic_bias_force_txt);
989
990 static char const * const plug_type_txt[] = {
991 "OMTP", "CTIA", "Reserved", "Headphone"};
992
993 static struct soc_enum const plug_type_force_enum =
994 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
995 ARRAY_SIZE(plug_type_txt), plug_type_txt);
996
997
998 /* R_CH0AIC PG 1 ADDR 0x06 */
999 static char const * const in_bst_mux_txt[] = {
1000 "Input 1", "Input 2", "Input 3", "D2S"};
1001
1002 static struct soc_enum const in_bst_mux_ch0_enum =
1003 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
1004 ARRAY_SIZE(in_bst_mux_txt),
1005 in_bst_mux_txt);
1006 static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
1007 SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
1008 in_bst_mux_ch0_enum);
1009
1010 static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
1011
1012 static char const * const adc_mux_txt[] = {
1013 "Input 1 Boost Bypass", "Input 2 Boost Bypass",
1014 "Input 3 Boost Bypass", "Input Boost"};
1015
1016 static struct soc_enum const adc_mux_ch0_enum =
1017 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
1018 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1019 static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
1020 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
1021
1022 static char const * const in_proc_mux_txt[] = {
1023 "ADC", "DMic"};
1024
1025 static struct soc_enum const in_proc_ch0_enum =
1026 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
1027 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1028 static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
1029 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1030 in_proc_ch0_enum);
1031
1032 /* R_CH1AIC PG 1 ADDR 0x07 */
1033 static struct soc_enum const in_bst_mux_ch1_enum =
1034 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
1035 ARRAY_SIZE(in_bst_mux_txt),
1036 in_bst_mux_txt);
1037 static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
1038 SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
1039 in_bst_mux_ch1_enum);
1040
1041 static struct soc_enum const adc_mux_ch1_enum =
1042 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
1043 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1044 static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
1045 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
1046
1047 static struct soc_enum const in_proc_ch1_enum =
1048 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
1049 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1050 static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
1051 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1052 in_proc_ch1_enum);
1053
1054 /* R_ICTL0 PG 1 ADDR 0x0A */
1055 static char const * const pol_txt[] = {
1056 "Normal", "Invert"};
1057
1058 static struct soc_enum const in_pol_ch1_enum =
1059 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
1060 ARRAY_SIZE(pol_txt), pol_txt);
1061
1062 static struct soc_enum const in_pol_ch0_enum =
1063 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
1064 ARRAY_SIZE(pol_txt), pol_txt);
1065
1066 static char const * const in_proc_ch_sel_txt[] = {
1067 "Normal", "Mono Mix to Channel 0",
1068 "Mono Mix to Channel 1", "Add"};
1069
1070 static struct soc_enum const in_proc_ch01_sel_enum =
1071 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
1072 ARRAY_SIZE(in_proc_ch_sel_txt),
1073 in_proc_ch_sel_txt);
1074
1075 /* R_ICTL1 PG 1 ADDR 0x0B */
1076 static struct soc_enum const in_pol_ch3_enum =
1077 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
1078 ARRAY_SIZE(pol_txt), pol_txt);
1079
1080 static struct soc_enum const in_pol_ch2_enum =
1081 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
1082 ARRAY_SIZE(pol_txt), pol_txt);
1083
1084 static struct soc_enum const in_proc_ch23_sel_enum =
1085 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
1086 ARRAY_SIZE(in_proc_ch_sel_txt),
1087 in_proc_ch_sel_txt);
1088
1089 /* R_MICBIAS PG 1 ADDR 0x0C */
1090 static char const * const mic_bias_txt[] = {
1091 "2.5V", "2.1V", "1.8V", "Vdd"};
1092
1093 static struct soc_enum const mic_bias_2_enum =
1094 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
1095 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1096
1097 static struct soc_enum const mic_bias_1_enum =
1098 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
1099 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1100
1101 /* R_PGACTL0 PG 1 ADDR 0x0D */
1102 /* R_PGACTL1 PG 1 ADDR 0x0E */
1103 /* R_PGACTL2 PG 1 ADDR 0x0F */
1104 /* R_PGACTL3 PG 1 ADDR 0x10 */
1105 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1106
1107 /* R_ICH0VOL PG1 ADDR 0x12 */
1108 /* R_ICH1VOL PG1 ADDR 0x13 */
1109 /* R_ICH2VOL PG1 ADDR 0x14 */
1110 /* R_ICH3VOL PG1 ADDR 0x15 */
1111 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1112
1113 /* R_ASRCILVOL PG1 ADDR 0x16 */
1114 /* R_ASRCIRVOL PG1 ADDR 0x17 */
1115 /* R_ASRCOLVOL PG1 ADDR 0x18 */
1116 /* R_ASRCORVOL PG1 ADDR 0x19 */
1117 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1118
1119 /* R_ALCCTL0 PG1 ADDR 0x1D */
1120 static char const * const alc_mode_txt[] = {
1121 "ALC", "Limiter"};
1122
1123 static struct soc_enum const alc_mode_enum =
1124 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
1125 ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
1126
1127 static char const * const alc_ref_text[] = {
1128 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
1129
1130 static struct soc_enum const alc_ref_enum =
1131 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
1132 ARRAY_SIZE(alc_ref_text), alc_ref_text);
1133
1134 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1135 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1136 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1137
1138 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1139 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1140
1141 /* R_NGATE PG 1 ADDR 0x21 */
1142 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1143
1144 static char const * const ngate_type_txt[] = {
1145 "PGA Constant", "ADC Mute"};
1146
1147 static struct soc_enum const ngate_type_enum =
1148 SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
1149 ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
1150
1151 /* R_DMICCTL PG 1 ADDR 0x22 */
1152 static char const * const dmic_mono_sel_txt[] = {
1153 "Stereo", "Mono"};
1154
1155 static struct soc_enum const dmic_mono_sel_enum =
1156 SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
1157 ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
1158
1159 /* R_DACCTL PG 2 ADDR 0x01 */
1160 static struct soc_enum const dac_pol_r_enum =
1161 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
1162 ARRAY_SIZE(pol_txt), pol_txt);
1163
1164 static struct soc_enum const dac_pol_l_enum =
1165 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
1166 ARRAY_SIZE(pol_txt), pol_txt);
1167
1168 static char const * const dac_dith_txt[] = {
1169 "Half", "Full", "Disabled", "Static"};
1170
1171 static struct soc_enum const dac_dith_enum =
1172 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
1173 ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
1174
1175 /* R_SPKCTL PG 2 ADDR 0x02 */
1176 static struct soc_enum const spk_pol_r_enum =
1177 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
1178 ARRAY_SIZE(pol_txt), pol_txt);
1179
1180 static struct soc_enum const spk_pol_l_enum =
1181 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
1182 ARRAY_SIZE(pol_txt), pol_txt);
1183
1184 /* R_SUBCTL PG 2 ADDR 0x03 */
1185 static struct soc_enum const sub_pol_enum =
1186 SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
1187 ARRAY_SIZE(pol_txt), pol_txt);
1188
1189 /* R_MVOLL PG 2 ADDR 0x08 */
1190 /* R_MVOLR PG 2 ADDR 0x09 */
1191 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1192
1193 /* R_HPVOLL PG 2 ADDR 0x0A */
1194 /* R_HPVOLR PG 2 ADDR 0x0B */
1195 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1196
1197 /* R_SPKVOLL PG 2 ADDR 0x0C */
1198 /* R_SPKVOLR PG 2 ADDR 0x0D */
1199 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1200
1201 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1202 static char const * const eq_txt[] = {
1203 "Pre Scale",
1204 "Pre Scale + EQ Band 0",
1205 "Pre Scale + EQ Band 0 - 1",
1206 "Pre Scale + EQ Band 0 - 2",
1207 "Pre Scale + EQ Band 0 - 3",
1208 "Pre Scale + EQ Band 0 - 4",
1209 "Pre Scale + EQ Band 0 - 5",
1210 };
1211
1212 static struct soc_enum const spk_eq_enums[] = {
1213 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
1214 ARRAY_SIZE(eq_txt), eq_txt),
1215 SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
1216 ARRAY_SIZE(eq_txt), eq_txt),
1217 };
1218
1219 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1220 static char const * const lvl_mode_txt[] = {
1221 "Average", "Peak"};
1222
1223 static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
1224 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
1225 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1226
1227 static char const * const win_sel_txt[] = {
1228 "512", "64"};
1229
1230 static struct soc_enum const spk_mbc3_win_sel_enum =
1231 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
1232 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1233
1234 static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
1235 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
1236 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1237
1238 static struct soc_enum const spk_mbc2_win_sel_enum =
1239 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
1240 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1241
1242 static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
1243 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
1244 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1245
1246 static struct soc_enum const spk_mbc1_win_sel_enum =
1247 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
1248 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1249
1250 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1251 static struct soc_enum const spk_mbc1_phase_pol_enum =
1252 SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
1253 ARRAY_SIZE(pol_txt), pol_txt);
1254
1255 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1256
1257 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1258 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1259
1260 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1261 static char const * const comp_rat_txt[] = {
1262 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
1263 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
1264 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
1265
1266 static struct soc_enum const spk_mbc1_comp_rat_enum =
1267 SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
1268 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1269
1270 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1271 static struct soc_enum const spk_mbc2_phase_pol_enum =
1272 SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
1273 ARRAY_SIZE(pol_txt), pol_txt);
1274
1275 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1276 static struct soc_enum const spk_mbc2_comp_rat_enum =
1277 SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
1278 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1279
1280 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1281 static struct soc_enum const spk_mbc3_phase_pol_enum =
1282 SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
1283 ARRAY_SIZE(pol_txt), pol_txt);
1284
1285 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1286 static struct soc_enum const spk_mbc3_comp_rat_enum =
1287 SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
1288 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1289
1290 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1291 static struct soc_enum const spk_cle_lvl_mode_enum =
1292 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
1293 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1294
1295 static struct soc_enum const spk_cle_win_sel_enum =
1296 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
1297 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1298
1299 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1300 static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
1301
1302 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1303 static struct soc_enum const spk_comp_rat_enum =
1304 SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
1305 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1306
1307 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1308 static char const * const exp_rat_txt[] = {
1309 "Reserved", "Reserved", "1:2", "1:3",
1310 "1:4", "1:5", "1:6", "1:7"};
1311
1312 static struct soc_enum const spk_exp_rat_enum =
1313 SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
1314 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1315
1316 /* R_DACEQFILT PG 4 ADDR 0x01 */
1317 static struct soc_enum const dac_eq_enums[] = {
1318 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
1319 ARRAY_SIZE(eq_txt), eq_txt),
1320 SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
1321 ARRAY_SIZE(eq_txt), eq_txt),
1322 };
1323
1324 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1325 static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
1326 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
1327 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1328
1329 static struct soc_enum const dac_mbc3_win_sel_enum =
1330 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
1331 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1332
1333 static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
1334 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
1335 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1336
1337 static struct soc_enum const dac_mbc2_win_sel_enum =
1338 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
1339 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1340
1341 static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
1342 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
1343 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1344
1345 static struct soc_enum const dac_mbc1_win_sel_enum =
1346 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
1347 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1348
1349 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1350 static struct soc_enum const dac_mbc1_phase_pol_enum =
1351 SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
1352 ARRAY_SIZE(pol_txt), pol_txt);
1353
1354 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1355 static struct soc_enum const dac_mbc1_comp_rat_enum =
1356 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
1357 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1358
1359 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1360 static struct soc_enum const dac_mbc2_phase_pol_enum =
1361 SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
1362 ARRAY_SIZE(pol_txt), pol_txt);
1363
1364 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1365 static struct soc_enum const dac_mbc2_comp_rat_enum =
1366 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
1367 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1368
1369 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1370 static struct soc_enum const dac_mbc3_phase_pol_enum =
1371 SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
1372 ARRAY_SIZE(pol_txt), pol_txt);
1373
1374 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1375 static struct soc_enum const dac_mbc3_comp_rat_enum =
1376 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
1377 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1378
1379 /* R_DACCLECTL PG 4 ADDR 0x21 */
1380 static struct soc_enum const dac_cle_lvl_mode_enum =
1381 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
1382 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1383
1384 static struct soc_enum const dac_cle_win_sel_enum =
1385 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
1386 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1387
1388 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1389 static struct soc_enum const dac_comp_rat_enum =
1390 SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
1391 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1392
1393 /* R_DACEXPRAT PG 4 ADDR 0x30 */
1394 static struct soc_enum const dac_exp_rat_enum =
1395 SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
1396 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1397
1398 /* R_SUBEQFILT PG 5 ADDR 0x01 */
1399 static struct soc_enum const sub_eq_enums[] = {
1400 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
1401 ARRAY_SIZE(eq_txt), eq_txt),
1402 SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
1403 ARRAY_SIZE(eq_txt), eq_txt),
1404 };
1405
1406 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
1407 static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
1408 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
1409 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1410
1411 static struct soc_enum const sub_mbc3_win_sel_enum =
1412 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
1413 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1414
1415 static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
1416 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
1417 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1418
1419 static struct soc_enum const sub_mbc2_win_sel_enum =
1420 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
1421 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1422
1423 static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
1424 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
1425 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1426
1427 static struct soc_enum const sub_mbc1_win_sel_enum =
1428 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
1429 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1430
1431 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
1432 static struct soc_enum const sub_mbc1_phase_pol_enum =
1433 SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
1434 ARRAY_SIZE(pol_txt), pol_txt);
1435
1436 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
1437 static struct soc_enum const sub_mbc1_comp_rat_enum =
1438 SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
1439 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1440
1441 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
1442 static struct soc_enum const sub_mbc2_phase_pol_enum =
1443 SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
1444 ARRAY_SIZE(pol_txt), pol_txt);
1445
1446 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
1447 static struct soc_enum const sub_mbc2_comp_rat_enum =
1448 SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
1449 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1450
1451 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
1452 static struct soc_enum const sub_mbc3_phase_pol_enum =
1453 SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
1454 ARRAY_SIZE(pol_txt), pol_txt);
1455
1456 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
1457 static struct soc_enum const sub_mbc3_comp_rat_enum =
1458 SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
1459 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1460
1461 /* R_SUBCLECTL PG 5 ADDR 0x21 */
1462 static struct soc_enum const sub_cle_lvl_mode_enum =
1463 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
1464 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1465 static struct soc_enum const sub_cle_win_sel_enum =
1466 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
1467 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1468
1469 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
1470 static struct soc_enum const sub_comp_rat_enum =
1471 SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
1472 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1473
1474 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
1475 static struct soc_enum const sub_exp_rat_enum =
1476 SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
1477 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1478
bytes_info_ext(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * ucontrol)1479 static int bytes_info_ext(struct snd_kcontrol *kcontrol,
1480 struct snd_ctl_elem_info *ucontrol)
1481 {
1482 struct coeff_ram_ctl *ctl =
1483 (struct coeff_ram_ctl *)kcontrol->private_value;
1484 struct soc_bytes_ext *params = &ctl->bytes_ext;
1485
1486 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1487 ucontrol->count = params->max;
1488
1489 return 0;
1490 }
1491
1492 /* CH 0_1 Input Mux */
1493 static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
1494
1495 static struct soc_enum const ch_0_1_mux_enum =
1496 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1497 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
1498
1499 static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
1500 SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
1501
1502 /* CH 2_3 Input Mux */
1503 static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
1504
1505 static struct soc_enum const ch_2_3_mux_enum =
1506 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1507 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
1508
1509 static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
1510 SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
1511
1512 /* CH 4_5 Input Mux */
1513 static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
1514
1515 static struct soc_enum const ch_4_5_mux_enum =
1516 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1517 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
1518
1519 static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
1520 SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
1521
1522 #define COEFF_RAM_CTL(xname, xcount, xaddr) \
1523 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1524 .info = bytes_info_ext, \
1525 .get = coeff_ram_get, .put = coeff_ram_put, \
1526 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
1527 .addr = xaddr, \
1528 .bytes_ext = {.max = xcount, }, \
1529 } \
1530 }
1531
1532 static struct snd_kcontrol_new const tscs454_snd_controls[] = {
1533 /* R_PLLCTL PG 0 ADDR 0x15 */
1534 SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
1535 /* R_ISRC PG 0 ADDR 0x16 */
1536 SOC_ENUM("Internal Rate", isrc_br_enum),
1537 SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
1538 /* R_SCLKCTL PG 0 ADDR 0x18 */
1539 SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
1540 SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
1541 /* R_ASRC PG 0 ADDR 0x28 */
1542 SOC_SINGLE("ASRC Out High Bandwidth Switch",
1543 R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
1544 SOC_SINGLE("ASRC In High Bandwidth Switch",
1545 R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
1546 /* R_I2SIDCTL PG 0 ADDR 0x38 */
1547 SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
1548 SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
1549 SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
1550 /* R_I2SODCTL PG 0 ADDR 0x39 */
1551 SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
1552 SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
1553 SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
1554 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
1555 SOC_ENUM("ASRC In", asrc_in_mux_enum),
1556 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
1557 SOC_ENUM("ASRC Out", asrc_out_mux_enum),
1558 /* R_HSDCTL1 PG 1 ADDR 0x01 */
1559 SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
1560 SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
1561 SOC_SINGLE("Headphone Detection Switch",
1562 R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
1563 SOC_SINGLE("Headset OMTP/CTIA Switch",
1564 R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
1565 /* R_HSDCTL1 PG 1 ADDR 0x02 */
1566 SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
1567 SOC_SINGLE("Manual Mic Bias Switch",
1568 R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
1569 SOC_SINGLE("Ring/Sleeve Auto Switch",
1570 R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
1571 SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
1572 /* R_CH0AIC PG 1 ADDR 0x06 */
1573 SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
1574 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1575 /* R_CH1AIC PG 1 ADDR 0x07 */
1576 SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
1577 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1578 /* R_CH2AIC PG 1 ADDR 0x08 */
1579 SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
1580 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1581 /* R_CH3AIC PG 1 ADDR 0x09 */
1582 SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
1583 FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1584 /* R_ICTL0 PG 1 ADDR 0x0A */
1585 SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
1586 SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
1587 SOC_ENUM("Input Processor Channel 0/1 Operation",
1588 in_proc_ch01_sel_enum),
1589 SOC_SINGLE("Input Channel 1 Mute Switch",
1590 R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
1591 SOC_SINGLE("Input Channel 0 Mute Switch",
1592 R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
1593 SOC_SINGLE("Input Channel 1 HPF Disable Switch",
1594 R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
1595 SOC_SINGLE("Input Channel 0 HPF Disable Switch",
1596 R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
1597 /* R_ICTL1 PG 1 ADDR 0x0B */
1598 SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
1599 SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
1600 SOC_ENUM("Input Processor Channel 2/3 Operation",
1601 in_proc_ch23_sel_enum),
1602 SOC_SINGLE("Input Channel 3 Mute Switch",
1603 R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
1604 SOC_SINGLE("Input Channel 2 Mute Switch",
1605 R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
1606 SOC_SINGLE("Input Channel 3 HPF Disable Switch",
1607 R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
1608 SOC_SINGLE("Input Channel 2 HPF Disable Switch",
1609 R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
1610 /* R_MICBIAS PG 1 ADDR 0x0C */
1611 SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
1612 SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
1613 /* R_PGACTL0 PG 1 ADDR 0x0D */
1614 SOC_SINGLE("Input Channel 0 PGA Mute Switch",
1615 R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
1616 SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
1617 FB_PGACTL_PGAVOL,
1618 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1619 /* R_PGACTL1 PG 1 ADDR 0x0E */
1620 SOC_SINGLE("Input Channel 1 PGA Mute Switch",
1621 R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
1622 SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
1623 FB_PGACTL_PGAVOL,
1624 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1625 /* R_PGACTL2 PG 1 ADDR 0x0F */
1626 SOC_SINGLE("Input Channel 2 PGA Mute Switch",
1627 R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
1628 SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
1629 FB_PGACTL_PGAVOL,
1630 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1631 /* R_PGACTL3 PG 1 ADDR 0x10 */
1632 SOC_SINGLE("Input Channel 3 PGA Mute Switch",
1633 R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
1634 SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
1635 FB_PGACTL_PGAVOL,
1636 FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1637 /* R_ICH0VOL PG 1 ADDR 0x12 */
1638 SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
1639 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1640 /* R_ICH1VOL PG 1 ADDR 0x13 */
1641 SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
1642 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1643 /* R_ICH2VOL PG 1 ADDR 0x14 */
1644 SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
1645 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1646 /* R_ICH3VOL PG 1 ADDR 0x15 */
1647 SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
1648 FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1649 /* R_ASRCILVOL PG 1 ADDR 0x16 */
1650 SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
1651 FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
1652 0, asrc_vol_tlv_arr),
1653 /* R_ASRCIRVOL PG 1 ADDR 0x17 */
1654 SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
1655 FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
1656 0, asrc_vol_tlv_arr),
1657 /* R_ASRCOLVOL PG 1 ADDR 0x18 */
1658 SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
1659 FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
1660 0, asrc_vol_tlv_arr),
1661 /* R_ASRCORVOL PG 1 ADDR 0x19 */
1662 SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
1663 FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
1664 0, asrc_vol_tlv_arr),
1665 /* R_IVOLCTLU PG 1 ADDR 0x1C */
1666 /* R_ALCCTL0 PG 1 ADDR 0x1D */
1667 SOC_ENUM("ALC Mode", alc_mode_enum),
1668 SOC_ENUM("ALC Reference", alc_ref_enum),
1669 SOC_SINGLE("Input Channel 3 ALC Switch",
1670 R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
1671 SOC_SINGLE("Input Channel 2 ALC Switch",
1672 R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
1673 SOC_SINGLE("Input Channel 1 ALC Switch",
1674 R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
1675 SOC_SINGLE("Input Channel 0 ALC Switch",
1676 R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
1677 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1678 SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
1679 FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
1680 0, alc_max_gain_tlv_arr),
1681 SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
1682 FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
1683 0, alc_target_tlv_arr),
1684 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1685 SOC_SINGLE("ALC Zero Cross Switch",
1686 R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
1687 SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
1688 FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
1689 0, alc_min_gain_tlv_arr),
1690 SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
1691 FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
1692 /* R_ALCCTL3 PG 1 ADDR 0x20 */
1693 SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
1694 FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
1695 SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
1696 FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
1697 /* R_NGATE PG 1 ADDR 0x21 */
1698 SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
1699 FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
1700 SOC_ENUM("Noise Gate Type", ngate_type_enum),
1701 SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
1702 /* R_DMICCTL PG 1 ADDR 0x22 */
1703 SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
1704 SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
1705 SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
1706 /* R_DACCTL PG 2 ADDR 0x01 */
1707 SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
1708 SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
1709 SOC_ENUM("DAC Dither", dac_dith_enum),
1710 SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
1711 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1712 /* R_SPKCTL PG 2 ADDR 0x02 */
1713 SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
1714 SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
1715 SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
1716 SOC_SINGLE("Speaker De-Emphasis Switch",
1717 R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
1718 /* R_SUBCTL PG 2 ADDR 0x03 */
1719 SOC_ENUM("Sub Polarity", sub_pol_enum),
1720 SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1721 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1722 /* R_DCCTL PG 2 ADDR 0x04 */
1723 SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1724 SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
1725 SOC_SINGLE("Speaker DC Removal Switch",
1726 R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
1727 SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
1728 FM_DCCTL_DCCOEFSEL, 0),
1729 /* R_OVOLCTLU PG 2 ADDR 0x06 */
1730 SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
1731 /* R_MVOLL PG 2 ADDR 0x08 */
1732 /* R_MVOLR PG 2 ADDR 0x09 */
1733 SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
1734 FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
1735 /* R_HPVOLL PG 2 ADDR 0x0A */
1736 /* R_HPVOLR PG 2 ADDR 0x0B */
1737 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
1738 FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
1739 hp_vol_tlv_arr),
1740 /* R_SPKVOLL PG 2 ADDR 0x0C */
1741 /* R_SPKVOLR PG 2 ADDR 0x0D */
1742 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
1743 FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
1744 spk_vol_tlv_arr),
1745 /* R_SUBVOL PG 2 ADDR 0x10 */
1746 SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1747 FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
1748 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1749 SOC_SINGLE("Speaker EQ 2 Switch",
1750 R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
1751 SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
1752 SOC_SINGLE("Speaker EQ 1 Switch",
1753 R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
1754 SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
1755 /* R_SPKMBCEN PG 3 ADDR 0x0A */
1756 SOC_SINGLE("Speaker MBC 3 Switch",
1757 R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
1758 SOC_SINGLE("Speaker MBC 2 Switch",
1759 R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
1760 SOC_SINGLE("Speaker MBC 1 Switch",
1761 R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
1762 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1763 SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
1764 SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
1765 SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
1766 SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
1767 SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
1768 SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
1769 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1770 SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
1771 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1772 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1773 0, mbc_mug_tlv_arr),
1774 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1775 SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
1776 R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1777 0, thr_tlv_arr),
1778 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1779 SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
1780 /* R_SPKMBCATK1L PG 3 ADDR 0x0F */
1781 /* R_SPKMBCATK1H PG 3 ADDR 0x10 */
1782 SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
1783 /* R_SPKMBCREL1L PG 3 ADDR 0x11 */
1784 /* R_SPKMBCREL1H PG 3 ADDR 0x12 */
1785 SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
1786 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1787 SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
1788 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1789 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1790 0, mbc_mug_tlv_arr),
1791 /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
1792 SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
1793 R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1794 0, thr_tlv_arr),
1795 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1796 SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
1797 /* R_SPKMBCATK2L PG 3 ADDR 0x16 */
1798 /* R_SPKMBCATK2H PG 3 ADDR 0x17 */
1799 SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
1800 /* R_SPKMBCREL2L PG 3 ADDR 0x18 */
1801 /* R_SPKMBCREL2H PG 3 ADDR 0x19 */
1802 SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
1803 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1804 SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
1805 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1806 FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1807 0, mbc_mug_tlv_arr),
1808 /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
1809 SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
1810 FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1811 0, thr_tlv_arr),
1812 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1813 SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
1814 /* R_SPKMBCATK3L PG 3 ADDR 0x1D */
1815 /* R_SPKMBCATK3H PG 3 ADDR 0x1E */
1816 SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
1817 /* R_SPKMBCREL3L PG 3 ADDR 0x1F */
1818 /* R_SPKMBCREL3H PG 3 ADDR 0x20 */
1819 SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
1820 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1821 SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
1822 SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
1823 SOC_SINGLE("Speaker CLE Expander Switch",
1824 R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
1825 SOC_SINGLE("Speaker CLE Limiter Switch",
1826 R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
1827 SOC_SINGLE("Speaker CLE Compressor Switch",
1828 R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
1829 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1830 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1831 FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
1832 0, cle_mug_tlv_arr),
1833 /* R_SPKCOMPTHR PG 3 ADDR 0x23 */
1834 SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
1835 FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
1836 0, thr_tlv_arr),
1837 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1838 SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
1839 /* R_SPKCOMPATKL PG 3 ADDR 0x25 */
1840 /* R_SPKCOMPATKH PG 3 ADDR 0x26 */
1841 SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
1842 /* R_SPKCOMPRELL PG 3 ADDR 0x27 */
1843 /* R_SPKCOMPRELH PG 3 ADDR 0x28 */
1844 SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
1845 /* R_SPKLIMTHR PG 3 ADDR 0x29 */
1846 SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
1847 FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
1848 0, thr_tlv_arr),
1849 /* R_SPKLIMTGT PG 3 ADDR 0x2A */
1850 SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
1851 FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
1852 0, thr_tlv_arr),
1853 /* R_SPKLIMATKL PG 3 ADDR 0x2B */
1854 /* R_SPKLIMATKH PG 3 ADDR 0x2C */
1855 SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
1856 /* R_SPKLIMRELL PG 3 ADDR 0x2D */
1857 /* R_SPKLIMRELR PG 3 ADDR 0x2E */
1858 SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
1859 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1860 SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
1861 FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
1862 0, thr_tlv_arr),
1863 /* R_SPKEXPRAT PG 3 ADDR 0x30 */
1864 SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
1865 /* R_SPKEXPATKL PG 3 ADDR 0x31 */
1866 /* R_SPKEXPATKR PG 3 ADDR 0x32 */
1867 SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
1868 /* R_SPKEXPRELL PG 3 ADDR 0x33 */
1869 /* R_SPKEXPRELR PG 3 ADDR 0x34 */
1870 SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
1871 /* R_SPKFXCTL PG 3 ADDR 0x35 */
1872 SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
1873 SOC_SINGLE("Speaker Treble Enhancement Switch",
1874 R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
1875 SOC_SINGLE("Speaker Treble NLF Switch",
1876 R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
1877 SOC_SINGLE("Speaker Bass Enhancement Switch",
1878 R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
1879 SOC_SINGLE("Speaker Bass NLF Switch",
1880 R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
1881 /* R_DACEQFILT PG 4 ADDR 0x01 */
1882 SOC_SINGLE("DAC EQ 2 Switch",
1883 R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
1884 SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
1885 SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
1886 SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
1887 /* R_DACMBCEN PG 4 ADDR 0x0A */
1888 SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
1889 SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
1890 SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
1891 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1892 SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
1893 SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
1894 SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
1895 SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
1896 SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
1897 SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
1898 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1899 SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
1900 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1901 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1902 0, mbc_mug_tlv_arr),
1903 /* R_DACMBCTHR1 PG 4 ADDR 0x0D */
1904 SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
1905 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1906 0, thr_tlv_arr),
1907 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1908 SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
1909 /* R_DACMBCATK1L PG 4 ADDR 0x0F */
1910 /* R_DACMBCATK1H PG 4 ADDR 0x10 */
1911 SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
1912 /* R_DACMBCREL1L PG 4 ADDR 0x11 */
1913 /* R_DACMBCREL1H PG 4 ADDR 0x12 */
1914 SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
1915 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1916 SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
1917 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1918 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1919 0, mbc_mug_tlv_arr),
1920 /* R_DACMBCTHR2 PG 4 ADDR 0x14 */
1921 SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
1922 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1923 0, thr_tlv_arr),
1924 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1925 SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
1926 /* R_DACMBCATK2L PG 4 ADDR 0x16 */
1927 /* R_DACMBCATK2H PG 4 ADDR 0x17 */
1928 SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
1929 /* R_DACMBCREL2L PG 4 ADDR 0x18 */
1930 /* R_DACMBCREL2H PG 4 ADDR 0x19 */
1931 SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
1932 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1933 SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
1934 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1935 FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1936 0, mbc_mug_tlv_arr),
1937 /* R_DACMBCTHR3 PG 4 ADDR 0x1B */
1938 SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
1939 FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1940 0, thr_tlv_arr),
1941 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1942 SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
1943 /* R_DACMBCATK3L PG 4 ADDR 0x1D */
1944 /* R_DACMBCATK3H PG 4 ADDR 0x1E */
1945 SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
1946 /* R_DACMBCREL3L PG 4 ADDR 0x1F */
1947 /* R_DACMBCREL3H PG 4 ADDR 0x20 */
1948 SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
1949 /* R_DACCLECTL PG 4 ADDR 0x21 */
1950 SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
1951 SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
1952 SOC_SINGLE("DAC CLE Expander Switch",
1953 R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
1954 SOC_SINGLE("DAC CLE Limiter Switch",
1955 R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
1956 SOC_SINGLE("DAC CLE Compressor Switch",
1957 R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
1958 /* R_DACCLEMUG PG 4 ADDR 0x22 */
1959 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
1960 FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
1961 0, cle_mug_tlv_arr),
1962 /* R_DACCOMPTHR PG 4 ADDR 0x23 */
1963 SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
1964 FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
1965 0, thr_tlv_arr),
1966 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1967 SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
1968 /* R_DACCOMPATKL PG 4 ADDR 0x25 */
1969 /* R_DACCOMPATKH PG 4 ADDR 0x26 */
1970 SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
1971 /* R_DACCOMPRELL PG 4 ADDR 0x27 */
1972 /* R_DACCOMPRELH PG 4 ADDR 0x28 */
1973 SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
1974 /* R_DACLIMTHR PG 4 ADDR 0x29 */
1975 SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
1976 FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
1977 0, thr_tlv_arr),
1978 /* R_DACLIMTGT PG 4 ADDR 0x2A */
1979 SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
1980 FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
1981 0, thr_tlv_arr),
1982 /* R_DACLIMATKL PG 4 ADDR 0x2B */
1983 /* R_DACLIMATKH PG 4 ADDR 0x2C */
1984 SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
1985 /* R_DACLIMRELL PG 4 ADDR 0x2D */
1986 /* R_DACLIMRELR PG 4 ADDR 0x2E */
1987 SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
1988 /* R_DACEXPTHR PG 4 ADDR 0x2F */
1989 SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
1990 FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
1991 0, thr_tlv_arr),
1992 /* R_DACEXPRAT PG 4 ADDR 0x30 */
1993 SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
1994 /* R_DACEXPATKL PG 4 ADDR 0x31 */
1995 /* R_DACEXPATKR PG 4 ADDR 0x32 */
1996 SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
1997 /* R_DACEXPRELL PG 4 ADDR 0x33 */
1998 /* R_DACEXPRELR PG 4 ADDR 0x34 */
1999 SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
2000 /* R_DACFXCTL PG 4 ADDR 0x35 */
2001 SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
2002 SOC_SINGLE("DAC Treble Enhancement Switch",
2003 R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
2004 SOC_SINGLE("DAC Treble NLF Switch",
2005 R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
2006 SOC_SINGLE("DAC Bass Enhancement Switch",
2007 R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
2008 SOC_SINGLE("DAC Bass NLF Switch",
2009 R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
2010 /* R_SUBEQFILT PG 5 ADDR 0x01 */
2011 SOC_SINGLE("Sub EQ 2 Switch",
2012 R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
2013 SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2014 SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2015 SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2016 /* R_SUBMBCEN PG 5 ADDR 0x0A */
2017 SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2018 SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2019 SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2020 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
2021 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2022 SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2023 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2024 SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2025 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2026 SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2027 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
2028 SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2029 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2030 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2031 0, mbc_mug_tlv_arr),
2032 /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
2033 SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2034 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2035 0, thr_tlv_arr),
2036 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
2037 SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2038 /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
2039 /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
2040 SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2041 /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
2042 /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
2043 SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2044 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
2045 SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2046 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2047 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2048 0, mbc_mug_tlv_arr),
2049 /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
2050 SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2051 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2052 0, thr_tlv_arr),
2053 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
2054 SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2055 /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
2056 /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
2057 SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2058 /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
2059 /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
2060 SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2061 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
2062 SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2063 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2064 FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2065 0, mbc_mug_tlv_arr),
2066 /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
2067 SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2068 FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2069 0, thr_tlv_arr),
2070 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
2071 SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2072 /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
2073 /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
2074 SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2075 /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
2076 /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
2077 SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2078 /* R_SUBCLECTL PG 5 ADDR 0x21 */
2079 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2080 SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2081 SOC_SINGLE("Sub CLE Expander Switch",
2082 R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
2083 SOC_SINGLE("Sub CLE Limiter Switch",
2084 R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
2085 SOC_SINGLE("Sub CLE Compressor Switch",
2086 R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
2087 /* R_SUBCLEMUG PG 5 ADDR 0x22 */
2088 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2089 FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
2090 0, cle_mug_tlv_arr),
2091 /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
2092 SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2093 FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
2094 0, thr_tlv_arr),
2095 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
2096 SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2097 /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
2098 /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
2099 SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2100 /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
2101 /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
2102 SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2103 /* R_SUBLIMTHR PG 5 ADDR 0x29 */
2104 SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2105 FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
2106 0, thr_tlv_arr),
2107 /* R_SUBLIMTGT PG 5 ADDR 0x2A */
2108 SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2109 FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
2110 0, thr_tlv_arr),
2111 /* R_SUBLIMATKL PG 5 ADDR 0x2B */
2112 /* R_SUBLIMATKH PG 5 ADDR 0x2C */
2113 SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2114 /* R_SUBLIMRELL PG 5 ADDR 0x2D */
2115 /* R_SUBLIMRELR PG 5 ADDR 0x2E */
2116 SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2117 /* R_SUBEXPTHR PG 5 ADDR 0x2F */
2118 SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2119 FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
2120 0, thr_tlv_arr),
2121 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
2122 SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2123 /* R_SUBEXPATKL PG 5 ADDR 0x31 */
2124 /* R_SUBEXPATKR PG 5 ADDR 0x32 */
2125 SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2126 /* R_SUBEXPRELL PG 5 ADDR 0x33 */
2127 /* R_SUBEXPRELR PG 5 ADDR 0x34 */
2128 SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2129 /* R_SUBFXCTL PG 5 ADDR 0x35 */
2130 SOC_SINGLE("Sub Treble Enhancement Switch",
2131 R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
2132 SOC_SINGLE("Sub Treble NLF Switch",
2133 R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
2134 SOC_SINGLE("Sub Bass Enhancement Switch",
2135 R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
2136 SOC_SINGLE("Sub Bass NLF Switch",
2137 R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
2138 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2139 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2140 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2141 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2142 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2143 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2144
2145 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2146 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2147 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2148 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2149 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2150 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2151
2152 COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2153 COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2154
2155 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2156 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2157 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2158 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2159 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2160 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2161
2162 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2163 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2164 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2165 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2166 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2167 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2168
2169 COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2170 COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2171
2172 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2173 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2174
2175 COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2176 COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2177
2178 COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2179
2180 COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2181
2182 COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
2183
2184 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2185 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2186
2187 COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2188 COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2189
2190 COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2191
2192 COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2193
2194 COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
2195
2196 COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
2197
2198 COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
2199
2200 COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2201 COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2202
2203 COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2204 COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2205
2206 COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2207 COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2208
2209 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2210 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2211 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2212 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2213 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2214 COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2215
2216 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2217 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2218 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2219 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2220 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2221 COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2222
2223 COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2224 COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2225
2226 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2227 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2228 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2229 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2230 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2231 COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2232
2233 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2234 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2235 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2236 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2237 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2238 COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2239
2240 COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2241 COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2242
2243 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2244 COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2245
2246 COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2247 COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2248
2249 COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2250
2251 COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2252
2253 COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
2254
2255 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2256 COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2257
2258 COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2259 COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2260
2261 COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2262
2263 COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2264
2265 COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
2266
2267 COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
2268
2269 COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
2270
2271 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2272 COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2273
2274 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2275 COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2276
2277 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2278 COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2279
2280 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2281 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2282 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2283 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2284 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2285 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2286
2287 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2288 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2289 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2290 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2291 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2292 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2293
2294 COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2295 COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2296
2297 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2298 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2299 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2300 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2301 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2302 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2303
2304 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2305 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2306 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2307 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2308 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2309 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2310
2311 COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2312 COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2313
2314 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2315 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2316
2317 COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2318 COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2319
2320 COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2321
2322 COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2323
2324 COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2325
2326 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2327 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2328
2329 COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2330 COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2331
2332 COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2333
2334 COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2335
2336 COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2337
2338 COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2339
2340 COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2341
2342 COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2343 COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2344
2345 COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2346 COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2347
2348 COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2349 COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2350 };
2351
2352 static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
2353 /* R_PLLCTL PG 0 ADDR 0x15 */
2354 SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
2355 pll_power_event,
2356 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2357 SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
2358 pll_power_event,
2359 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2360 /* R_I2SPINC0 PG 0 ADDR 0x22 */
2361 SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
2362 R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
2363 SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
2364 R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
2365 SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
2366 R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
2367 /* R_PWRM0 PG 0 ADDR 0x33 */
2368 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2369 R_PWRM0, FB_PWRM0_INPROC3PU, 0),
2370 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2371 R_PWRM0, FB_PWRM0_INPROC2PU, 0),
2372 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2373 R_PWRM0, FB_PWRM0_INPROC1PU, 0),
2374 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2375 R_PWRM0, FB_PWRM0_INPROC0PU, 0),
2376 SND_SOC_DAPM_SUPPLY("Mic Bias 2",
2377 R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
2378 SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
2379 FB_PWRM0_MICB1PU, 0, NULL, 0),
2380 /* R_PWRM1 PG 0 ADDR 0x34 */
2381 SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2382 SND_SOC_DAPM_SUPPLY("Headphone Left Power",
2383 R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
2384 SND_SOC_DAPM_SUPPLY("Headphone Right Power",
2385 R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
2386 SND_SOC_DAPM_SUPPLY("Speaker Left Power",
2387 R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
2388 SND_SOC_DAPM_SUPPLY("Speaker Right Power",
2389 R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
2390 SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
2391 R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
2392 SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
2393 R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
2394 /* R_PWRM2 PG 0 ADDR 0x35 */
2395 SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
2396 R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
2397 SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
2398 R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
2399 SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
2400 R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
2401 SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
2402 R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
2403 SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
2404 R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
2405 SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
2406 R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
2407 /* R_PWRM3 PG 0 ADDR 0x36 */
2408 SND_SOC_DAPM_SUPPLY("Line Out Left Power",
2409 R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
2410 SND_SOC_DAPM_SUPPLY("Line Out Right Power",
2411 R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
2412 /* R_PWRM4 PG 0 ADDR 0x37 */
2413 SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2414 SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
2415 SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
2416 SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
2417 SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
2418 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
2419 SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
2420 &dai2_mux_dapm_enum),
2421 SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
2422 &dai1_mux_dapm_enum),
2423 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
2424 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
2425 &dac_mux_dapm_enum),
2426 SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
2427 &dai3_mux_dapm_enum),
2428 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
2429 SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2430 &sub_mux_dapm_enum),
2431 SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
2432 &classd_mux_dapm_enum),
2433 /* R_HSDCTL1 PG 1 ADDR 0x01 */
2434 SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
2435 FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
2436 /* R_CH0AIC PG 1 ADDR 0x06 */
2437 SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2438 &in_bst_mux_ch0_dapm_enum),
2439 SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2440 &adc_mux_ch0_dapm_enum),
2441 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2442 &in_proc_mux_ch0_dapm_enum),
2443 /* R_CH1AIC PG 1 ADDR 0x07 */
2444 SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2445 &in_bst_mux_ch1_dapm_enum),
2446 SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2447 &adc_mux_ch1_dapm_enum),
2448 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2449 &in_proc_mux_ch1_dapm_enum),
2450 /* Virtual */
2451 SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
2452 SND_SOC_NOPM, 0, 0),
2453 SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
2454 SND_SOC_NOPM, 0, 0),
2455 SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
2456 SND_SOC_NOPM, 0, 0),
2457 SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
2458 SND_SOC_DAPM_OUTPUT("Sub Out"),
2459 SND_SOC_DAPM_OUTPUT("Headphone Left"),
2460 SND_SOC_DAPM_OUTPUT("Headphone Right"),
2461 SND_SOC_DAPM_OUTPUT("Speaker Left"),
2462 SND_SOC_DAPM_OUTPUT("Speaker Right"),
2463 SND_SOC_DAPM_OUTPUT("Line Out Left"),
2464 SND_SOC_DAPM_OUTPUT("Line Out Right"),
2465 SND_SOC_DAPM_INPUT("D2S 2"),
2466 SND_SOC_DAPM_INPUT("D2S 1"),
2467 SND_SOC_DAPM_INPUT("Line In 1 Left"),
2468 SND_SOC_DAPM_INPUT("Line In 1 Right"),
2469 SND_SOC_DAPM_INPUT("Line In 2 Left"),
2470 SND_SOC_DAPM_INPUT("Line In 2 Right"),
2471 SND_SOC_DAPM_INPUT("Line In 3 Left"),
2472 SND_SOC_DAPM_INPUT("Line In 3 Right"),
2473 SND_SOC_DAPM_INPUT("DMic 1"),
2474 SND_SOC_DAPM_INPUT("DMic 2"),
2475
2476 SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
2477 &ch_0_1_mux_dapm_enum),
2478 SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
2479 &ch_2_3_mux_dapm_enum),
2480 SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
2481 &ch_4_5_mux_dapm_enum),
2482 };
2483
2484 static struct snd_soc_dapm_route const tscs454_intercon[] = {
2485 /* PLLs */
2486 {"PLLs", NULL, "PLL 1 Power", pll_connected},
2487 {"PLLs", NULL, "PLL 2 Power", pll_connected},
2488 /* Inputs */
2489 {"DAI 3 In", NULL, "DAI 3 In Power"},
2490 {"DAI 2 In", NULL, "DAI 2 In Power"},
2491 {"DAI 1 In", NULL, "DAI 1 In Power"},
2492 /* Outputs */
2493 {"DAI 3 Out", NULL, "DAI 3 Out Power"},
2494 {"DAI 2 Out", NULL, "DAI 2 Out Power"},
2495 {"DAI 1 Out", NULL, "DAI 1 Out Power"},
2496 /* Ch Muxing */
2497 {"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
2498 {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
2499 {"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
2500 {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
2501 {"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
2502 {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
2503 /* In/Out Muxing */
2504 {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2505 {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2506 {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2507 {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2508 {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2509 {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2510 {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2511 {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2512 {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2513 /******************
2514 * Playback Paths *
2515 ******************/
2516 /* DAC Path */
2517 {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
2518 {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
2519 {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
2520 {"DAC Left", NULL, "DAC Mux"},
2521 {"DAC Right", NULL, "DAC Mux"},
2522 {"DAC Left", NULL, "PLLs"},
2523 {"DAC Right", NULL, "PLLs"},
2524 {"Headphone Left", NULL, "Headphone Left Power"},
2525 {"Headphone Right", NULL, "Headphone Right Power"},
2526 {"Headphone Left", NULL, "DAC Left"},
2527 {"Headphone Right", NULL, "DAC Right"},
2528 /* Line Out */
2529 {"Line Out Left", NULL, "Line Out Left Power"},
2530 {"Line Out Right", NULL, "Line Out Right Power"},
2531 {"Line Out Left", NULL, "DAC Left"},
2532 {"Line Out Right", NULL, "DAC Right"},
2533 /* ClassD Path */
2534 {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
2535 {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
2536 {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
2537 {"ClassD Left", NULL, "Speaker Mux"},
2538 {"ClassD Right", NULL, "Speaker Mux"},
2539 {"ClassD Left", NULL, "PLLs"},
2540 {"ClassD Right", NULL, "PLLs"},
2541 {"Speaker Left", NULL, "Speaker Left Power"},
2542 {"Speaker Right", NULL, "Speaker Right Power"},
2543 {"Speaker Left", NULL, "ClassD Left"},
2544 {"Speaker Right", NULL, "ClassD Right"},
2545 /* Sub Path */
2546 {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2547 {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2548 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2549 {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2550 {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2551 {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2552 {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2553 {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2554 {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2555 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2556 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2557 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2558 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2559 {"Sub Mux", "DMic 2 Left", "DMic 2"},
2560 {"Sub Mux", "DMic 2 Right", "DMic 2"},
2561 {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2562 {"Sub Mux", "ClassD Left", "ClassD Left"},
2563 {"Sub Mux", "ClassD Right", "ClassD Right"},
2564 {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2565 {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2566 {"Sub", NULL, "Sub Mux"},
2567 {"Sub", NULL, "PLLs"},
2568 {"Sub Out", NULL, "Sub Power"},
2569 {"Sub Out", NULL, "Sub"},
2570 /*****************
2571 * Capture Paths *
2572 *****************/
2573 {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
2574 {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
2575 {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
2576 {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
2577
2578 {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
2579 {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
2580 {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
2581 {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
2582
2583 {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
2584 {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
2585 {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
2586 {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
2587
2588 {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
2589 {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
2590 {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
2591 {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
2592
2593 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2594 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2595
2596 {"Input Processor Channel 0", NULL, "PLLs"},
2597 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2598
2599 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2600 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2601
2602 {"Input Processor Channel 1", NULL, "PLLs"},
2603 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2604
2605 {"Input Processor Channel 2", NULL, "PLLs"},
2606 {"Input Processor Channel 2", NULL, "DMic 2"},
2607
2608 {"Input Processor Channel 3", NULL, "PLLs"},
2609 {"Input Processor Channel 3", NULL, "DMic 2"},
2610
2611 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2612 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2613 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2614 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2615
2616 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2617 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2618 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2619 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2620
2621 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2622 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2623 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2624 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2625
2626 {"DAI 1 Out", NULL, "DAI 1 Out Mux"},
2627 {"DAI 2 Out", NULL, "DAI 2 Out Mux"},
2628 {"DAI 3 Out", NULL, "DAI 3 Out Mux"},
2629 };
2630
2631 /* This is used when BCLK is sourcing the PLLs */
tscs454_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2632 static int tscs454_set_sysclk(struct snd_soc_dai *dai,
2633 int clk_id, unsigned int freq, int dir)
2634 {
2635 struct snd_soc_component *component = dai->component;
2636 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2637 unsigned int val;
2638 int bclk_dai;
2639
2640 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
2641
2642 val = snd_soc_component_read(component, R_PLLCTL);
2643
2644 bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
2645 if (bclk_dai != dai->id)
2646 return 0;
2647
2648 tscs454->bclk_freq = freq;
2649 return set_sysclk(component);
2650 }
2651
tscs454_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)2652 static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
2653 unsigned int ratio)
2654 {
2655 unsigned int mask;
2656 int ret;
2657 struct snd_soc_component *component = dai->component;
2658 unsigned int val;
2659 int shift;
2660
2661 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
2662 dai->id, ratio);
2663
2664 switch (dai->id) {
2665 case TSCS454_DAI1_ID:
2666 mask = FM_I2SCMC_BCMP1;
2667 shift = FB_I2SCMC_BCMP1;
2668 break;
2669 case TSCS454_DAI2_ID:
2670 mask = FM_I2SCMC_BCMP2;
2671 shift = FB_I2SCMC_BCMP2;
2672 break;
2673 case TSCS454_DAI3_ID:
2674 mask = FM_I2SCMC_BCMP3;
2675 shift = FB_I2SCMC_BCMP3;
2676 break;
2677 default:
2678 ret = -EINVAL;
2679 dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
2680 return ret;
2681 }
2682
2683 switch (ratio) {
2684 case 32:
2685 val = I2SCMC_BCMP_32X;
2686 break;
2687 case 40:
2688 val = I2SCMC_BCMP_40X;
2689 break;
2690 case 64:
2691 val = I2SCMC_BCMP_64X;
2692 break;
2693 default:
2694 ret = -EINVAL;
2695 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
2696 return ret;
2697 }
2698
2699 ret = snd_soc_component_update_bits(component,
2700 R_I2SCMC, mask, val << shift);
2701 if (ret < 0) {
2702 dev_err(component->dev,
2703 "Failed to set DAI BCLK ratio (%d)\n", ret);
2704 return ret;
2705 }
2706
2707 return 0;
2708 }
2709
set_aif_provider_from_fmt(struct snd_soc_component * component,struct aif * aif,unsigned int fmt)2710 static inline int set_aif_provider_from_fmt(struct snd_soc_component *component,
2711 struct aif *aif, unsigned int fmt)
2712 {
2713 int ret;
2714
2715 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
2716 case SND_SOC_DAIFMT_CBP_CFP:
2717 aif->provider = true;
2718 break;
2719 case SND_SOC_DAIFMT_CBC_CFC:
2720 aif->provider = false;
2721 break;
2722 default:
2723 ret = -EINVAL;
2724 dev_err(component->dev, "Unsupported format (%d)\n", ret);
2725 return ret;
2726 }
2727
2728 return 0;
2729 }
2730
set_aif_tdm_delay(struct snd_soc_component * component,unsigned int dai_id,bool delay)2731 static inline int set_aif_tdm_delay(struct snd_soc_component *component,
2732 unsigned int dai_id, bool delay)
2733 {
2734 unsigned int reg;
2735 int ret;
2736
2737 switch (dai_id) {
2738 case TSCS454_DAI1_ID:
2739 reg = R_TDMCTL0;
2740 break;
2741 case TSCS454_DAI2_ID:
2742 reg = R_PCMP2CTL0;
2743 break;
2744 case TSCS454_DAI3_ID:
2745 reg = R_PCMP3CTL0;
2746 break;
2747 default:
2748 ret = -EINVAL;
2749 dev_err(component->dev,
2750 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2751 return ret;
2752 }
2753 ret = snd_soc_component_update_bits(component,
2754 reg, FM_TDMCTL0_BDELAY, delay);
2755 if (ret < 0) {
2756 dev_err(component->dev, "Failed to setup tdm format (%d)\n",
2757 ret);
2758 return ret;
2759 }
2760
2761 return 0;
2762 }
2763
set_aif_format_from_fmt(struct snd_soc_component * component,unsigned int dai_id,unsigned int fmt)2764 static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
2765 unsigned int dai_id, unsigned int fmt)
2766 {
2767 unsigned int reg;
2768 unsigned int val;
2769 int ret;
2770
2771 switch (dai_id) {
2772 case TSCS454_DAI1_ID:
2773 reg = R_I2SP1CTL;
2774 break;
2775 case TSCS454_DAI2_ID:
2776 reg = R_I2SP2CTL;
2777 break;
2778 case TSCS454_DAI3_ID:
2779 reg = R_I2SP3CTL;
2780 break;
2781 default:
2782 ret = -EINVAL;
2783 dev_err(component->dev,
2784 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2785 return ret;
2786 }
2787
2788 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2789 case SND_SOC_DAIFMT_RIGHT_J:
2790 val = FV_FORMAT_RIGHT;
2791 break;
2792 case SND_SOC_DAIFMT_LEFT_J:
2793 val = FV_FORMAT_LEFT;
2794 break;
2795 case SND_SOC_DAIFMT_I2S:
2796 val = FV_FORMAT_I2S;
2797 break;
2798 case SND_SOC_DAIFMT_DSP_A:
2799 ret = set_aif_tdm_delay(component, dai_id, true);
2800 if (ret < 0)
2801 return ret;
2802 val = FV_FORMAT_TDM;
2803 break;
2804 case SND_SOC_DAIFMT_DSP_B:
2805 ret = set_aif_tdm_delay(component, dai_id, false);
2806 if (ret < 0)
2807 return ret;
2808 val = FV_FORMAT_TDM;
2809 break;
2810 default:
2811 ret = -EINVAL;
2812 dev_err(component->dev, "Format unsupported (%d)\n", ret);
2813 return ret;
2814 }
2815
2816 ret = snd_soc_component_update_bits(component,
2817 reg, FM_I2SPCTL_FORMAT, val);
2818 if (ret < 0) {
2819 dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
2820 dai_id + 1, ret);
2821 return ret;
2822 }
2823
2824 return 0;
2825 }
2826
2827 static inline int
set_aif_clock_format_from_fmt(struct snd_soc_component * component,unsigned int dai_id,unsigned int fmt)2828 set_aif_clock_format_from_fmt(struct snd_soc_component *component,
2829 unsigned int dai_id, unsigned int fmt)
2830 {
2831 unsigned int reg;
2832 unsigned int val;
2833 int ret;
2834
2835 switch (dai_id) {
2836 case TSCS454_DAI1_ID:
2837 reg = R_I2SP1CTL;
2838 break;
2839 case TSCS454_DAI2_ID:
2840 reg = R_I2SP2CTL;
2841 break;
2842 case TSCS454_DAI3_ID:
2843 reg = R_I2SP3CTL;
2844 break;
2845 default:
2846 ret = -EINVAL;
2847 dev_err(component->dev,
2848 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2849 return ret;
2850 }
2851
2852 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2853 case SND_SOC_DAIFMT_NB_NF:
2854 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
2855 break;
2856 case SND_SOC_DAIFMT_NB_IF:
2857 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
2858 break;
2859 case SND_SOC_DAIFMT_IB_NF:
2860 val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
2861 break;
2862 case SND_SOC_DAIFMT_IB_IF:
2863 val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
2864 break;
2865 default:
2866 ret = -EINVAL;
2867 dev_err(component->dev, "Format unknown (%d)\n", ret);
2868 return ret;
2869 }
2870
2871 ret = snd_soc_component_update_bits(component, reg,
2872 FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
2873 if (ret < 0) {
2874 dev_err(component->dev,
2875 "Failed to set clock polarity for DAI%d (%d)\n",
2876 dai_id + 1, ret);
2877 return ret;
2878 }
2879
2880 return 0;
2881 }
2882
tscs454_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2883 static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2884 {
2885 struct snd_soc_component *component = dai->component;
2886 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2887 struct aif *aif = &tscs454->aifs[dai->id];
2888 int ret;
2889
2890 ret = set_aif_provider_from_fmt(component, aif, fmt);
2891 if (ret < 0)
2892 return ret;
2893
2894 ret = set_aif_format_from_fmt(component, dai->id, fmt);
2895 if (ret < 0)
2896 return ret;
2897
2898 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
2899 if (ret < 0)
2900 return ret;
2901
2902 return 0;
2903 }
2904
tscs454_dai1_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2905 static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
2906 unsigned int tx_mask, unsigned int rx_mask, int slots,
2907 int slot_width)
2908 {
2909 struct snd_soc_component *component = dai->component;
2910 unsigned int val;
2911 int ret;
2912
2913 if (!slots)
2914 return 0;
2915
2916 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2917 ret = -EINVAL;
2918 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2919 return ret;
2920 }
2921
2922 switch (slots) {
2923 case 2:
2924 val = FV_TDMSO_2 | FV_TDMSI_2;
2925 break;
2926 case 4:
2927 val = FV_TDMSO_4 | FV_TDMSI_4;
2928 break;
2929 case 6:
2930 val = FV_TDMSO_6 | FV_TDMSI_6;
2931 break;
2932 default:
2933 ret = -EINVAL;
2934 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
2935 return ret;
2936 }
2937
2938 switch (slot_width) {
2939 case 16:
2940 val = val | FV_TDMDSS_16;
2941 break;
2942 case 24:
2943 val = val | FV_TDMDSS_24;
2944 break;
2945 case 32:
2946 val = val | FV_TDMDSS_32;
2947 break;
2948 default:
2949 ret = -EINVAL;
2950 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
2951 return ret;
2952 }
2953 ret = snd_soc_component_write(component, R_TDMCTL1, val);
2954 if (ret < 0) {
2955 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
2956 return ret;
2957 }
2958
2959 return 0;
2960 }
2961
tscs454_dai23_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2962 static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
2963 unsigned int tx_mask, unsigned int rx_mask, int slots,
2964 int slot_width)
2965 {
2966 struct snd_soc_component *component = dai->component;
2967 unsigned int reg;
2968 unsigned int val;
2969 int ret;
2970
2971 if (!slots)
2972 return 0;
2973
2974 if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2975 ret = -EINVAL;
2976 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2977 return ret;
2978 }
2979
2980 switch (dai->id) {
2981 case TSCS454_DAI2_ID:
2982 reg = R_PCMP2CTL1;
2983 break;
2984 case TSCS454_DAI3_ID:
2985 reg = R_PCMP3CTL1;
2986 break;
2987 default:
2988 ret = -EINVAL;
2989 dev_err(component->dev, "Unrecognized interface %d (%d)\n",
2990 dai->id, ret);
2991 return ret;
2992 }
2993
2994 switch (slots) {
2995 case 1:
2996 val = FV_PCMSOP_1 | FV_PCMSIP_1;
2997 break;
2998 case 2:
2999 val = FV_PCMSOP_2 | FV_PCMSIP_2;
3000 break;
3001 default:
3002 ret = -EINVAL;
3003 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
3004 return ret;
3005 }
3006
3007 switch (slot_width) {
3008 case 16:
3009 val = val | FV_PCMDSSP_16;
3010 break;
3011 case 24:
3012 val = val | FV_PCMDSSP_24;
3013 break;
3014 case 32:
3015 val = val | FV_PCMDSSP_32;
3016 break;
3017 default:
3018 ret = -EINVAL;
3019 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
3020 return ret;
3021 }
3022 ret = snd_soc_component_write(component, reg, val);
3023 if (ret < 0) {
3024 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
3025 return ret;
3026 }
3027
3028 return 0;
3029 }
3030
set_aif_fs(struct snd_soc_component * component,unsigned int id,unsigned int rate)3031 static int set_aif_fs(struct snd_soc_component *component,
3032 unsigned int id,
3033 unsigned int rate)
3034 {
3035 unsigned int reg;
3036 unsigned int br;
3037 unsigned int bm;
3038 int ret;
3039
3040 switch (rate) {
3041 case 8000:
3042 br = FV_I2SMBR_32;
3043 bm = FV_I2SMBM_0PT25;
3044 break;
3045 case 16000:
3046 br = FV_I2SMBR_32;
3047 bm = FV_I2SMBM_0PT5;
3048 break;
3049 case 24000:
3050 br = FV_I2SMBR_48;
3051 bm = FV_I2SMBM_0PT5;
3052 break;
3053 case 32000:
3054 br = FV_I2SMBR_32;
3055 bm = FV_I2SMBM_1;
3056 break;
3057 case 48000:
3058 br = FV_I2SMBR_48;
3059 bm = FV_I2SMBM_1;
3060 break;
3061 case 96000:
3062 br = FV_I2SMBR_48;
3063 bm = FV_I2SMBM_2;
3064 break;
3065 case 11025:
3066 br = FV_I2SMBR_44PT1;
3067 bm = FV_I2SMBM_0PT25;
3068 break;
3069 case 22050:
3070 br = FV_I2SMBR_44PT1;
3071 bm = FV_I2SMBM_0PT5;
3072 break;
3073 case 44100:
3074 br = FV_I2SMBR_44PT1;
3075 bm = FV_I2SMBM_1;
3076 break;
3077 case 88200:
3078 br = FV_I2SMBR_44PT1;
3079 bm = FV_I2SMBM_2;
3080 break;
3081 default:
3082 ret = -EINVAL;
3083 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
3084 return ret;
3085 }
3086
3087 switch (id) {
3088 case TSCS454_DAI1_ID:
3089 reg = R_I2S1MRATE;
3090 break;
3091 case TSCS454_DAI2_ID:
3092 reg = R_I2S2MRATE;
3093 break;
3094 case TSCS454_DAI3_ID:
3095 reg = R_I2S3MRATE;
3096 break;
3097 default:
3098 ret = -EINVAL;
3099 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
3100 return ret;
3101 }
3102
3103 ret = snd_soc_component_update_bits(component, reg,
3104 FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
3105 if (ret < 0) {
3106 dev_err(component->dev,
3107 "Failed to update register (%d)\n", ret);
3108 return ret;
3109 }
3110
3111 return 0;
3112 }
3113
set_aif_sample_format(struct snd_soc_component * component,snd_pcm_format_t format,int aif_id)3114 static int set_aif_sample_format(struct snd_soc_component *component,
3115 snd_pcm_format_t format,
3116 int aif_id)
3117 {
3118 unsigned int reg;
3119 unsigned int width;
3120 int ret;
3121
3122 switch (snd_pcm_format_width(format)) {
3123 case 16:
3124 width = FV_WL_16;
3125 break;
3126 case 20:
3127 width = FV_WL_20;
3128 break;
3129 case 24:
3130 width = FV_WL_24;
3131 break;
3132 case 32:
3133 width = FV_WL_32;
3134 break;
3135 default:
3136 ret = -EINVAL;
3137 dev_err(component->dev, "Unsupported format width (%d)\n", ret);
3138 return ret;
3139 }
3140
3141 switch (aif_id) {
3142 case TSCS454_DAI1_ID:
3143 reg = R_I2SP1CTL;
3144 break;
3145 case TSCS454_DAI2_ID:
3146 reg = R_I2SP2CTL;
3147 break;
3148 case TSCS454_DAI3_ID:
3149 reg = R_I2SP3CTL;
3150 break;
3151 default:
3152 ret = -EINVAL;
3153 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
3154 return ret;
3155 }
3156
3157 ret = snd_soc_component_update_bits(component,
3158 reg, FM_I2SPCTL_WL, width);
3159 if (ret < 0) {
3160 dev_err(component->dev,
3161 "Failed to set sample width (%d)\n", ret);
3162 return ret;
3163 }
3164
3165 return 0;
3166 }
3167
tscs454_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)3168 static int tscs454_hw_params(struct snd_pcm_substream *substream,
3169 struct snd_pcm_hw_params *params,
3170 struct snd_soc_dai *dai)
3171 {
3172 struct snd_soc_component *component = dai->component;
3173 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3174 unsigned int fs = params_rate(params);
3175 struct aif *aif = &tscs454->aifs[dai->id];
3176 unsigned int val;
3177 int ret;
3178
3179 mutex_lock(&tscs454->aifs_status_lock);
3180
3181 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
3182 aif->id, fs);
3183
3184 if (!aif_active(&tscs454->aifs_status, aif->id)) {
3185 if (PLL_44_1K_RATE % fs)
3186 aif->pll = &tscs454->pll1;
3187 else
3188 aif->pll = &tscs454->pll2;
3189
3190 dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
3191 aif->pll->id, aif->id);
3192
3193 reserve_pll(aif->pll);
3194 }
3195
3196 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
3197 val = snd_soc_component_read(component, R_ISRC);
3198 if ((val & FM_ISRC_IBR) == FV_IBR_48)
3199 tscs454->internal_rate.pll = &tscs454->pll1;
3200 else
3201 tscs454->internal_rate.pll = &tscs454->pll2;
3202
3203 dev_dbg(component->dev, "Reserving pll %d for ir\n",
3204 tscs454->internal_rate.pll->id);
3205
3206 reserve_pll(tscs454->internal_rate.pll);
3207 }
3208
3209 ret = set_aif_fs(component, aif->id, fs);
3210 if (ret < 0) {
3211 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
3212 goto exit;
3213 }
3214
3215 ret = set_aif_sample_format(component, params_format(params), aif->id);
3216 if (ret < 0) {
3217 dev_err(component->dev,
3218 "Failed to set aif sample format (%d)\n", ret);
3219 goto exit;
3220 }
3221
3222 set_aif_status_active(&tscs454->aifs_status, aif->id,
3223 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3224
3225 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
3226 aif->id, tscs454->aifs_status.streams);
3227
3228 ret = 0;
3229 exit:
3230 mutex_unlock(&tscs454->aifs_status_lock);
3231
3232 return ret;
3233 }
3234
tscs454_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3235 static int tscs454_hw_free(struct snd_pcm_substream *substream,
3236 struct snd_soc_dai *dai)
3237 {
3238 struct snd_soc_component *component = dai->component;
3239 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3240 struct aif *aif = &tscs454->aifs[dai->id];
3241
3242 return aif_free(component, aif,
3243 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3244 }
3245
tscs454_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)3246 static int tscs454_prepare(struct snd_pcm_substream *substream,
3247 struct snd_soc_dai *dai)
3248 {
3249 int ret;
3250 struct snd_soc_component *component = dai->component;
3251 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3252 struct aif *aif = &tscs454->aifs[dai->id];
3253
3254 ret = aif_prepare(component, aif);
3255 if (ret < 0)
3256 return ret;
3257
3258 return 0;
3259 }
3260
3261 static struct snd_soc_dai_ops const tscs454_dai1_ops = {
3262 .set_sysclk = tscs454_set_sysclk,
3263 .set_bclk_ratio = tscs454_set_bclk_ratio,
3264 .set_fmt = tscs454_set_dai_fmt,
3265 .set_tdm_slot = tscs454_dai1_set_tdm_slot,
3266 .hw_params = tscs454_hw_params,
3267 .hw_free = tscs454_hw_free,
3268 .prepare = tscs454_prepare,
3269 };
3270
3271 static struct snd_soc_dai_ops const tscs454_dai23_ops = {
3272 .set_sysclk = tscs454_set_sysclk,
3273 .set_bclk_ratio = tscs454_set_bclk_ratio,
3274 .set_fmt = tscs454_set_dai_fmt,
3275 .set_tdm_slot = tscs454_dai23_set_tdm_slot,
3276 .hw_params = tscs454_hw_params,
3277 .hw_free = tscs454_hw_free,
3278 .prepare = tscs454_prepare,
3279 };
3280
tscs454_probe(struct snd_soc_component * component)3281 static int tscs454_probe(struct snd_soc_component *component)
3282 {
3283 struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3284 unsigned int val;
3285 int ret = 0;
3286
3287 switch (tscs454->sysclk_src_id) {
3288 case PLL_INPUT_XTAL:
3289 val = FV_PLLISEL_XTAL;
3290 break;
3291 case PLL_INPUT_MCLK1:
3292 val = FV_PLLISEL_MCLK1;
3293 break;
3294 case PLL_INPUT_MCLK2:
3295 val = FV_PLLISEL_MCLK2;
3296 break;
3297 case PLL_INPUT_BCLK:
3298 val = FV_PLLISEL_BCLK;
3299 break;
3300 default:
3301 ret = -EINVAL;
3302 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
3303 return ret;
3304 }
3305
3306 ret = snd_soc_component_update_bits(component, R_PLLCTL,
3307 FM_PLLCTL_PLLISEL, val);
3308 if (ret < 0) {
3309 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
3310 return ret;
3311 }
3312
3313 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
3314 ret = set_sysclk(component);
3315
3316 return ret;
3317 }
3318
3319 static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
3320 .probe = tscs454_probe,
3321 .dapm_widgets = tscs454_dapm_widgets,
3322 .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
3323 .dapm_routes = tscs454_intercon,
3324 .num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
3325 .controls = tscs454_snd_controls,
3326 .num_controls = ARRAY_SIZE(tscs454_snd_controls),
3327 .endianness = 1,
3328 };
3329
3330 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
3331
3332 #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
3333 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
3334 | SNDRV_PCM_FMTBIT_S32_LE)
3335
3336 static struct snd_soc_dai_driver tscs454_dais[] = {
3337 {
3338 .name = "tscs454-dai1",
3339 .id = TSCS454_DAI1_ID,
3340 .playback = {
3341 .stream_name = "DAI 1 Playback",
3342 .channels_min = 1,
3343 .channels_max = 6,
3344 .rates = TSCS454_RATES,
3345 .formats = TSCS454_FORMATS,},
3346 .capture = {
3347 .stream_name = "DAI 1 Capture",
3348 .channels_min = 1,
3349 .channels_max = 6,
3350 .rates = TSCS454_RATES,
3351 .formats = TSCS454_FORMATS,},
3352 .ops = &tscs454_dai1_ops,
3353 .symmetric_rate = 1,
3354 .symmetric_channels = 1,
3355 .symmetric_sample_bits = 1,
3356 },
3357 {
3358 .name = "tscs454-dai2",
3359 .id = TSCS454_DAI2_ID,
3360 .playback = {
3361 .stream_name = "DAI 2 Playback",
3362 .channels_min = 1,
3363 .channels_max = 2,
3364 .rates = TSCS454_RATES,
3365 .formats = TSCS454_FORMATS,},
3366 .capture = {
3367 .stream_name = "DAI 2 Capture",
3368 .channels_min = 1,
3369 .channels_max = 2,
3370 .rates = TSCS454_RATES,
3371 .formats = TSCS454_FORMATS,},
3372 .ops = &tscs454_dai23_ops,
3373 .symmetric_rate = 1,
3374 .symmetric_channels = 1,
3375 .symmetric_sample_bits = 1,
3376 },
3377 {
3378 .name = "tscs454-dai3",
3379 .id = TSCS454_DAI3_ID,
3380 .playback = {
3381 .stream_name = "DAI 3 Playback",
3382 .channels_min = 1,
3383 .channels_max = 2,
3384 .rates = TSCS454_RATES,
3385 .formats = TSCS454_FORMATS,},
3386 .capture = {
3387 .stream_name = "DAI 3 Capture",
3388 .channels_min = 1,
3389 .channels_max = 2,
3390 .rates = TSCS454_RATES,
3391 .formats = TSCS454_FORMATS,},
3392 .ops = &tscs454_dai23_ops,
3393 .symmetric_rate = 1,
3394 .symmetric_channels = 1,
3395 .symmetric_sample_bits = 1,
3396 },
3397 };
3398
3399 static char const * const src_names[] = {
3400 "xtal", "mclk1", "mclk2", "bclk"};
3401
tscs454_i2c_probe(struct i2c_client * i2c)3402 static int tscs454_i2c_probe(struct i2c_client *i2c)
3403 {
3404 struct tscs454 *tscs454;
3405 int src;
3406 int ret;
3407
3408 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
3409 if (!tscs454)
3410 return -ENOMEM;
3411
3412 ret = tscs454_data_init(tscs454, i2c);
3413 if (ret < 0)
3414 return ret;
3415
3416 i2c_set_clientdata(i2c, tscs454);
3417
3418 for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
3419 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
3420 if (!IS_ERR(tscs454->sysclk)) {
3421 break;
3422 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
3423 ret = PTR_ERR(tscs454->sysclk);
3424 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
3425 return ret;
3426 }
3427 }
3428 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
3429 tscs454->sysclk_src_id = src;
3430
3431 ret = regmap_write(tscs454->regmap,
3432 R_RESET, FV_RESET_PWR_ON_DEFAULTS);
3433 if (ret < 0) {
3434 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
3435 return ret;
3436 }
3437 regcache_mark_dirty(tscs454->regmap);
3438
3439 ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
3440 ARRAY_SIZE(tscs454_patch));
3441 if (ret < 0) {
3442 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
3443 return ret;
3444 }
3445 /* Sync pg sel reg with cache */
3446 regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
3447
3448 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3449 tscs454_dais, ARRAY_SIZE(tscs454_dais));
3450 if (ret) {
3451 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
3452 return ret;
3453 }
3454
3455 return 0;
3456 }
3457
3458 static const struct i2c_device_id tscs454_i2c_id[] = {
3459 { "tscs454" },
3460 { }
3461 };
3462 MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
3463
3464 static const struct of_device_id tscs454_of_match[] = {
3465 { .compatible = "tempo,tscs454", },
3466 { }
3467 };
3468 MODULE_DEVICE_TABLE(of, tscs454_of_match);
3469
3470 static struct i2c_driver tscs454_i2c_driver = {
3471 .driver = {
3472 .name = "tscs454",
3473 .of_match_table = tscs454_of_match,
3474 },
3475 .probe = tscs454_i2c_probe,
3476 .id_table = tscs454_i2c_id,
3477 };
3478
3479 module_i2c_driver(tscs454_i2c_driver);
3480
3481 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
3482 MODULE_DESCRIPTION("ASoC TSCS454 driver");
3483 MODULE_LICENSE("GPL v2");
3484