1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mt6358.c -- mt6358 ALSA SoC audio codec driver
4 //
5 // Copyright (c) 2018 MediaTek Inc.
6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8 #include <linux/platform_device.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/module.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/sched.h>
14 #include <linux/mfd/mt6397/core.h>
15 #include <linux/regulator/consumer.h>
16
17 #include <sound/soc.h>
18 #include <sound/tlv.h>
19
20 #include "mt6358.h"
21
22 enum {
23 AUDIO_ANALOG_VOLUME_HSOUTL,
24 AUDIO_ANALOG_VOLUME_HSOUTR,
25 AUDIO_ANALOG_VOLUME_HPOUTL,
26 AUDIO_ANALOG_VOLUME_HPOUTR,
27 AUDIO_ANALOG_VOLUME_LINEOUTL,
28 AUDIO_ANALOG_VOLUME_LINEOUTR,
29 AUDIO_ANALOG_VOLUME_MICAMP1,
30 AUDIO_ANALOG_VOLUME_MICAMP2,
31 AUDIO_ANALOG_VOLUME_TYPE_MAX
32 };
33
34 enum {
35 MUX_ADC_L,
36 MUX_ADC_R,
37 MUX_PGA_L,
38 MUX_PGA_R,
39 MUX_MIC_TYPE,
40 MUX_HP_L,
41 MUX_HP_R,
42 MUX_NUM,
43 };
44
45 enum {
46 DEVICE_HP,
47 DEVICE_LO,
48 DEVICE_RCV,
49 DEVICE_MIC1,
50 DEVICE_MIC2,
51 DEVICE_NUM
52 };
53
54 /* Supply widget subseq */
55 enum {
56 /* common */
57 SUPPLY_SEQ_CLK_BUF,
58 SUPPLY_SEQ_AUD_GLB,
59 SUPPLY_SEQ_CLKSQ,
60 SUPPLY_SEQ_VOW_AUD_LPW,
61 SUPPLY_SEQ_AUD_VOW,
62 SUPPLY_SEQ_VOW_CLK,
63 SUPPLY_SEQ_VOW_LDO,
64 SUPPLY_SEQ_TOP_CK,
65 SUPPLY_SEQ_TOP_CK_LAST,
66 SUPPLY_SEQ_AUD_TOP,
67 SUPPLY_SEQ_AUD_TOP_LAST,
68 SUPPLY_SEQ_AFE,
69 /* capture */
70 SUPPLY_SEQ_ADC_SUPPLY,
71 };
72
73 enum {
74 CH_L = 0,
75 CH_R,
76 NUM_CH,
77 };
78
79 #define REG_STRIDE 2
80
81 struct mt6358_priv {
82 struct device *dev;
83 struct regmap *regmap;
84
85 unsigned int dl_rate;
86 unsigned int ul_rate;
87
88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
89 unsigned int mux_select[MUX_NUM];
90
91 int dev_counter[DEVICE_NUM];
92
93 int mtkaif_protocol;
94
95 struct regulator *avdd_reg;
96
97 int wov_enabled;
98
99 int dmic_one_wire_mode;
100 };
101
mt6358_set_mtkaif_protocol(struct snd_soc_component * cmpnt,int mtkaif_protocol)102 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
103 int mtkaif_protocol)
104 {
105 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
106
107 priv->mtkaif_protocol = mtkaif_protocol;
108 return 0;
109 }
110 EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol);
111
playback_gpio_set(struct mt6358_priv * priv)112 static void playback_gpio_set(struct mt6358_priv *priv)
113 {
114 /* set gpio mosi mode */
115 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
116 0x01f8, 0x01f8);
117 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
118 0xffff, 0x0249);
119 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
120 0xffff, 0x0249);
121 }
122
playback_gpio_reset(struct mt6358_priv * priv)123 static void playback_gpio_reset(struct mt6358_priv *priv)
124 {
125 /* set pad_aud_*_mosi to GPIO mode and dir input
126 * reason:
127 * pad_aud_dat_mosi*, because the pin is used as boot strap
128 * don't clean clk/sync, for mtkaif protocol 2
129 */
130 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
131 0x01f8, 0x01f8);
132 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
133 0x01f8, 0x0000);
134 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
135 0xf << 8, 0x0);
136 }
137
capture_gpio_set(struct mt6358_priv * priv)138 static void capture_gpio_set(struct mt6358_priv *priv)
139 {
140 /* set gpio miso mode */
141 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
142 0xffff, 0xffff);
143 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
144 0xffff, 0x0249);
145 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
146 0xffff, 0x0249);
147 }
148
capture_gpio_reset(struct mt6358_priv * priv)149 static void capture_gpio_reset(struct mt6358_priv *priv)
150 {
151 /* set pad_aud_*_miso to GPIO mode and dir input
152 * reason:
153 * pad_aud_clk_miso, because when playback only the miso_clk
154 * will also have 26m, so will have power leak
155 * pad_aud_dat_miso*, because the pin is used as boot strap
156 */
157 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
158 0xffff, 0xffff);
159 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
160 0xffff, 0x0000);
161 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
162 0xf << 12, 0x0);
163 }
164
mt6358_mtkaif_tx_enable(struct mt6358_priv * priv)165 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
166 {
167 switch (priv->mtkaif_protocol) {
168 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
169 /* MTKAIF TX format setting */
170 regmap_update_bits(priv->regmap,
171 MT6358_AFE_ADDA_MTKAIF_CFG0,
172 0xffff, 0x0010);
173 /* enable aud_pad TX fifos */
174 regmap_update_bits(priv->regmap,
175 MT6358_AFE_AUD_PAD_TOP,
176 0xff00, 0x3800);
177 regmap_update_bits(priv->regmap,
178 MT6358_AFE_AUD_PAD_TOP,
179 0xff00, 0x3900);
180 break;
181 case MT6358_MTKAIF_PROTOCOL_2:
182 /* MTKAIF TX format setting */
183 regmap_update_bits(priv->regmap,
184 MT6358_AFE_ADDA_MTKAIF_CFG0,
185 0xffff, 0x0010);
186 /* enable aud_pad TX fifos */
187 regmap_update_bits(priv->regmap,
188 MT6358_AFE_AUD_PAD_TOP,
189 0xff00, 0x3100);
190 break;
191 case MT6358_MTKAIF_PROTOCOL_1:
192 default:
193 /* MTKAIF TX format setting */
194 regmap_update_bits(priv->regmap,
195 MT6358_AFE_ADDA_MTKAIF_CFG0,
196 0xffff, 0x0000);
197 /* enable aud_pad TX fifos */
198 regmap_update_bits(priv->regmap,
199 MT6358_AFE_AUD_PAD_TOP,
200 0xff00, 0x3100);
201 break;
202 }
203 return 0;
204 }
205
mt6358_mtkaif_tx_disable(struct mt6358_priv * priv)206 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
207 {
208 /* disable aud_pad TX fifos */
209 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
210 0xff00, 0x3000);
211 return 0;
212 }
213
214 /* dl pga gain */
215 enum {
216 DL_GAIN_8DB = 0,
217 DL_GAIN_0DB = 8,
218 DL_GAIN_N_1DB = 9,
219 DL_GAIN_N_10DB = 18,
220 DL_GAIN_N_40DB = 0x1f,
221 };
222
223 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
224 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
225 #define DL_GAIN_REG_MASK 0x0f9f
226
hp_zcd_disable(struct mt6358_priv * priv)227 static void hp_zcd_disable(struct mt6358_priv *priv)
228 {
229 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
230 }
231
hp_main_output_ramp(struct mt6358_priv * priv,bool up)232 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
233 {
234 int i, stage;
235 int target = 7;
236
237 /* Enable/Reduce HPL/R main output stage step by step */
238 for (i = 0; i <= target; i++) {
239 stage = up ? i : target - i;
240 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
241 0x7 << 8, stage << 8);
242 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
243 0x7 << 11, stage << 11);
244 usleep_range(100, 150);
245 }
246 }
247
hp_aux_feedback_loop_gain_ramp(struct mt6358_priv * priv,bool up)248 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
249 {
250 int i, stage;
251
252 /* Reduce HP aux feedback loop gain step by step */
253 for (i = 0; i <= 0xf; i++) {
254 stage = up ? i : 0xf - i;
255 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
256 0xf << 12, stage << 12);
257 usleep_range(100, 150);
258 }
259 }
260
hp_pull_down(struct mt6358_priv * priv,bool enable)261 static void hp_pull_down(struct mt6358_priv *priv, bool enable)
262 {
263 int i;
264
265 if (enable) {
266 for (i = 0x0; i <= 0x6; i++) {
267 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
268 0x7, i);
269 usleep_range(600, 700);
270 }
271 } else {
272 for (i = 0x6; i >= 0x1; i--) {
273 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
274 0x7, i);
275 usleep_range(600, 700);
276 }
277 }
278 }
279
is_valid_hp_pga_idx(int reg_idx)280 static bool is_valid_hp_pga_idx(int reg_idx)
281 {
282 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
283 reg_idx == DL_GAIN_N_40DB;
284 }
285
headset_volume_ramp(struct mt6358_priv * priv,int from,int to)286 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
287 {
288 int offset = 0, count = 0, reg_idx;
289
290 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
291 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
292 __func__, from, to);
293
294 dev_info(priv->dev, "%s(), from %d, to %d\n",
295 __func__, from, to);
296
297 if (to > from)
298 offset = to - from;
299 else
300 offset = from - to;
301
302 while (offset >= 0) {
303 if (to > from)
304 reg_idx = from + count;
305 else
306 reg_idx = from - count;
307
308 if (is_valid_hp_pga_idx(reg_idx)) {
309 regmap_update_bits(priv->regmap,
310 MT6358_ZCD_CON2,
311 DL_GAIN_REG_MASK,
312 (reg_idx << 7) | reg_idx);
313 usleep_range(200, 300);
314 }
315 offset--;
316 count++;
317 }
318 }
319
mt6358_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)320 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
321 struct snd_ctl_elem_value *ucontrol)
322 {
323 struct snd_soc_component *component =
324 snd_soc_kcontrol_component(kcontrol);
325 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
326 struct soc_mixer_control *mc =
327 (struct soc_mixer_control *)kcontrol->private_value;
328 unsigned int reg = 0;
329 int ret;
330
331 ret = snd_soc_put_volsw(kcontrol, ucontrol);
332 if (ret < 0)
333 return ret;
334
335 switch (mc->reg) {
336 case MT6358_ZCD_CON2:
337 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®);
338 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
339 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
340 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
341 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
342 break;
343 case MT6358_ZCD_CON1:
344 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®);
345 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
346 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
347 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
348 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
349 break;
350 case MT6358_ZCD_CON3:
351 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®);
352 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
353 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
354 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
355 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
356 break;
357 case MT6358_AUDENC_ANA_CON0:
358 case MT6358_AUDENC_ANA_CON1:
359 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®);
360 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
361 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
362 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®);
363 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
364 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
365 break;
366 }
367
368 return ret;
369 }
370
371 static void mt6358_restore_pga(struct mt6358_priv *priv);
372
mt6358_enable_wov_phase2(struct mt6358_priv * priv)373 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv)
374 {
375 /* analog */
376 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
377 0xffff, 0x0000);
378 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
379 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
380 0xffff, 0x0800);
381 mt6358_restore_pga(priv);
382
383 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929);
384 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
385 0xffff, 0x0025);
386 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
387 0xffff, 0x0005);
388
389 /* digital */
390 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
391 0xffff, 0x0000);
392 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120);
393 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff);
394 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200);
395 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424);
396 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac);
397 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e);
398 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000);
399 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
400 0xffff, 0x0000);
401 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
402 0xffff, 0x0451);
403 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1);
404
405 return 0;
406 }
407
mt6358_disable_wov_phase2(struct mt6358_priv * priv)408 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv)
409 {
410 /* digital */
411 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000);
412 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
413 0xffff, 0x0450);
414 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
415 0xffff, 0x0c00);
416 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100);
417 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c);
418 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879);
419 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323);
420 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400);
421 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000);
422 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8);
423 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
424 0xffff, 0x0000);
425
426 /* analog */
427 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
428 0xffff, 0x0004);
429 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
430 0xffff, 0x0000);
431 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829);
432 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
433 0xffff, 0x0000);
434 mt6358_restore_pga(priv);
435 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
436 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
437 0xffff, 0x0010);
438
439 return 0;
440 }
441
mt6358_get_wov(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)442 static int mt6358_get_wov(struct snd_kcontrol *kcontrol,
443 struct snd_ctl_elem_value *ucontrol)
444 {
445 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
446 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
447
448 ucontrol->value.integer.value[0] = priv->wov_enabled;
449 return 0;
450 }
451
mt6358_put_wov(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)452 static int mt6358_put_wov(struct snd_kcontrol *kcontrol,
453 struct snd_ctl_elem_value *ucontrol)
454 {
455 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
456 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
457 int enabled = ucontrol->value.integer.value[0];
458
459 if (enabled < 0 || enabled > 1)
460 return -EINVAL;
461
462 if (priv->wov_enabled != enabled) {
463 if (enabled)
464 mt6358_enable_wov_phase2(priv);
465 else
466 mt6358_disable_wov_phase2(priv);
467
468 priv->wov_enabled = enabled;
469
470 return 1;
471 }
472
473 return 0;
474 }
475
mt6358_dmic_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)476 static int mt6358_dmic_mode_get(struct snd_kcontrol *kcontrol,
477 struct snd_ctl_elem_value *ucontrol)
478 {
479 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
480 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
481
482 ucontrol->value.integer.value[0] = priv->dmic_one_wire_mode;
483 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode);
484
485 return 0;
486 }
487
mt6358_dmic_mode_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)488 static int mt6358_dmic_mode_set(struct snd_kcontrol *kcontrol,
489 struct snd_ctl_elem_value *ucontrol)
490 {
491 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
492 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
493 int enabled = ucontrol->value.integer.value[0];
494
495 if (enabled < 0 || enabled > 1)
496 return -EINVAL;
497
498 if (priv->dmic_one_wire_mode != enabled) {
499 priv->dmic_one_wire_mode = enabled;
500 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode);
501
502 return 1;
503 }
504 dev_dbg(priv->dev, "%s() dmic_mode = %d", __func__, priv->dmic_one_wire_mode);
505
506 return 0;
507 }
508
509 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
510 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
511
512 static const struct snd_kcontrol_new mt6358_snd_controls[] = {
513 /* dl pga gain */
514 SOC_DOUBLE_EXT_TLV("Headphone Volume",
515 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
516 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
517 SOC_DOUBLE_EXT_TLV("Lineout Volume",
518 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
519 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
520 SOC_SINGLE_EXT_TLV("Handset Volume",
521 MT6358_ZCD_CON3, 0, 0x12, 1,
522 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
523 /* ul pga gain */
524 SOC_DOUBLE_R_EXT_TLV("PGA Volume",
525 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
526 8, 4, 0,
527 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
528
529 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
530 mt6358_get_wov, mt6358_put_wov),
531
532 SOC_SINGLE_BOOL_EXT("Dmic Mode Switch", 0,
533 mt6358_dmic_mode_get, mt6358_dmic_mode_set),
534 };
535
536 /* MUX */
537 /* LOL MUX */
538 static const char * const lo_in_mux_map[] = {
539 "Open", "Mute", "Playback", "Test Mode"
540 };
541
542 static int lo_in_mux_map_value[] = {
543 0x0, 0x1, 0x2, 0x3,
544 };
545
546 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
547 MT6358_AUDDEC_ANA_CON7,
548 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
549 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
550 lo_in_mux_map,
551 lo_in_mux_map_value);
552
553 static const struct snd_kcontrol_new lo_in_mux_control =
554 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
555
556 /*HP MUX */
557 enum {
558 HP_MUX_OPEN = 0,
559 HP_MUX_HPSPK,
560 HP_MUX_HP,
561 HP_MUX_TEST_MODE,
562 HP_MUX_HP_IMPEDANCE,
563 HP_MUX_MASK = 0x7,
564 };
565
566 static const char * const hp_in_mux_map[] = {
567 "Open",
568 "LoudSPK Playback",
569 "Audio Playback",
570 "Test Mode",
571 "HP Impedance",
572 };
573
574 static int hp_in_mux_map_value[] = {
575 HP_MUX_OPEN,
576 HP_MUX_HPSPK,
577 HP_MUX_HP,
578 HP_MUX_TEST_MODE,
579 HP_MUX_HP_IMPEDANCE,
580 };
581
582 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
583 SND_SOC_NOPM,
584 0,
585 HP_MUX_MASK,
586 hp_in_mux_map,
587 hp_in_mux_map_value);
588
589 static const struct snd_kcontrol_new hpl_in_mux_control =
590 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
591
592 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
593 SND_SOC_NOPM,
594 0,
595 HP_MUX_MASK,
596 hp_in_mux_map,
597 hp_in_mux_map_value);
598
599 static const struct snd_kcontrol_new hpr_in_mux_control =
600 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
601
602 /* RCV MUX */
603 enum {
604 RCV_MUX_OPEN = 0,
605 RCV_MUX_MUTE,
606 RCV_MUX_VOICE_PLAYBACK,
607 RCV_MUX_TEST_MODE,
608 RCV_MUX_MASK = 0x3,
609 };
610
611 static const char * const rcv_in_mux_map[] = {
612 "Open", "Mute", "Voice Playback", "Test Mode"
613 };
614
615 static int rcv_in_mux_map_value[] = {
616 RCV_MUX_OPEN,
617 RCV_MUX_MUTE,
618 RCV_MUX_VOICE_PLAYBACK,
619 RCV_MUX_TEST_MODE,
620 };
621
622 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
623 SND_SOC_NOPM,
624 0,
625 RCV_MUX_MASK,
626 rcv_in_mux_map,
627 rcv_in_mux_map_value);
628
629 static const struct snd_kcontrol_new rcv_in_mux_control =
630 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
631
632 /* DAC In MUX */
633 static const char * const dac_in_mux_map[] = {
634 "Normal Path", "Sgen"
635 };
636
637 static int dac_in_mux_map_value[] = {
638 0x0, 0x1,
639 };
640
641 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
642 MT6358_AFE_TOP_CON0,
643 DL_SINE_ON_SFT,
644 DL_SINE_ON_MASK,
645 dac_in_mux_map,
646 dac_in_mux_map_value);
647
648 static const struct snd_kcontrol_new dac_in_mux_control =
649 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
650
651 /* AIF Out MUX */
652 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
653 MT6358_AFE_TOP_CON0,
654 UL_SINE_ON_SFT,
655 UL_SINE_ON_MASK,
656 dac_in_mux_map,
657 dac_in_mux_map_value);
658
659 static const struct snd_kcontrol_new aif_out_mux_control =
660 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
661
662 /* Mic Type MUX */
663 enum {
664 MIC_TYPE_MUX_IDLE = 0,
665 MIC_TYPE_MUX_ACC,
666 MIC_TYPE_MUX_DMIC,
667 MIC_TYPE_MUX_DCC,
668 MIC_TYPE_MUX_DCC_ECM_DIFF,
669 MIC_TYPE_MUX_DCC_ECM_SINGLE,
670 MIC_TYPE_MUX_MASK = 0x7,
671 };
672
673 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
674 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
675 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
676
677 static const char * const mic_type_mux_map[] = {
678 "Idle",
679 "ACC",
680 "DMIC",
681 "DCC",
682 "DCC_ECM_DIFF",
683 "DCC_ECM_SINGLE",
684 };
685
686 static int mic_type_mux_map_value[] = {
687 MIC_TYPE_MUX_IDLE,
688 MIC_TYPE_MUX_ACC,
689 MIC_TYPE_MUX_DMIC,
690 MIC_TYPE_MUX_DCC,
691 MIC_TYPE_MUX_DCC_ECM_DIFF,
692 MIC_TYPE_MUX_DCC_ECM_SINGLE,
693 };
694
695 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
696 SND_SOC_NOPM,
697 0,
698 MIC_TYPE_MUX_MASK,
699 mic_type_mux_map,
700 mic_type_mux_map_value);
701
702 static const struct snd_kcontrol_new mic_type_mux_control =
703 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
704
705 /* ADC L MUX */
706 enum {
707 ADC_MUX_IDLE = 0,
708 ADC_MUX_AIN0,
709 ADC_MUX_PREAMPLIFIER,
710 ADC_MUX_IDLE1,
711 ADC_MUX_MASK = 0x3,
712 };
713
714 static const char * const adc_left_mux_map[] = {
715 "Idle", "AIN0", "Left Preamplifier", "Idle_1"
716 };
717
718 static int adc_mux_map_value[] = {
719 ADC_MUX_IDLE,
720 ADC_MUX_AIN0,
721 ADC_MUX_PREAMPLIFIER,
722 ADC_MUX_IDLE1,
723 };
724
725 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
726 SND_SOC_NOPM,
727 0,
728 ADC_MUX_MASK,
729 adc_left_mux_map,
730 adc_mux_map_value);
731
732 static const struct snd_kcontrol_new adc_left_mux_control =
733 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
734
735 /* ADC R MUX */
736 static const char * const adc_right_mux_map[] = {
737 "Idle", "AIN0", "Right Preamplifier", "Idle_1"
738 };
739
740 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
741 SND_SOC_NOPM,
742 0,
743 ADC_MUX_MASK,
744 adc_right_mux_map,
745 adc_mux_map_value);
746
747 static const struct snd_kcontrol_new adc_right_mux_control =
748 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
749
750 /* PGA L MUX */
751 enum {
752 PGA_MUX_NONE = 0,
753 PGA_MUX_AIN0,
754 PGA_MUX_AIN1,
755 PGA_MUX_AIN2,
756 PGA_MUX_MASK = 0x3,
757 };
758
759 static const char * const pga_mux_map[] = {
760 "None", "AIN0", "AIN1", "AIN2"
761 };
762
763 static int pga_mux_map_value[] = {
764 PGA_MUX_NONE,
765 PGA_MUX_AIN0,
766 PGA_MUX_AIN1,
767 PGA_MUX_AIN2,
768 };
769
770 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
771 SND_SOC_NOPM,
772 0,
773 PGA_MUX_MASK,
774 pga_mux_map,
775 pga_mux_map_value);
776
777 static const struct snd_kcontrol_new pga_left_mux_control =
778 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
779
780 /* PGA R MUX */
781 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
782 SND_SOC_NOPM,
783 0,
784 PGA_MUX_MASK,
785 pga_mux_map,
786 pga_mux_map_value);
787
788 static const struct snd_kcontrol_new pga_right_mux_control =
789 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
790
mt_clksq_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)791 static int mt_clksq_event(struct snd_soc_dapm_widget *w,
792 struct snd_kcontrol *kcontrol,
793 int event)
794 {
795 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
796 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
797
798 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
799
800 switch (event) {
801 case SND_SOC_DAPM_PRE_PMU:
802 /* audio clk source from internal dcxo */
803 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
804 RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
805 0x0);
806 break;
807 default:
808 break;
809 }
810
811 return 0;
812 }
813
mt_sgen_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)814 static int mt_sgen_event(struct snd_soc_dapm_widget *w,
815 struct snd_kcontrol *kcontrol,
816 int event)
817 {
818 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
819 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
820
821 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
822
823 switch (event) {
824 case SND_SOC_DAPM_PRE_PMU:
825 /* sdm audio fifo clock power on */
826 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
827 /* scrambler clock on enable */
828 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
829 /* sdm power on */
830 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
831 /* sdm fifo enable */
832 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
833
834 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
835 0xff3f,
836 0x0000);
837 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
838 0xffff,
839 0x0001);
840 break;
841 case SND_SOC_DAPM_POST_PMD:
842 /* DL scrambler disabling sequence */
843 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
844 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
845 break;
846 default:
847 break;
848 }
849
850 return 0;
851 }
852
mt_aif_in_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)853 static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
854 struct snd_kcontrol *kcontrol,
855 int event)
856 {
857 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
858 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
859
860 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
861 __func__, event, priv->dl_rate);
862
863 switch (event) {
864 case SND_SOC_DAPM_PRE_PMU:
865 playback_gpio_set(priv);
866
867 /* sdm audio fifo clock power on */
868 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
869 /* scrambler clock on enable */
870 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
871 /* sdm power on */
872 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
873 /* sdm fifo enable */
874 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
875 break;
876 case SND_SOC_DAPM_POST_PMD:
877 /* DL scrambler disabling sequence */
878 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
879 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
880
881 playback_gpio_reset(priv);
882 break;
883 default:
884 break;
885 }
886
887 return 0;
888 }
889
mtk_hp_enable(struct mt6358_priv * priv)890 static int mtk_hp_enable(struct mt6358_priv *priv)
891 {
892 /* Pull-down HPL/R to AVSS28_AUD */
893 hp_pull_down(priv, true);
894 /* release HP CMFB gate rstb */
895 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
896 0x1 << 6, 0x1 << 6);
897
898 /* Reduce ESD resistance of AU_REFN */
899 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
900
901 /* Set HPR/HPL gain as minimum (~ -40dB) */
902 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
903
904 /* Turn on DA_600K_NCP_VA18 */
905 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
906 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
907 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
908 /* Toggle RG_DIVCKS_CHG */
909 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
910 /* Set NCP soft start mode as default mode: 100us */
911 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
912 /* Enable NCP */
913 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
914 usleep_range(250, 270);
915
916 /* Enable cap-less LDOs (1.5V) */
917 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
918 0x1055, 0x1055);
919 /* Enable NV regulator (-1.2V) */
920 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
921 usleep_range(100, 120);
922
923 /* Disable AUD_ZCD */
924 hp_zcd_disable(priv);
925
926 /* Disable headphone short-circuit protection */
927 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
928
929 /* Enable IBIST */
930 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
931
932 /* Set HP DR bias current optimization, 010: 6uA */
933 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
934 /* Set HP & ZCD bias current optimization */
935 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
936 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
937 /* Set HPP/N STB enhance circuits */
938 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
939
940 /* Enable HP aux output stage */
941 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
942 /* Enable HP aux feedback loop */
943 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
944 /* Enable HP aux CMFB loop */
945 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
946 /* Enable HP driver bias circuits */
947 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
948 /* Enable HP driver core circuits */
949 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
950 /* Short HP main output to HP aux output stage */
951 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
952
953 /* Enable HP main CMFB loop */
954 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
955 /* Disable HP aux CMFB loop */
956 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
957
958 /* Select CMFB resistor bulk to AC mode */
959 /* Selec HS/LO cap size (6.5pF default) */
960 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
961
962 /* Enable HP main output stage */
963 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
964 /* Enable HPR/L main output stage step by step */
965 hp_main_output_ramp(priv, true);
966
967 /* Reduce HP aux feedback loop gain */
968 hp_aux_feedback_loop_gain_ramp(priv, true);
969 /* Disable HP aux feedback loop */
970 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
971
972 /* apply volume setting */
973 headset_volume_ramp(priv,
974 DL_GAIN_N_10DB,
975 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
976
977 /* Disable HP aux output stage */
978 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
979 /* Unshort HP main output to HP aux output stage */
980 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
981 usleep_range(100, 120);
982
983 /* Enable AUD_CLK */
984 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
985 /* Enable Audio DAC */
986 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
987 /* Enable low-noise mode of DAC */
988 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
989 usleep_range(100, 120);
990
991 /* Switch HPL MUX to audio DAC */
992 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
993 /* Switch HPR MUX to audio DAC */
994 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
995
996 /* Disable Pull-down HPL/R to AVSS28_AUD */
997 hp_pull_down(priv, false);
998
999 return 0;
1000 }
1001
mtk_hp_disable(struct mt6358_priv * priv)1002 static int mtk_hp_disable(struct mt6358_priv *priv)
1003 {
1004 /* Pull-down HPL/R to AVSS28_AUD */
1005 hp_pull_down(priv, true);
1006
1007 /* HPR/HPL mux to open */
1008 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1009 0x0f00, 0x0000);
1010
1011 /* Disable low-noise mode of DAC */
1012 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1013 0x0001, 0x0000);
1014
1015 /* Disable Audio DAC */
1016 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1017 0x000f, 0x0000);
1018
1019 /* Disable AUD_CLK */
1020 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1021
1022 /* Short HP main output to HP aux output stage */
1023 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1024 /* Enable HP aux output stage */
1025 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1026
1027 /* decrease HPL/R gain to normal gain step by step */
1028 headset_volume_ramp(priv,
1029 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1030 DL_GAIN_N_40DB);
1031
1032 /* Enable HP aux feedback loop */
1033 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1034
1035 /* Reduce HP aux feedback loop gain */
1036 hp_aux_feedback_loop_gain_ramp(priv, false);
1037
1038 /* decrease HPR/L main output stage step by step */
1039 hp_main_output_ramp(priv, false);
1040
1041 /* Disable HP main output stage */
1042 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1043
1044 /* Enable HP aux CMFB loop */
1045 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1046
1047 /* Disable HP main CMFB loop */
1048 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1049
1050 /* Unshort HP main output to HP aux output stage */
1051 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1052 0x3 << 6, 0x0);
1053
1054 /* Disable HP driver core circuits */
1055 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1056 0x3 << 4, 0x0);
1057
1058 /* Disable HP driver bias circuits */
1059 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1060 0x3 << 6, 0x0);
1061
1062 /* Disable HP aux CMFB loop */
1063 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1064
1065 /* Disable HP aux feedback loop */
1066 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1067 0x3 << 4, 0x0);
1068
1069 /* Disable HP aux output stage */
1070 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1071 0x3 << 2, 0x0);
1072
1073 /* Disable IBIST */
1074 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1075 0x1 << 8, 0x1 << 8);
1076
1077 /* Disable NV regulator (-1.2V) */
1078 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1079 /* Disable cap-less LDOs (1.5V) */
1080 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1081 0x1055, 0x0);
1082 /* Disable NCP */
1083 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1084 0x1, 0x1);
1085
1086 /* Increase ESD resistance of AU_REFN */
1087 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1088 0x1 << 14, 0x0);
1089
1090 /* Set HP CMFB gate rstb */
1091 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1092 0x1 << 6, 0x0);
1093 /* disable Pull-down HPL/R to AVSS28_AUD */
1094 hp_pull_down(priv, false);
1095
1096 return 0;
1097 }
1098
mtk_hp_spk_enable(struct mt6358_priv * priv)1099 static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1100 {
1101 /* Pull-down HPL/R to AVSS28_AUD */
1102 hp_pull_down(priv, true);
1103 /* release HP CMFB gate rstb */
1104 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1105 0x1 << 6, 0x1 << 6);
1106
1107 /* Reduce ESD resistance of AU_REFN */
1108 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1109
1110 /* Set HPR/HPL gain to -10dB */
1111 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1112
1113 /* Turn on DA_600K_NCP_VA18 */
1114 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1115 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1116 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1117 /* Toggle RG_DIVCKS_CHG */
1118 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1119 /* Set NCP soft start mode as default mode: 100us */
1120 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1121 /* Enable NCP */
1122 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1123 usleep_range(250, 270);
1124
1125 /* Enable cap-less LDOs (1.5V) */
1126 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1127 0x1055, 0x1055);
1128 /* Enable NV regulator (-1.2V) */
1129 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1130 usleep_range(100, 120);
1131
1132 /* Disable AUD_ZCD */
1133 hp_zcd_disable(priv);
1134
1135 /* Disable headphone short-circuit protection */
1136 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1137
1138 /* Enable IBIST */
1139 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1140
1141 /* Set HP DR bias current optimization, 010: 6uA */
1142 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1143 /* Set HP & ZCD bias current optimization */
1144 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1145 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1146 /* Set HPP/N STB enhance circuits */
1147 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1148
1149 /* Disable Pull-down HPL/R to AVSS28_AUD */
1150 hp_pull_down(priv, false);
1151
1152 /* Enable HP driver bias circuits */
1153 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1154 /* Enable HP driver core circuits */
1155 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1156 /* Enable HP main CMFB loop */
1157 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1158
1159 /* Select CMFB resistor bulk to AC mode */
1160 /* Selec HS/LO cap size (6.5pF default) */
1161 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1162
1163 /* Enable HP main output stage */
1164 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1165 /* Enable HPR/L main output stage step by step */
1166 hp_main_output_ramp(priv, true);
1167
1168 /* Set LO gain as minimum (~ -40dB) */
1169 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1170 /* apply volume setting */
1171 headset_volume_ramp(priv,
1172 DL_GAIN_N_10DB,
1173 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1174
1175 /* Set LO STB enhance circuits */
1176 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1177 /* Enable LO driver bias circuits */
1178 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1179 /* Enable LO driver core circuits */
1180 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1181
1182 /* Set LOL gain to normal gain step by step */
1183 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1184 RG_AUDLOLGAIN_MASK_SFT,
1185 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1186 RG_AUDLOLGAIN_SFT);
1187 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1188 RG_AUDLORGAIN_MASK_SFT,
1189 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1190 RG_AUDLORGAIN_SFT);
1191
1192 /* Enable AUD_CLK */
1193 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1194 /* Enable Audio DAC */
1195 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1196 /* Enable low-noise mode of DAC */
1197 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1198 /* Switch LOL MUX to audio DAC */
1199 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1200 /* Switch HPL/R MUX to Line-out */
1201 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1202
1203 return 0;
1204 }
1205
mtk_hp_spk_disable(struct mt6358_priv * priv)1206 static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1207 {
1208 /* HPR/HPL mux to open */
1209 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1210 0x0f00, 0x0000);
1211 /* LOL mux to open */
1212 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1213 0x3 << 2, 0x0000);
1214
1215 /* Disable Audio DAC */
1216 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1217 0x000f, 0x0000);
1218
1219 /* Disable AUD_CLK */
1220 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1221
1222 /* decrease HPL/R gain to normal gain step by step */
1223 headset_volume_ramp(priv,
1224 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1225 DL_GAIN_N_40DB);
1226
1227 /* decrease LOL gain to minimum gain step by step */
1228 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1229 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1230
1231 /* decrease HPR/L main output stage step by step */
1232 hp_main_output_ramp(priv, false);
1233
1234 /* Disable HP main output stage */
1235 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1236
1237 /* Short HP main output to HP aux output stage */
1238 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1239 /* Enable HP aux output stage */
1240 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1241
1242 /* Enable HP aux feedback loop */
1243 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1244
1245 /* Reduce HP aux feedback loop gain */
1246 hp_aux_feedback_loop_gain_ramp(priv, false);
1247
1248 /* Disable HP driver core circuits */
1249 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1250 0x3 << 4, 0x0);
1251 /* Disable LO driver core circuits */
1252 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1253 0x1, 0x0);
1254
1255 /* Disable HP driver bias circuits */
1256 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1257 0x3 << 6, 0x0);
1258 /* Disable LO driver bias circuits */
1259 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1260 0x1 << 1, 0x0);
1261
1262 /* Disable HP aux CMFB loop */
1263 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1264 0xff << 8, 0x0000);
1265
1266 /* Disable IBIST */
1267 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1268 0x1 << 8, 0x1 << 8);
1269 /* Disable NV regulator (-1.2V) */
1270 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1271 /* Disable cap-less LDOs (1.5V) */
1272 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1273 /* Disable NCP */
1274 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1275
1276 /* Set HP CMFB gate rstb */
1277 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1278 0x1 << 6, 0x0);
1279 /* disable Pull-down HPL/R to AVSS28_AUD */
1280 hp_pull_down(priv, false);
1281
1282 return 0;
1283 }
1284
mt_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1285 static int mt_hp_event(struct snd_soc_dapm_widget *w,
1286 struct snd_kcontrol *kcontrol,
1287 int event)
1288 {
1289 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1290 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1291 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1292 int device = DEVICE_HP;
1293
1294 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1295 __func__,
1296 event,
1297 priv->dev_counter[device],
1298 mux);
1299
1300 switch (event) {
1301 case SND_SOC_DAPM_PRE_PMU:
1302 priv->dev_counter[device]++;
1303 if (priv->dev_counter[device] > 1)
1304 break; /* already enabled, do nothing */
1305 else if (priv->dev_counter[device] <= 0)
1306 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1307 __func__,
1308 priv->dev_counter[device]);
1309
1310 priv->mux_select[MUX_HP_L] = mux;
1311
1312 if (mux == HP_MUX_HP)
1313 mtk_hp_enable(priv);
1314 else if (mux == HP_MUX_HPSPK)
1315 mtk_hp_spk_enable(priv);
1316 break;
1317 case SND_SOC_DAPM_PRE_PMD:
1318 priv->dev_counter[device]--;
1319 if (priv->dev_counter[device] > 0) {
1320 break; /* still being used, don't close */
1321 } else if (priv->dev_counter[device] < 0) {
1322 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1323 __func__,
1324 priv->dev_counter[device]);
1325 priv->dev_counter[device] = 0;
1326 break;
1327 }
1328
1329 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1330 mtk_hp_disable(priv);
1331 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1332 mtk_hp_spk_disable(priv);
1333
1334 priv->mux_select[MUX_HP_L] = mux;
1335 break;
1336 default:
1337 break;
1338 }
1339
1340 return 0;
1341 }
1342
mt_rcv_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1343 static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1344 struct snd_kcontrol *kcontrol,
1345 int event)
1346 {
1347 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1348 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1349
1350 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1351 __func__,
1352 event,
1353 dapm_kcontrol_get_value(w->kcontrols[0]));
1354
1355 switch (event) {
1356 case SND_SOC_DAPM_PRE_PMU:
1357 /* Reduce ESD resistance of AU_REFN */
1358 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1359
1360 /* Turn on DA_600K_NCP_VA18 */
1361 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1362 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1363 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1364 /* Toggle RG_DIVCKS_CHG */
1365 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1366 /* Set NCP soft start mode as default mode: 100us */
1367 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1368 /* Enable NCP */
1369 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1370 usleep_range(250, 270);
1371
1372 /* Enable cap-less LDOs (1.5V) */
1373 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1374 0x1055, 0x1055);
1375 /* Enable NV regulator (-1.2V) */
1376 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1377 usleep_range(100, 120);
1378
1379 /* Disable AUD_ZCD */
1380 hp_zcd_disable(priv);
1381
1382 /* Disable handset short-circuit protection */
1383 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1384
1385 /* Enable IBIST */
1386 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1387 /* Set HP DR bias current optimization, 010: 6uA */
1388 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1389 /* Set HP & ZCD bias current optimization */
1390 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1391 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1392 /* Set HS STB enhance circuits */
1393 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1394
1395 /* Disable HP main CMFB loop */
1396 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1397 /* Select CMFB resistor bulk to AC mode */
1398 /* Selec HS/LO cap size (6.5pF default) */
1399 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1400
1401 /* Enable HS driver bias circuits */
1402 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1403 /* Enable HS driver core circuits */
1404 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1405
1406 /* Enable AUD_CLK */
1407 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1408 0x1, 0x1);
1409
1410 /* Enable Audio DAC */
1411 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1412 /* Enable low-noise mode of DAC */
1413 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1414 /* Switch HS MUX to audio DAC */
1415 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1416 break;
1417 case SND_SOC_DAPM_PRE_PMD:
1418 /* HS mux to open */
1419 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1420 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1421 RCV_MUX_OPEN);
1422
1423 /* Disable Audio DAC */
1424 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1425 0x000f, 0x0000);
1426
1427 /* Disable AUD_CLK */
1428 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1429 0x1, 0x0);
1430
1431 /* decrease HS gain to minimum gain step by step */
1432 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1433
1434 /* Disable HS driver core circuits */
1435 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1436 0x1, 0x0);
1437
1438 /* Disable HS driver bias circuits */
1439 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1440 0x1 << 1, 0x0000);
1441
1442 /* Disable HP aux CMFB loop */
1443 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1444 0xff << 8, 0x0);
1445
1446 /* Enable HP main CMFB Switch */
1447 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1448 0xff << 8, 0x2 << 8);
1449
1450 /* Disable IBIST */
1451 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1452 0x1 << 8, 0x1 << 8);
1453
1454 /* Disable NV regulator (-1.2V) */
1455 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1456 0x1, 0x0);
1457 /* Disable cap-less LDOs (1.5V) */
1458 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1459 0x1055, 0x0);
1460 /* Disable NCP */
1461 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1462 0x1, 0x1);
1463 break;
1464 default:
1465 break;
1466 }
1467
1468 return 0;
1469 }
1470
mt_aif_out_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1471 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1472 struct snd_kcontrol *kcontrol,
1473 int event)
1474 {
1475 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1476 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1477
1478 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1479 __func__, event, priv->ul_rate);
1480
1481 switch (event) {
1482 case SND_SOC_DAPM_PRE_PMU:
1483 capture_gpio_set(priv);
1484 break;
1485 case SND_SOC_DAPM_POST_PMD:
1486 capture_gpio_reset(priv);
1487 break;
1488 default:
1489 break;
1490 }
1491
1492 return 0;
1493 }
1494
mt_adc_supply_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1495 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1496 struct snd_kcontrol *kcontrol,
1497 int event)
1498 {
1499 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1500 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1501
1502 dev_dbg(priv->dev, "%s(), event 0x%x\n",
1503 __func__, event);
1504
1505 switch (event) {
1506 case SND_SOC_DAPM_PRE_PMU:
1507 /* Enable audio ADC CLKGEN */
1508 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1509 0x1 << 5, 0x1 << 5);
1510 /* ADC CLK from CLKGEN (13MHz) */
1511 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1512 0x0000);
1513 /* Enable LCLDO_ENC 1P8V */
1514 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1515 0x2500, 0x0100);
1516 /* LCLDO_ENC remote sense */
1517 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1518 0x2500, 0x2500);
1519 break;
1520 case SND_SOC_DAPM_POST_PMD:
1521 /* LCLDO_ENC remote sense off */
1522 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1523 0x2500, 0x0100);
1524 /* disable LCLDO_ENC 1P8V */
1525 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1526 0x2500, 0x0000);
1527
1528 /* ADC CLK from CLKGEN (13MHz) */
1529 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1530 /* disable audio ADC CLKGEN */
1531 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1532 0x1 << 5, 0x0 << 5);
1533 break;
1534 default:
1535 break;
1536 }
1537
1538 return 0;
1539 }
1540
mt6358_amic_enable(struct mt6358_priv * priv)1541 static int mt6358_amic_enable(struct mt6358_priv *priv)
1542 {
1543 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1544 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1545 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1546
1547 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1548 __func__, mic_type, mux_pga_l, mux_pga_r);
1549
1550 if (IS_DCC_BASE(mic_type)) {
1551 /* DCC 50k CLK (from 26M) */
1552 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1553 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1554 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1555 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1556 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1557 }
1558
1559 /* mic bias 0 */
1560 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1561 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1562 switch (mic_type) {
1563 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1564 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1565 0xff00, 0x7700);
1566 break;
1567 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1568 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1569 0xff00, 0x1100);
1570 break;
1571 default:
1572 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1573 0xff00, 0x0000);
1574 break;
1575 }
1576 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1577 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1578 0xff, 0x21);
1579 }
1580
1581 /* mic bias 1 */
1582 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1583 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1584 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1585 regmap_write(priv->regmap,
1586 MT6358_AUDENC_ANA_CON10, 0x0161);
1587 else
1588 regmap_write(priv->regmap,
1589 MT6358_AUDENC_ANA_CON10, 0x0061);
1590 }
1591
1592 if (IS_DCC_BASE(mic_type)) {
1593 /* Audio L/R preamplifier DCC precharge */
1594 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1595 0xf8ff, 0x0004);
1596 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1597 0xf8ff, 0x0004);
1598 } else {
1599 /* reset reg */
1600 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1601 0xf8ff, 0x0000);
1602 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1603 0xf8ff, 0x0000);
1604 }
1605
1606 if (mux_pga_l != PGA_MUX_NONE) {
1607 /* L preamplifier input sel */
1608 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1609 RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1610 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1611
1612 /* L preamplifier enable */
1613 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1614 RG_AUDPREAMPLON_MASK_SFT,
1615 0x1 << RG_AUDPREAMPLON_SFT);
1616
1617 if (IS_DCC_BASE(mic_type)) {
1618 /* L preamplifier DCCEN */
1619 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1620 RG_AUDPREAMPLDCCEN_MASK_SFT,
1621 0x1 << RG_AUDPREAMPLDCCEN_SFT);
1622 }
1623
1624 /* L ADC input sel : L PGA. Enable audio L ADC */
1625 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1626 RG_AUDADCLINPUTSEL_MASK_SFT,
1627 ADC_MUX_PREAMPLIFIER <<
1628 RG_AUDADCLINPUTSEL_SFT);
1629 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1630 RG_AUDADCLPWRUP_MASK_SFT,
1631 0x1 << RG_AUDADCLPWRUP_SFT);
1632 }
1633
1634 if (mux_pga_r != PGA_MUX_NONE) {
1635 /* R preamplifier input sel */
1636 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1637 RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1638 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1639
1640 /* R preamplifier enable */
1641 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1642 RG_AUDPREAMPRON_MASK_SFT,
1643 0x1 << RG_AUDPREAMPRON_SFT);
1644
1645 if (IS_DCC_BASE(mic_type)) {
1646 /* R preamplifier DCCEN */
1647 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1648 RG_AUDPREAMPRDCCEN_MASK_SFT,
1649 0x1 << RG_AUDPREAMPRDCCEN_SFT);
1650 }
1651
1652 /* R ADC input sel : R PGA. Enable audio R ADC */
1653 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1654 RG_AUDADCRINPUTSEL_MASK_SFT,
1655 ADC_MUX_PREAMPLIFIER <<
1656 RG_AUDADCRINPUTSEL_SFT);
1657 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1658 RG_AUDADCRPWRUP_MASK_SFT,
1659 0x1 << RG_AUDADCRPWRUP_SFT);
1660 }
1661
1662 if (IS_DCC_BASE(mic_type)) {
1663 usleep_range(100, 150);
1664 /* Audio L preamplifier DCC precharge off */
1665 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1666 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1667 /* Audio R preamplifier DCC precharge off */
1668 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1669 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1670
1671 /* Short body to ground in PGA */
1672 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1673 0x1 << 12, 0x0);
1674 }
1675
1676 /* here to set digital part */
1677 mt6358_mtkaif_tx_enable(priv);
1678
1679 /* UL dmic setting off */
1680 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1681
1682 /* UL turn on */
1683 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1684
1685 return 0;
1686 }
1687
mt6358_amic_disable(struct mt6358_priv * priv)1688 static void mt6358_amic_disable(struct mt6358_priv *priv)
1689 {
1690 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1691 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1692 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1693
1694 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1695 __func__, mic_type, mux_pga_l, mux_pga_r);
1696
1697 /* UL turn off */
1698 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1699 0x0001, 0x0000);
1700
1701 /* disable aud_pad TX fifos */
1702 mt6358_mtkaif_tx_disable(priv);
1703
1704 /* L ADC input sel : off, disable L ADC */
1705 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1706 0xf000, 0x0000);
1707 /* L preamplifier DCCEN */
1708 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1709 0x1 << 1, 0x0);
1710 /* L preamplifier input sel : off, L PGA 0 dB gain */
1711 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1712 0xfffb, 0x0000);
1713
1714 /* disable L preamplifier DCC precharge */
1715 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1716 0x1 << 2, 0x0);
1717
1718 /* R ADC input sel : off, disable R ADC */
1719 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1720 0xf000, 0x0000);
1721 /* R preamplifier DCCEN */
1722 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1723 0x1 << 1, 0x0);
1724 /* R preamplifier input sel : off, R PGA 0 dB gain */
1725 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1726 0x0ffb, 0x0000);
1727
1728 /* disable R preamplifier DCC precharge */
1729 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1730 0x1 << 2, 0x0);
1731
1732 /* mic bias */
1733 /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1734 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1735
1736 /* Disable MICBIAS1 */
1737 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1738 0x0001, 0x0000);
1739
1740 if (IS_DCC_BASE(mic_type)) {
1741 /* dcclk_gen_on=1'b0 */
1742 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1743 /* dcclk_pdn=1'b1 */
1744 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1745 /* dcclk_ref_ck_sel=2'b00 */
1746 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1747 /* dcclk_div=11'b00100000011 */
1748 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1749 }
1750 }
1751
mt6358_dmic_enable(struct mt6358_priv * priv)1752 static int mt6358_dmic_enable(struct mt6358_priv *priv)
1753 {
1754 dev_info(priv->dev, "%s()\n", __func__);
1755
1756 /* mic bias */
1757 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1758 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1759
1760 /* RG_BANDGAPGEN=1'b0 */
1761 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1762 0x1 << 12, 0x0);
1763
1764 /* DMIC enable */
1765 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1766
1767 /* here to set digital part */
1768 mt6358_mtkaif_tx_enable(priv);
1769
1770 /* UL dmic setting */
1771 if (priv->dmic_one_wire_mode)
1772 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400);
1773 else
1774 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1775
1776 /* UL turn on */
1777 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1778
1779 /* Prevent pop noise form dmic hw */
1780 msleep(100);
1781
1782 return 0;
1783 }
1784
mt6358_dmic_disable(struct mt6358_priv * priv)1785 static void mt6358_dmic_disable(struct mt6358_priv *priv)
1786 {
1787 dev_info(priv->dev, "%s()\n", __func__);
1788
1789 /* UL turn off */
1790 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1791 0x0003, 0x0000);
1792
1793 /* disable aud_pad TX fifos */
1794 mt6358_mtkaif_tx_disable(priv);
1795
1796 /* DMIC disable */
1797 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1798
1799 /* mic bias */
1800 /* MISBIAS0 = 1P7V */
1801 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1802
1803 /* RG_BANDGAPGEN=1'b0 */
1804 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1805 0x1 << 12, 0x0);
1806
1807 /* MICBIA0 disable */
1808 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1809 }
1810
mt6358_restore_pga(struct mt6358_priv * priv)1811 static void mt6358_restore_pga(struct mt6358_priv *priv)
1812 {
1813 unsigned int gain_l, gain_r;
1814
1815 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1816 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1817
1818 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1819 RG_AUDPREAMPLGAIN_MASK_SFT,
1820 gain_l << RG_AUDPREAMPLGAIN_SFT);
1821 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1822 RG_AUDPREAMPRGAIN_MASK_SFT,
1823 gain_r << RG_AUDPREAMPRGAIN_SFT);
1824 }
1825
mt_mic_type_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1826 static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1827 struct snd_kcontrol *kcontrol,
1828 int event)
1829 {
1830 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1831 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1832 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1833
1834 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1835 __func__, event, mux);
1836
1837 switch (event) {
1838 case SND_SOC_DAPM_WILL_PMU:
1839 priv->mux_select[MUX_MIC_TYPE] = mux;
1840 break;
1841 case SND_SOC_DAPM_PRE_PMU:
1842 switch (mux) {
1843 case MIC_TYPE_MUX_DMIC:
1844 mt6358_dmic_enable(priv);
1845 break;
1846 default:
1847 mt6358_amic_enable(priv);
1848 break;
1849 }
1850 mt6358_restore_pga(priv);
1851
1852 break;
1853 case SND_SOC_DAPM_POST_PMD:
1854 switch (priv->mux_select[MUX_MIC_TYPE]) {
1855 case MIC_TYPE_MUX_DMIC:
1856 mt6358_dmic_disable(priv);
1857 break;
1858 default:
1859 mt6358_amic_disable(priv);
1860 break;
1861 }
1862
1863 priv->mux_select[MUX_MIC_TYPE] = mux;
1864 break;
1865 default:
1866 break;
1867 }
1868
1869 return 0;
1870 }
1871
mt_adc_l_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1872 static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1873 struct snd_kcontrol *kcontrol,
1874 int event)
1875 {
1876 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1877 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1878 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1879
1880 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1881 __func__, event, mux);
1882
1883 priv->mux_select[MUX_ADC_L] = mux;
1884
1885 return 0;
1886 }
1887
mt_adc_r_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1888 static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1889 struct snd_kcontrol *kcontrol,
1890 int event)
1891 {
1892 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1893 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1894 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1895
1896 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1897 __func__, event, mux);
1898
1899 priv->mux_select[MUX_ADC_R] = mux;
1900
1901 return 0;
1902 }
1903
mt_pga_left_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1904 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
1905 struct snd_kcontrol *kcontrol,
1906 int event)
1907 {
1908 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1909 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1910 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1911
1912 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1913 __func__, event, mux);
1914
1915 priv->mux_select[MUX_PGA_L] = mux;
1916
1917 return 0;
1918 }
1919
mt_pga_right_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1920 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
1921 struct snd_kcontrol *kcontrol,
1922 int event)
1923 {
1924 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1925 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1926 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1927
1928 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1929 __func__, event, mux);
1930
1931 priv->mux_select[MUX_PGA_R] = mux;
1932
1933 return 0;
1934 }
1935
mt_delay_250_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1936 static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
1937 struct snd_kcontrol *kcontrol,
1938 int event)
1939 {
1940 switch (event) {
1941 case SND_SOC_DAPM_POST_PMU:
1942 usleep_range(250, 270);
1943 break;
1944 case SND_SOC_DAPM_PRE_PMD:
1945 usleep_range(250, 270);
1946 break;
1947 default:
1948 break;
1949 }
1950
1951 return 0;
1952 }
1953
1954 /* DAPM Widgets */
1955 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
1956 /* Global Supply*/
1957 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
1958 MT6358_DCXO_CW14,
1959 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1960 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
1961 MT6358_AUDDEC_ANA_CON13,
1962 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
1963 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
1964 MT6358_AUDENC_ANA_CON6,
1965 RG_CLKSQ_EN_SFT, 0,
1966 mt_clksq_event,
1967 SND_SOC_DAPM_PRE_PMU),
1968 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
1969 MT6358_AUD_TOP_CKPDN_CON0,
1970 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1971 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
1972 MT6358_AUD_TOP_CKPDN_CON0,
1973 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1974 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
1975 MT6358_AUD_TOP_CKPDN_CON0,
1976 RG_AUD_CK_PDN_SFT, 1,
1977 mt_delay_250_event,
1978 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1979 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
1980 MT6358_AUD_TOP_CKPDN_CON0,
1981 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1982
1983 /* Digital Clock */
1984 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
1985 MT6358_AUDIO_TOP_CON0,
1986 PDN_AFE_CTL_SFT, 1,
1987 mt_delay_250_event,
1988 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1989 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
1990 MT6358_AUDIO_TOP_CON0,
1991 PDN_DAC_CTL_SFT, 1, NULL, 0),
1992 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
1993 MT6358_AUDIO_TOP_CON0,
1994 PDN_ADC_CTL_SFT, 1, NULL, 0),
1995 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
1996 MT6358_AUDIO_TOP_CON0,
1997 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1998 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
1999 MT6358_AUDIO_TOP_CON0,
2000 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2001 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
2002 MT6358_AUDIO_TOP_CON0,
2003 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2004 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
2005 MT6358_AUDIO_TOP_CON0,
2006 PDN_RESERVED_SFT, 1, NULL, 0),
2007
2008 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
2009 0, 0, NULL, 0),
2010
2011 /* AFE ON */
2012 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
2013 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2014 NULL, 0),
2015
2016 /* AIF Rx*/
2017 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2018 MT6358_AFE_DL_SRC2_CON0_L,
2019 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2020 mt_aif_in_event,
2021 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2022
2023 /* DL Supply */
2024 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
2025 0, 0, NULL, 0),
2026
2027 /* DAC */
2028 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2029
2030 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2031
2032 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2033
2034 /* LOL */
2035 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
2036
2037 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
2038 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2039
2040 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
2041 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2042
2043 /* Headphone */
2044 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2045 &hpl_in_mux_control,
2046 mt_hp_event,
2047 SND_SOC_DAPM_PRE_PMU |
2048 SND_SOC_DAPM_PRE_PMD),
2049
2050 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2051 &hpr_in_mux_control,
2052 mt_hp_event,
2053 SND_SOC_DAPM_PRE_PMU |
2054 SND_SOC_DAPM_PRE_PMD),
2055
2056 /* Receiver */
2057 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2058 &rcv_in_mux_control,
2059 mt_rcv_event,
2060 SND_SOC_DAPM_PRE_PMU |
2061 SND_SOC_DAPM_PRE_PMD),
2062
2063 /* Outputs */
2064 SND_SOC_DAPM_OUTPUT("Receiver"),
2065 SND_SOC_DAPM_OUTPUT("Headphone L"),
2066 SND_SOC_DAPM_OUTPUT("Headphone R"),
2067 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2068 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2069 SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2070 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2071
2072 /* SGEN */
2073 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2074 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2075 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
2076 SGEN_MUTE_SW_CTL_SFT, 1,
2077 mt_sgen_event,
2078 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2079 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
2080 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2081
2082 SND_SOC_DAPM_INPUT("SGEN DL"),
2083
2084 /* Uplinks */
2085 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2086 SND_SOC_NOPM, 0, 0,
2087 mt_aif_out_event,
2088 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2089
2090 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2091 SND_SOC_NOPM, 0, 0,
2092 mt_adc_supply_event,
2093 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2094
2095 /* Uplinks MUX */
2096 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2097 &aif_out_mux_control),
2098
2099 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2100 &mic_type_mux_control,
2101 mt_mic_type_event,
2102 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2103 SND_SOC_DAPM_WILL_PMU),
2104
2105 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2106 &adc_left_mux_control,
2107 mt_adc_l_event,
2108 SND_SOC_DAPM_WILL_PMU),
2109 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2110 &adc_right_mux_control,
2111 mt_adc_r_event,
2112 SND_SOC_DAPM_WILL_PMU),
2113
2114 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2115 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2116
2117 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2118 &pga_left_mux_control,
2119 mt_pga_left_event,
2120 SND_SOC_DAPM_WILL_PMU),
2121 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2122 &pga_right_mux_control,
2123 mt_pga_right_event,
2124 SND_SOC_DAPM_WILL_PMU),
2125
2126 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2127 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2128
2129 /* UL input */
2130 SND_SOC_DAPM_INPUT("AIN0"),
2131 SND_SOC_DAPM_INPUT("AIN1"),
2132 SND_SOC_DAPM_INPUT("AIN2"),
2133 };
2134
2135 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2136 /* Capture */
2137 {"AIF1TX", NULL, "AIF Out Mux"},
2138 {"AIF1TX", NULL, "CLK_BUF"},
2139 {"AIF1TX", NULL, "AUDGLB"},
2140 {"AIF1TX", NULL, "CLKSQ Audio"},
2141
2142 {"AIF1TX", NULL, "AUD_CK"},
2143 {"AIF1TX", NULL, "AUDIF_CK"},
2144
2145 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2146 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2147 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2148 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2149 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2150
2151 {"AIF1TX", NULL, "AFE_ON"},
2152
2153 {"AIF Out Mux", NULL, "Mic Type Mux"},
2154
2155 {"Mic Type Mux", "ACC", "ADC L"},
2156 {"Mic Type Mux", "ACC", "ADC R"},
2157 {"Mic Type Mux", "DCC", "ADC L"},
2158 {"Mic Type Mux", "DCC", "ADC R"},
2159 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2160 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2161 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2162 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2163 {"Mic Type Mux", "DMIC", "AIN0"},
2164 {"Mic Type Mux", "DMIC", "AIN2"},
2165
2166 {"ADC L", NULL, "ADC L Mux"},
2167 {"ADC L", NULL, "ADC Supply"},
2168 {"ADC R", NULL, "ADC R Mux"},
2169 {"ADC R", NULL, "ADC Supply"},
2170
2171 {"ADC L Mux", "Left Preamplifier", "PGA L"},
2172
2173 {"ADC R Mux", "Right Preamplifier", "PGA R"},
2174
2175 {"PGA L", NULL, "PGA L Mux"},
2176 {"PGA R", NULL, "PGA R Mux"},
2177
2178 {"PGA L Mux", "AIN0", "AIN0"},
2179 {"PGA L Mux", "AIN1", "AIN1"},
2180 {"PGA L Mux", "AIN2", "AIN2"},
2181
2182 {"PGA R Mux", "AIN0", "AIN0"},
2183 {"PGA R Mux", "AIN1", "AIN1"},
2184 {"PGA R Mux", "AIN2", "AIN2"},
2185
2186 /* DL Supply */
2187 {"DL Power Supply", NULL, "CLK_BUF"},
2188 {"DL Power Supply", NULL, "AUDGLB"},
2189 {"DL Power Supply", NULL, "CLKSQ Audio"},
2190
2191 {"DL Power Supply", NULL, "AUDNCP_CK"},
2192 {"DL Power Supply", NULL, "ZCD13M_CK"},
2193 {"DL Power Supply", NULL, "AUD_CK"},
2194 {"DL Power Supply", NULL, "AUDIF_CK"},
2195
2196 /* DL Digital Supply */
2197 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2198 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2199 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2200
2201 {"DL Digital Clock", NULL, "AFE_ON"},
2202
2203 {"AIF_RX", NULL, "DL Digital Clock"},
2204
2205 /* DL Path */
2206 {"DAC In Mux", "Normal Path", "AIF_RX"},
2207
2208 {"DAC In Mux", "Sgen", "SGEN DL"},
2209 {"SGEN DL", NULL, "SGEN DL SRC"},
2210 {"SGEN DL", NULL, "SGEN MUTE"},
2211 {"SGEN DL", NULL, "SGEN DL Enable"},
2212 {"SGEN DL", NULL, "DL Digital Clock"},
2213 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2214
2215 {"DACL", NULL, "DAC In Mux"},
2216 {"DACL", NULL, "DL Power Supply"},
2217
2218 {"DACR", NULL, "DAC In Mux"},
2219 {"DACR", NULL, "DL Power Supply"},
2220
2221 /* Lineout Path */
2222 {"LOL Mux", "Playback", "DACL"},
2223
2224 {"LOL Buffer", NULL, "LOL Mux"},
2225 {"LOL Buffer", NULL, "LO Stability Enh"},
2226
2227 {"LINEOUT L", NULL, "LOL Buffer"},
2228
2229 /* Headphone Path */
2230 {"HPL Mux", "Audio Playback", "DACL"},
2231 {"HPR Mux", "Audio Playback", "DACR"},
2232 {"HPL Mux", "HP Impedance", "DACL"},
2233 {"HPR Mux", "HP Impedance", "DACR"},
2234 {"HPL Mux", "LoudSPK Playback", "DACL"},
2235 {"HPR Mux", "LoudSPK Playback", "DACR"},
2236
2237 {"Headphone L", NULL, "HPL Mux"},
2238 {"Headphone R", NULL, "HPR Mux"},
2239 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2240 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2241 {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2242
2243 /* Receiver Path */
2244 {"RCV Mux", "Voice Playback", "DACL"},
2245 {"Receiver", NULL, "RCV Mux"},
2246 };
2247
mt6358_codec_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2248 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2249 struct snd_pcm_hw_params *params,
2250 struct snd_soc_dai *dai)
2251 {
2252 struct snd_soc_component *cmpnt = dai->component;
2253 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2254 unsigned int rate = params_rate(params);
2255
2256 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2257 __func__,
2258 substream->stream,
2259 rate,
2260 substream->number);
2261
2262 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2263 priv->dl_rate = rate;
2264 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2265 priv->ul_rate = rate;
2266
2267 return 0;
2268 }
2269
2270 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2271 .hw_params = mt6358_codec_dai_hw_params,
2272 };
2273
2274 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE |\
2275 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE |\
2276 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)
2277
2278 static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2279 {
2280 .name = "mt6358-snd-codec-aif1",
2281 .playback = {
2282 .stream_name = "AIF1 Playback",
2283 .channels_min = 1,
2284 .channels_max = 2,
2285 .rates = SNDRV_PCM_RATE_8000_48000 |
2286 SNDRV_PCM_RATE_96000 |
2287 SNDRV_PCM_RATE_192000,
2288 .formats = MT6358_FORMATS,
2289 },
2290 .capture = {
2291 .stream_name = "AIF1 Capture",
2292 .channels_min = 1,
2293 .channels_max = 2,
2294 .rates = SNDRV_PCM_RATE_8000 |
2295 SNDRV_PCM_RATE_16000 |
2296 SNDRV_PCM_RATE_32000 |
2297 SNDRV_PCM_RATE_48000,
2298 .formats = MT6358_FORMATS,
2299 },
2300 .ops = &mt6358_codec_dai_ops,
2301 },
2302 };
2303
mt6358_codec_init_reg(struct mt6358_priv * priv)2304 static void mt6358_codec_init_reg(struct mt6358_priv *priv)
2305 {
2306 /* Disable HeadphoneL/HeadphoneR short circuit protection */
2307 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2308 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2309 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2310 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2311 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2312 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2313 /* Disable voice short circuit protection */
2314 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2315 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2316 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2317 /* disable LO buffer left short circuit protection */
2318 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2319 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2320 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2321
2322 /* accdet s/w enable */
2323 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
2324 0xFFFF, 0x700E);
2325
2326 /* gpio miso driving set to 4mA */
2327 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2328
2329 /* set gpio */
2330 playback_gpio_reset(priv);
2331 capture_gpio_reset(priv);
2332 }
2333
mt6358_codec_probe(struct snd_soc_component * cmpnt)2334 static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
2335 {
2336 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2337 int ret;
2338
2339 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2340
2341 mt6358_codec_init_reg(priv);
2342
2343 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
2344 if (IS_ERR(priv->avdd_reg)) {
2345 dev_err(priv->dev, "%s() have no Avdd supply", __func__);
2346 return PTR_ERR(priv->avdd_reg);
2347 }
2348
2349 ret = regulator_enable(priv->avdd_reg);
2350 if (ret)
2351 return ret;
2352
2353 return 0;
2354 }
2355
2356 static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2357 .probe = mt6358_codec_probe,
2358 .controls = mt6358_snd_controls,
2359 .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2360 .dapm_widgets = mt6358_dapm_widgets,
2361 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2362 .dapm_routes = mt6358_dapm_routes,
2363 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2364 .endianness = 1,
2365 };
2366
mt6358_parse_dt(struct mt6358_priv * priv)2367 static void mt6358_parse_dt(struct mt6358_priv *priv)
2368 {
2369 int ret;
2370 struct device *dev = priv->dev;
2371
2372 ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode",
2373 &priv->dmic_one_wire_mode);
2374 if (ret) {
2375 dev_warn(priv->dev, "%s() failed to read dmic-mode\n",
2376 __func__);
2377 priv->dmic_one_wire_mode = 0;
2378 }
2379 }
2380
mt6358_platform_driver_probe(struct platform_device * pdev)2381 static int mt6358_platform_driver_probe(struct platform_device *pdev)
2382 {
2383 struct mt6358_priv *priv;
2384 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2385
2386 priv = devm_kzalloc(&pdev->dev,
2387 sizeof(struct mt6358_priv),
2388 GFP_KERNEL);
2389 if (!priv)
2390 return -ENOMEM;
2391
2392 dev_set_drvdata(&pdev->dev, priv);
2393
2394 priv->dev = &pdev->dev;
2395
2396 priv->regmap = mt6397->regmap;
2397 if (IS_ERR(priv->regmap))
2398 return PTR_ERR(priv->regmap);
2399
2400 mt6358_parse_dt(priv);
2401
2402 dev_info(priv->dev, "%s(), dev name %s\n",
2403 __func__, dev_name(&pdev->dev));
2404
2405 return devm_snd_soc_register_component(&pdev->dev,
2406 &mt6358_soc_component_driver,
2407 mt6358_dai_driver,
2408 ARRAY_SIZE(mt6358_dai_driver));
2409 }
2410
2411 static const struct of_device_id mt6358_of_match[] = {
2412 {.compatible = "mediatek,mt6358-sound",},
2413 {.compatible = "mediatek,mt6366-sound",},
2414 {}
2415 };
2416 MODULE_DEVICE_TABLE(of, mt6358_of_match);
2417
2418 static struct platform_driver mt6358_platform_driver = {
2419 .driver = {
2420 .name = "mt6358-sound",
2421 .of_match_table = mt6358_of_match,
2422 },
2423 .probe = mt6358_platform_driver_probe,
2424 };
2425
2426 module_platform_driver(mt6358_platform_driver)
2427
2428 /* Module information */
2429 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
2430 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2431 MODULE_LICENSE("GPL v2");
2432