1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * ALSA SoC CPCAP codec driver
4  *
5  * Copyright (C) 2017 - 2018 Sebastian Reichel <sre@kernel.org>
6  *
7  * Very loosely based on original driver from Motorola:
8  * Copyright (C) 2007 - 2009 Motorola, Inc.
9  */
10 
11 #include <linux/module.h>
12 #include <linux/regmap.h>
13 #include <linux/platform_device.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/mfd/motorola-cpcap.h>
16 #include <sound/core.h>
17 #include <linux/input.h>
18 #include <sound/jack.h>
19 #include <sound/soc.h>
20 #include <sound/tlv.h>
21 
22 /* Register 8 - CPCAP_REG_INTS1  --- Interrupt Sense 1 */
23 #define CPCAP_BIT_HS_S                    9  /* Headset */
24 #define CPCAP_BIT_MB2_S                   10 /* Mic Bias2 */
25 
26 /* Register 9 - CPCAP_REG_INTS2   --- Interrupt Sense 2 */
27 #define CPCAP_BIT_PTT_S                   11 /* Push To Talk */
28 
29 /* Register 512 CPCAP_REG_VAUDIOC --- Audio Regulator and Bias Voltage */
30 #define CPCAP_BIT_AUDIO_LOW_PWR           6
31 #define CPCAP_BIT_AUD_LOWPWR_SPEED        5
32 #define CPCAP_BIT_VAUDIOPRISTBY           4
33 #define CPCAP_BIT_VAUDIO_MODE1            2
34 #define CPCAP_BIT_VAUDIO_MODE0            1
35 #define CPCAP_BIT_V_AUDIO_EN              0
36 
37 /* Register 513 CPCAP_REG_CC     --- CODEC */
38 #define CPCAP_BIT_CDC_CLK2                15
39 #define CPCAP_BIT_CDC_CLK1                14
40 #define CPCAP_BIT_CDC_CLK0                13
41 #define CPCAP_BIT_CDC_SR3                 12
42 #define CPCAP_BIT_CDC_SR2                 11
43 #define CPCAP_BIT_CDC_SR1                 10
44 #define CPCAP_BIT_CDC_SR0                 9
45 #define CPCAP_BIT_CDC_CLOCK_TREE_RESET    8
46 #define CPCAP_BIT_MIC2_CDC_EN             7
47 #define CPCAP_BIT_CDC_EN_RX               6
48 #define CPCAP_BIT_DF_RESET                5
49 #define CPCAP_BIT_MIC1_CDC_EN             4
50 #define CPCAP_BIT_AUDOHPF_1		  3
51 #define CPCAP_BIT_AUDOHPF_0		  2
52 #define CPCAP_BIT_AUDIHPF_1		  1
53 #define CPCAP_BIT_AUDIHPF_0		  0
54 
55 /* Register 514 CPCAP_REG_CDI    --- CODEC Digital Audio Interface */
56 #define CPCAP_BIT_CDC_PLL_SEL             15
57 #define CPCAP_BIT_CLK_IN_SEL              13
58 #define CPCAP_BIT_DIG_AUD_IN              12
59 #define CPCAP_BIT_CDC_CLK_EN              11
60 #define CPCAP_BIT_CDC_DIG_AUD_FS1         10
61 #define CPCAP_BIT_CDC_DIG_AUD_FS0         9
62 #define CPCAP_BIT_MIC2_TIMESLOT2          8
63 #define CPCAP_BIT_MIC2_TIMESLOT1          7
64 #define CPCAP_BIT_MIC2_TIMESLOT0          6
65 #define CPCAP_BIT_MIC1_RX_TIMESLOT2       5
66 #define CPCAP_BIT_MIC1_RX_TIMESLOT1       4
67 #define CPCAP_BIT_MIC1_RX_TIMESLOT0       3
68 #define CPCAP_BIT_FS_INV                  2
69 #define CPCAP_BIT_CLK_INV                 1
70 #define CPCAP_BIT_SMB_CDC                 0
71 
72 /* Register 515 CPCAP_REG_SDAC   --- Stereo DAC */
73 #define CPCAP_BIT_FSYNC_CLK_IN_COMMON     11
74 #define CPCAP_BIT_SLAVE_PLL_CLK_INPUT     10
75 #define CPCAP_BIT_ST_CLOCK_TREE_RESET     9
76 #define CPCAP_BIT_DF_RESET_ST_DAC         8
77 #define CPCAP_BIT_ST_SR3                  7
78 #define CPCAP_BIT_ST_SR2                  6
79 #define CPCAP_BIT_ST_SR1                  5
80 #define CPCAP_BIT_ST_SR0                  4
81 #define CPCAP_BIT_ST_DAC_CLK2             3
82 #define CPCAP_BIT_ST_DAC_CLK1             2
83 #define CPCAP_BIT_ST_DAC_CLK0             1
84 #define CPCAP_BIT_ST_DAC_EN               0
85 
86 /* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */
87 #define CPCAP_BIT_ST_L_TIMESLOT2          13
88 #define CPCAP_BIT_ST_L_TIMESLOT1          12
89 #define CPCAP_BIT_ST_L_TIMESLOT0          11
90 #define CPCAP_BIT_ST_R_TIMESLOT2          10
91 #define CPCAP_BIT_ST_R_TIMESLOT1          9
92 #define CPCAP_BIT_ST_R_TIMESLOT0          8
93 #define CPCAP_BIT_ST_DAC_CLK_IN_SEL       7
94 #define CPCAP_BIT_ST_FS_INV               6
95 #define CPCAP_BIT_ST_CLK_INV              5
96 #define CPCAP_BIT_ST_DIG_AUD_FS1          4
97 #define CPCAP_BIT_ST_DIG_AUD_FS0          3
98 #define CPCAP_BIT_DIG_AUD_IN_ST_DAC       2
99 #define CPCAP_BIT_ST_CLK_EN               1
100 #define CPCAP_BIT_SMB_ST_DAC              0
101 
102 /* Register 517 CPCAP_REG_TXI    --- TX Interface */
103 #define CPCAP_BIT_PTT_TH		15
104 #define CPCAP_BIT_PTT_CMP_EN		14
105 #define CPCAP_BIT_HS_ID_TX		13
106 #define CPCAP_BIT_MB_ON2		12
107 #define CPCAP_BIT_MB_ON1L		11
108 #define CPCAP_BIT_MB_ON1R		10
109 #define CPCAP_BIT_RX_L_ENCODE		9
110 #define CPCAP_BIT_RX_R_ENCODE		8
111 #define CPCAP_BIT_MIC2_MUX		7
112 #define CPCAP_BIT_MIC2_PGA_EN		6
113 #define CPCAP_BIT_CDET_DIS		5
114 #define CPCAP_BIT_EMU_MIC_MUX		4
115 #define CPCAP_BIT_HS_MIC_MUX		3
116 #define CPCAP_BIT_MIC1_MUX		2
117 #define CPCAP_BIT_MIC1_PGA_EN		1
118 #define CPCAP_BIT_DLM			0
119 
120 /* Register 518 CPCAP_REG_TXMP   --- Mic Gain */
121 #define CPCAP_BIT_MB_BIAS_R1              11
122 #define CPCAP_BIT_MB_BIAS_R0              10
123 #define CPCAP_BIT_MIC2_GAIN_4             9
124 #define CPCAP_BIT_MIC2_GAIN_3             8
125 #define CPCAP_BIT_MIC2_GAIN_2             7
126 #define CPCAP_BIT_MIC2_GAIN_1             6
127 #define CPCAP_BIT_MIC2_GAIN_0             5
128 #define CPCAP_BIT_MIC1_GAIN_4             4
129 #define CPCAP_BIT_MIC1_GAIN_3             3
130 #define CPCAP_BIT_MIC1_GAIN_2             2
131 #define CPCAP_BIT_MIC1_GAIN_1             1
132 #define CPCAP_BIT_MIC1_GAIN_0             0
133 
134 /* Register 519 CPCAP_REG_RXOA   --- RX Output Amplifier */
135 #define CPCAP_BIT_UNUSED_519_15		15
136 #define CPCAP_BIT_UNUSED_519_14		14
137 #define CPCAP_BIT_UNUSED_519_13		13
138 #define CPCAP_BIT_STDAC_LOW_PWR_DISABLE	12
139 #define CPCAP_BIT_HS_LOW_PWR		11
140 #define CPCAP_BIT_HS_ID_RX		10
141 #define CPCAP_BIT_ST_HS_CP_EN		9
142 #define CPCAP_BIT_EMU_SPKR_R_EN		8
143 #define CPCAP_BIT_EMU_SPKR_L_EN		7
144 #define CPCAP_BIT_HS_L_EN		6
145 #define CPCAP_BIT_HS_R_EN		5
146 #define CPCAP_BIT_A4_LINEOUT_L_EN	4
147 #define CPCAP_BIT_A4_LINEOUT_R_EN	3
148 #define CPCAP_BIT_A2_LDSP_L_EN		2
149 #define CPCAP_BIT_A2_LDSP_R_EN		1
150 #define CPCAP_BIT_A1_EAR_EN		0
151 
152 /* Register 520 CPCAP_REG_RXVC   --- RX Volume Control */
153 #define CPCAP_BIT_VOL_EXT3                15
154 #define CPCAP_BIT_VOL_EXT2                14
155 #define CPCAP_BIT_VOL_EXT1                13
156 #define CPCAP_BIT_VOL_EXT0                12
157 #define CPCAP_BIT_VOL_DAC3                11
158 #define CPCAP_BIT_VOL_DAC2                10
159 #define CPCAP_BIT_VOL_DAC1                9
160 #define CPCAP_BIT_VOL_DAC0                8
161 #define CPCAP_BIT_VOL_DAC_LSB_1dB1        7
162 #define CPCAP_BIT_VOL_DAC_LSB_1dB0        6
163 #define CPCAP_BIT_VOL_CDC3                5
164 #define CPCAP_BIT_VOL_CDC2                4
165 #define CPCAP_BIT_VOL_CDC1                3
166 #define CPCAP_BIT_VOL_CDC0                2
167 #define CPCAP_BIT_VOL_CDC_LSB_1dB1        1
168 #define CPCAP_BIT_VOL_CDC_LSB_1dB0        0
169 
170 /* Register 521 CPCAP_REG_RXCOA  --- Codec to Output Amp Switches */
171 #define CPCAP_BIT_PGA_CDC_EN              10
172 #define CPCAP_BIT_CDC_SW                  9
173 #define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW   8
174 #define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW   7
175 #define CPCAP_BIT_ALEFT_HS_CDC_SW         6
176 #define CPCAP_BIT_ARIGHT_HS_CDC_SW        5
177 #define CPCAP_BIT_A4_LINEOUT_L_CDC_SW     4
178 #define CPCAP_BIT_A4_LINEOUT_R_CDC_SW     3
179 #define CPCAP_BIT_A2_LDSP_L_CDC_SW        2
180 #define CPCAP_BIT_A2_LDSP_R_CDC_SW        1
181 #define CPCAP_BIT_A1_EAR_CDC_SW           0
182 
183 /* Register 522 CPCAP_REG_RXSDOA --- RX Stereo DAC to Output Amp Switches */
184 #define CPCAP_BIT_PGA_DAC_EN              12
185 #define CPCAP_BIT_ST_DAC_SW               11
186 #define CPCAP_BIT_MONO_DAC1               10
187 #define CPCAP_BIT_MONO_DAC0               9
188 #define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW   8
189 #define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW   7
190 #define CPCAP_BIT_ALEFT_HS_DAC_SW         6
191 #define CPCAP_BIT_ARIGHT_HS_DAC_SW        5
192 #define CPCAP_BIT_A4_LINEOUT_L_DAC_SW     4
193 #define CPCAP_BIT_A4_LINEOUT_R_DAC_SW     3
194 #define CPCAP_BIT_A2_LDSP_L_DAC_SW        2
195 #define CPCAP_BIT_A2_LDSP_R_DAC_SW        1
196 #define CPCAP_BIT_A1_EAR_DAC_SW           0
197 
198 /* Register 523 CPCAP_REG_RXEPOA --- RX External PGA to Output Amp Switches */
199 #define CPCAP_BIT_PGA_EXT_L_EN            14
200 #define CPCAP_BIT_PGA_EXT_R_EN            13
201 #define CPCAP_BIT_PGA_IN_L_SW             12
202 #define CPCAP_BIT_PGA_IN_R_SW             11
203 #define CPCAP_BIT_MONO_EXT1               10
204 #define CPCAP_BIT_MONO_EXT0               9
205 #define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW   8
206 #define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW   7
207 #define CPCAP_BIT_ALEFT_HS_EXT_SW         6
208 #define CPCAP_BIT_ARIGHT_HS_EXT_SW        5
209 #define CPCAP_BIT_A4_LINEOUT_L_EXT_SW     4
210 #define CPCAP_BIT_A4_LINEOUT_R_EXT_SW     3
211 #define CPCAP_BIT_A2_LDSP_L_EXT_SW        2
212 #define CPCAP_BIT_A2_LDSP_R_EXT_SW        1
213 #define CPCAP_BIT_A1_EAR_EXT_SW           0
214 
215 /* Register 525 CPCAP_REG_A2LA --- SPK Amplifier and Clock Config for Headset */
216 #define CPCAP_BIT_NCP_CLK_SYNC            7
217 #define CPCAP_BIT_A2_CLK_SYNC             6
218 #define CPCAP_BIT_A2_FREE_RUN             5
219 #define CPCAP_BIT_A2_CLK2                 4
220 #define CPCAP_BIT_A2_CLK1                 3
221 #define CPCAP_BIT_A2_CLK0                 2
222 #define CPCAP_BIT_A2_CLK_IN               1
223 #define CPCAP_BIT_A2_CONFIG               0
224 
225 #define SLEEP_ACTIVATE_POWER 2
226 #define CLOCK_TREE_RESET_TIME 1
227 
228 /* constants for ST delay workaround */
229 #define STM_STDAC_ACTIVATE_RAMP_TIME   1
230 #define STM_STDAC_EN_TEST_PRE          0x090C
231 #define STM_STDAC_EN_TEST_POST         0x0000
232 #define STM_STDAC_EN_ST_TEST1_PRE      0x2400
233 #define STM_STDAC_EN_ST_TEST1_POST     0x0400
234 
235 struct cpcap_reg_info {
236 	u16 reg;
237 	u16 mask;
238 	u16 val;
239 };
240 
241 static const struct cpcap_reg_info cpcap_default_regs[] = {
242 	{ CPCAP_REG_VAUDIOC, 0x003F, 0x0000 },
243 	{ CPCAP_REG_CC, 0xFFFF, 0x0000 },
244 	{ CPCAP_REG_CC, 0xFFFF, 0x0000 },
245 	{ CPCAP_REG_CDI, 0xBFFF, 0x0000 },
246 	{ CPCAP_REG_SDAC, 0x0FFF, 0x0000 },
247 	{ CPCAP_REG_SDACDI, 0x3FFF, 0x0000 },
248 	{ CPCAP_REG_TXI, 0x0FDF, 0x0000 },
249 	{ CPCAP_REG_TXMP, 0x0FFF, 0x0400 },
250 	{ CPCAP_REG_RXOA, 0x01FF, 0x0000 },
251 	{ CPCAP_REG_RXVC, 0xFF3C, 0x0000 },
252 	{ CPCAP_REG_RXCOA, 0x07FF, 0x0000 },
253 	{ CPCAP_REG_RXSDOA, 0x1FFF, 0x0000 },
254 	{ CPCAP_REG_RXEPOA, 0x7FFF, 0x0000 },
255 	{ CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN),
256 	  BIT(CPCAP_BIT_A2_FREE_RUN) },
257 };
258 
259 enum cpcap_dai {
260 	CPCAP_DAI_HIFI,
261 	CPCAP_DAI_VOICE,
262 };
263 
264 struct cpcap_audio {
265 	struct snd_soc_component *component;
266 	struct regmap *regmap;
267 
268 	u16 vendor;
269 
270 	int codec_clk_id;
271 	int codec_freq;
272 	int codec_format;
273 	struct regulator *vaudio;
274 	int hsirq;
275 	int mb2irq;
276 	struct snd_soc_jack jack;
277 };
278 
cpcap_st_workaround(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)279 static int cpcap_st_workaround(struct snd_soc_dapm_widget *w,
280 			       struct snd_kcontrol *kcontrol, int event)
281 {
282 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
283 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
284 	int err = 0;
285 
286 	/* Only CPCAP from ST requires workaround */
287 	if (cpcap->vendor != CPCAP_VENDOR_ST)
288 		return 0;
289 
290 	switch (event) {
291 	case SND_SOC_DAPM_PRE_PMU:
292 		err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
293 				   STM_STDAC_EN_TEST_PRE);
294 		if (err)
295 			return err;
296 		err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
297 				   STM_STDAC_EN_ST_TEST1_PRE);
298 		break;
299 	case SND_SOC_DAPM_POST_PMU:
300 		msleep(STM_STDAC_ACTIVATE_RAMP_TIME);
301 
302 		err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
303 				   STM_STDAC_EN_ST_TEST1_POST);
304 		if (err)
305 			return err;
306 		err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
307 				   STM_STDAC_EN_TEST_POST);
308 		break;
309 	default:
310 		break;
311 	}
312 
313 	return err;
314 }
315 
316 /* Capture Gain Control: 0dB to 31dB in 1dB steps */
317 static const DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
318 
319 /* Playback Gain Control: -33dB to 12dB in 3dB steps */
320 static const DECLARE_TLV_DB_SCALE(vol_tlv, -3300, 300, 0);
321 
322 static const struct snd_kcontrol_new cpcap_snd_controls[] = {
323 	/* Playback Gain */
324 	SOC_SINGLE_TLV("HiFi Playback Volume",
325 		CPCAP_REG_RXVC, CPCAP_BIT_VOL_DAC0, 0xF, 0, vol_tlv),
326 	SOC_SINGLE_TLV("Voice Playback Volume",
327 		CPCAP_REG_RXVC, CPCAP_BIT_VOL_CDC0, 0xF, 0, vol_tlv),
328 	SOC_SINGLE_TLV("Ext Playback Volume",
329 		CPCAP_REG_RXVC, CPCAP_BIT_VOL_EXT0, 0xF, 0, vol_tlv),
330 
331 	/* Capture Gain */
332 	SOC_SINGLE_TLV("Mic1 Capture Volume",
333 		CPCAP_REG_TXMP, CPCAP_BIT_MIC1_GAIN_0, 0x1F, 0, mic_gain_tlv),
334 	SOC_SINGLE_TLV("Mic2 Capture Volume",
335 		CPCAP_REG_TXMP, CPCAP_BIT_MIC2_GAIN_0, 0x1F, 0, mic_gain_tlv),
336 
337 	/* Phase Invert */
338 	SOC_SINGLE("Hifi Left Phase Invert Switch",
339 		CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC0, 1, 0),
340 	SOC_SINGLE("Ext Left Phase Invert Switch",
341 		CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
342 };
343 
344 static const char * const cpcap_out_mux_texts[] = {
345 	"Off", "Voice", "HiFi", "Ext"
346 };
347 
348 static const char * const cpcap_in_right_mux_texts[] = {
349 	"Off", "Mic 1", "Headset Mic", "EMU Mic", "Ext Right"
350 };
351 
352 static const char * const cpcap_in_left_mux_texts[] = {
353 	"Off", "Mic 2", "Ext Left"
354 };
355 
356 /*
357  * input muxes use unusual register layout, so that we need to use custom
358  * getter/setter methods
359  */
360 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_left_mux_enum,
361 				cpcap_in_left_mux_texts);
362 static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_right_mux_enum,
363 				cpcap_in_right_mux_texts);
364 
365 /*
366  * mux uses same bit in CPCAP_REG_RXCOA, CPCAP_REG_RXSDOA & CPCAP_REG_RXEPOA;
367  * even though the register layout makes it look like a mixer, this is a mux.
368  * Enabling multiple inputs will result in no audio being forwarded.
369  */
370 static SOC_ENUM_SINGLE_DECL(cpcap_earpiece_mux_enum, 0, 0, cpcap_out_mux_texts);
371 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_r_mux_enum, 0, 1, cpcap_out_mux_texts);
372 static SOC_ENUM_SINGLE_DECL(cpcap_spkr_l_mux_enum, 0, 2, cpcap_out_mux_texts);
373 static SOC_ENUM_SINGLE_DECL(cpcap_line_r_mux_enum, 0, 3, cpcap_out_mux_texts);
374 static SOC_ENUM_SINGLE_DECL(cpcap_line_l_mux_enum, 0, 4, cpcap_out_mux_texts);
375 static SOC_ENUM_SINGLE_DECL(cpcap_hs_r_mux_enum, 0, 5, cpcap_out_mux_texts);
376 static SOC_ENUM_SINGLE_DECL(cpcap_hs_l_mux_enum, 0, 6, cpcap_out_mux_texts);
377 static SOC_ENUM_SINGLE_DECL(cpcap_emu_l_mux_enum, 0, 7, cpcap_out_mux_texts);
378 static SOC_ENUM_SINGLE_DECL(cpcap_emu_r_mux_enum, 0, 8, cpcap_out_mux_texts);
379 
cpcap_output_mux_get_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)380 static int cpcap_output_mux_get_enum(struct snd_kcontrol *kcontrol,
381 				     struct snd_ctl_elem_value *ucontrol)
382 {
383 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
384 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
385 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
386 	unsigned int shift = e->shift_l;
387 	int reg_voice, reg_hifi, reg_ext, status;
388 	int err;
389 
390 	err = regmap_read(cpcap->regmap, CPCAP_REG_RXCOA, &reg_voice);
391 	if (err)
392 		return err;
393 	err = regmap_read(cpcap->regmap, CPCAP_REG_RXSDOA, &reg_hifi);
394 	if (err)
395 		return err;
396 	err = regmap_read(cpcap->regmap, CPCAP_REG_RXEPOA, &reg_ext);
397 	if (err)
398 		return err;
399 
400 	reg_voice = (reg_voice >> shift) & 1;
401 	reg_hifi = (reg_hifi >> shift) & 1;
402 	reg_ext = (reg_ext >> shift) & 1;
403 	status = reg_ext << 2 | reg_hifi << 1 | reg_voice;
404 
405 	switch (status) {
406 	case 0x04:
407 		ucontrol->value.enumerated.item[0] = 3;
408 		break;
409 	case 0x02:
410 		ucontrol->value.enumerated.item[0] = 2;
411 		break;
412 	case 0x01:
413 		ucontrol->value.enumerated.item[0] = 1;
414 		break;
415 	default:
416 		ucontrol->value.enumerated.item[0] = 0;
417 		break;
418 	}
419 
420 	return 0;
421 }
422 
cpcap_output_mux_put_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)423 static int cpcap_output_mux_put_enum(struct snd_kcontrol *kcontrol,
424 				     struct snd_ctl_elem_value *ucontrol)
425 {
426 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
427 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
428 	struct snd_soc_dapm_context *dapm =
429 		snd_soc_dapm_kcontrol_dapm(kcontrol);
430 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
431 	unsigned int muxval = ucontrol->value.enumerated.item[0];
432 	unsigned int mask = BIT(e->shift_l);
433 	u16 reg_voice = 0x00, reg_hifi = 0x00, reg_ext = 0x00;
434 	int err;
435 
436 	switch (muxval) {
437 	case 1:
438 		reg_voice = mask;
439 		break;
440 	case 2:
441 		reg_hifi = mask;
442 		break;
443 	case 3:
444 		reg_ext = mask;
445 		break;
446 	default:
447 		break;
448 	}
449 
450 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
451 				 mask, reg_voice);
452 	if (err)
453 		return err;
454 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXSDOA,
455 				 mask, reg_hifi);
456 	if (err)
457 		return err;
458 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXEPOA,
459 				 mask, reg_ext);
460 	if (err)
461 		return err;
462 
463 	snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
464 
465 	return 0;
466 }
467 
cpcap_input_right_mux_get_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)468 static int cpcap_input_right_mux_get_enum(struct snd_kcontrol *kcontrol,
469 					  struct snd_ctl_elem_value *ucontrol)
470 {
471 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
472 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
473 	int regval, mask;
474 	int err;
475 
476 	err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
477 	if (err)
478 		return err;
479 
480 	mask = 0;
481 	mask |= BIT(CPCAP_BIT_MIC1_MUX);
482 	mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
483 	mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
484 	mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
485 
486 	switch (regval & mask) {
487 	case BIT(CPCAP_BIT_RX_R_ENCODE):
488 		ucontrol->value.enumerated.item[0] = 4;
489 		break;
490 	case BIT(CPCAP_BIT_EMU_MIC_MUX):
491 		ucontrol->value.enumerated.item[0] = 3;
492 		break;
493 	case BIT(CPCAP_BIT_HS_MIC_MUX):
494 		ucontrol->value.enumerated.item[0] = 2;
495 		break;
496 	case BIT(CPCAP_BIT_MIC1_MUX):
497 		ucontrol->value.enumerated.item[0] = 1;
498 		break;
499 	default:
500 		ucontrol->value.enumerated.item[0] = 0;
501 		break;
502 	}
503 
504 	return 0;
505 }
506 
cpcap_input_right_mux_put_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)507 static int cpcap_input_right_mux_put_enum(struct snd_kcontrol *kcontrol,
508 					  struct snd_ctl_elem_value *ucontrol)
509 {
510 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
511 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
512 	struct snd_soc_dapm_context *dapm =
513 		snd_soc_dapm_kcontrol_dapm(kcontrol);
514 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
515 	unsigned int muxval = ucontrol->value.enumerated.item[0];
516 	int regval = 0, mask;
517 	int err;
518 
519 	mask = 0;
520 	mask |= BIT(CPCAP_BIT_MIC1_MUX);
521 	mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
522 	mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
523 	mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
524 
525 	switch (muxval) {
526 	case 1:
527 		regval = BIT(CPCAP_BIT_MIC1_MUX);
528 		break;
529 	case 2:
530 		regval = BIT(CPCAP_BIT_HS_MIC_MUX);
531 		break;
532 	case 3:
533 		regval = BIT(CPCAP_BIT_EMU_MIC_MUX);
534 		break;
535 	case 4:
536 		regval = BIT(CPCAP_BIT_RX_R_ENCODE);
537 		break;
538 	default:
539 		break;
540 	}
541 
542 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
543 				 mask, regval);
544 	if (err)
545 		return err;
546 
547 	snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
548 
549 	return 0;
550 }
551 
cpcap_input_left_mux_get_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)552 static int cpcap_input_left_mux_get_enum(struct snd_kcontrol *kcontrol,
553 					 struct snd_ctl_elem_value *ucontrol)
554 {
555 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
556 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
557 	int regval, mask;
558 	int err;
559 
560 	err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
561 	if (err)
562 		return err;
563 
564 	mask = 0;
565 	mask |= BIT(CPCAP_BIT_MIC2_MUX);
566 	mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
567 
568 	switch (regval & mask) {
569 	case BIT(CPCAP_BIT_RX_L_ENCODE):
570 		ucontrol->value.enumerated.item[0] = 2;
571 		break;
572 	case BIT(CPCAP_BIT_MIC2_MUX):
573 		ucontrol->value.enumerated.item[0] = 1;
574 		break;
575 	default:
576 		ucontrol->value.enumerated.item[0] = 0;
577 		break;
578 	}
579 
580 	return 0;
581 }
582 
cpcap_input_left_mux_put_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)583 static int cpcap_input_left_mux_put_enum(struct snd_kcontrol *kcontrol,
584 					 struct snd_ctl_elem_value *ucontrol)
585 {
586 	struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
587 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
588 	struct snd_soc_dapm_context *dapm =
589 		snd_soc_dapm_kcontrol_dapm(kcontrol);
590 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
591 	unsigned int muxval = ucontrol->value.enumerated.item[0];
592 	int regval = 0, mask;
593 	int err;
594 
595 	mask = 0;
596 	mask |= BIT(CPCAP_BIT_MIC2_MUX);
597 	mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
598 
599 	switch (muxval) {
600 	case 1:
601 		regval = BIT(CPCAP_BIT_MIC2_MUX);
602 		break;
603 	case 2:
604 		regval = BIT(CPCAP_BIT_RX_L_ENCODE);
605 		break;
606 	default:
607 		break;
608 	}
609 
610 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
611 				 mask, regval);
612 	if (err)
613 		return err;
614 
615 	snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
616 
617 	return 0;
618 }
619 
620 static const struct snd_kcontrol_new cpcap_input_left_mux =
621 	SOC_DAPM_ENUM_EXT("Input Left", cpcap_input_left_mux_enum,
622 			  cpcap_input_left_mux_get_enum,
623 			  cpcap_input_left_mux_put_enum);
624 static const struct snd_kcontrol_new cpcap_input_right_mux =
625 	SOC_DAPM_ENUM_EXT("Input Right", cpcap_input_right_mux_enum,
626 			  cpcap_input_right_mux_get_enum,
627 			  cpcap_input_right_mux_put_enum);
628 static const struct snd_kcontrol_new cpcap_emu_left_mux =
629 	SOC_DAPM_ENUM_EXT("EMU Left", cpcap_emu_l_mux_enum,
630 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
631 static const struct snd_kcontrol_new cpcap_emu_right_mux =
632 	SOC_DAPM_ENUM_EXT("EMU Right", cpcap_emu_r_mux_enum,
633 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
634 static const struct snd_kcontrol_new cpcap_hs_left_mux =
635 	SOC_DAPM_ENUM_EXT("Headset Left", cpcap_hs_l_mux_enum,
636 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
637 static const struct snd_kcontrol_new cpcap_hs_right_mux =
638 	SOC_DAPM_ENUM_EXT("Headset Right", cpcap_hs_r_mux_enum,
639 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
640 static const struct snd_kcontrol_new cpcap_line_left_mux =
641 	SOC_DAPM_ENUM_EXT("Line Left", cpcap_line_l_mux_enum,
642 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
643 static const struct snd_kcontrol_new cpcap_line_right_mux =
644 	SOC_DAPM_ENUM_EXT("Line Right", cpcap_line_r_mux_enum,
645 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
646 static const struct snd_kcontrol_new cpcap_speaker_left_mux =
647 	SOC_DAPM_ENUM_EXT("Speaker Left", cpcap_spkr_l_mux_enum,
648 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
649 static const struct snd_kcontrol_new cpcap_speaker_right_mux =
650 	SOC_DAPM_ENUM_EXT("Speaker Right", cpcap_spkr_r_mux_enum,
651 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
652 static const struct snd_kcontrol_new cpcap_earpiece_mux =
653 	SOC_DAPM_ENUM_EXT("Earpiece", cpcap_earpiece_mux_enum,
654 			  cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
655 
656 static const struct snd_kcontrol_new cpcap_hifi_mono_mixer_controls[] = {
657 	SOC_DAPM_SINGLE("HiFi Mono Playback Switch",
658 		CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC1, 1, 0),
659 };
660 static const struct snd_kcontrol_new cpcap_ext_mono_mixer_controls[] = {
661 	SOC_DAPM_SINGLE("Ext Mono Playback Switch",
662 		CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
663 };
664 
665 static const struct snd_kcontrol_new cpcap_extr_mute_control =
666 	SOC_DAPM_SINGLE("Switch",
667 		CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_R_SW, 1, 0);
668 static const struct snd_kcontrol_new cpcap_extl_mute_control =
669 	SOC_DAPM_SINGLE("Switch",
670 		CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_L_SW, 1, 0);
671 
672 static const struct snd_kcontrol_new cpcap_voice_loopback =
673 	SOC_DAPM_SINGLE("Switch",
674 		CPCAP_REG_TXI, CPCAP_BIT_DLM, 1, 0);
675 
676 static const struct snd_soc_dapm_widget cpcap_dapm_widgets[] = {
677 	/* DAIs */
678 	SND_SOC_DAPM_AIF_IN("HiFi RX", NULL, 0, SND_SOC_NOPM, 0, 0),
679 	SND_SOC_DAPM_AIF_IN("Voice RX", NULL, 0, SND_SOC_NOPM, 0, 0),
680 	SND_SOC_DAPM_AIF_OUT("Voice TX", NULL, 0, SND_SOC_NOPM, 0, 0),
681 
682 	/* Power Supply */
683 	SND_SOC_DAPM_REGULATOR_SUPPLY("VAUDIO", SLEEP_ACTIVATE_POWER, 0),
684 
685 	/* Highpass Filters */
686 	SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter RX",
687 		CPCAP_REG_CC, CPCAP_BIT_AUDIHPF_0, 0x3, 0x3, 0x0),
688 	SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter TX",
689 		CPCAP_REG_CC, CPCAP_BIT_AUDOHPF_0, 0x3, 0x3, 0x0),
690 
691 	/* Clocks */
692 	SND_SOC_DAPM_SUPPLY("HiFi DAI Clock",
693 		CPCAP_REG_SDACDI, CPCAP_BIT_ST_CLK_EN, 0, NULL, 0),
694 	SND_SOC_DAPM_SUPPLY("Voice DAI Clock",
695 		CPCAP_REG_CDI, CPCAP_BIT_CDC_CLK_EN, 0, NULL, 0),
696 
697 	/* Microphone Bias */
698 	SND_SOC_DAPM_SUPPLY("MIC1R Bias",
699 		CPCAP_REG_TXI, CPCAP_BIT_MB_ON1R, 0, NULL, 0),
700 	SND_SOC_DAPM_SUPPLY("MIC1L Bias",
701 		CPCAP_REG_TXI, CPCAP_BIT_MB_ON1L, 0, NULL, 0),
702 	SND_SOC_DAPM_SUPPLY("MIC2 Bias",
703 		CPCAP_REG_TXI, CPCAP_BIT_MB_ON2, 0, NULL, 0),
704 
705 	/* Inputs */
706 	SND_SOC_DAPM_INPUT("MICR"),
707 	SND_SOC_DAPM_INPUT("HSMIC"),
708 	SND_SOC_DAPM_INPUT("EMUMIC"),
709 	SND_SOC_DAPM_INPUT("MICL"),
710 	SND_SOC_DAPM_INPUT("EXTR"),
711 	SND_SOC_DAPM_INPUT("EXTL"),
712 
713 	/* Capture Route */
714 	SND_SOC_DAPM_MUX("Right Capture Route",
715 		SND_SOC_NOPM, 0, 0, &cpcap_input_right_mux),
716 	SND_SOC_DAPM_MUX("Left Capture Route",
717 		SND_SOC_NOPM, 0, 0, &cpcap_input_left_mux),
718 
719 	/* Capture PGAs */
720 	SND_SOC_DAPM_PGA("Microphone 1 PGA",
721 		CPCAP_REG_TXI, CPCAP_BIT_MIC1_PGA_EN, 0, NULL, 0),
722 	SND_SOC_DAPM_PGA("Microphone 2 PGA",
723 		CPCAP_REG_TXI, CPCAP_BIT_MIC2_PGA_EN, 0, NULL, 0),
724 
725 	/* ADC */
726 	SND_SOC_DAPM_ADC("ADC Right", NULL,
727 		CPCAP_REG_CC, CPCAP_BIT_MIC1_CDC_EN, 0),
728 	SND_SOC_DAPM_ADC("ADC Left", NULL,
729 		CPCAP_REG_CC, CPCAP_BIT_MIC2_CDC_EN, 0),
730 
731 	/* DAC */
732 	SND_SOC_DAPM_DAC_E("DAC HiFi", NULL,
733 		CPCAP_REG_SDAC, CPCAP_BIT_ST_DAC_EN, 0,
734 		cpcap_st_workaround,
735 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
736 	SND_SOC_DAPM_DAC_E("DAC Voice", NULL,
737 		CPCAP_REG_CC, CPCAP_BIT_CDC_EN_RX, 0,
738 		cpcap_st_workaround,
739 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
740 
741 	/* Playback PGA */
742 	SND_SOC_DAPM_PGA("HiFi PGA",
743 		CPCAP_REG_RXSDOA, CPCAP_BIT_PGA_DAC_EN, 0, NULL, 0),
744 	SND_SOC_DAPM_PGA("Voice PGA",
745 		CPCAP_REG_RXCOA, CPCAP_BIT_PGA_CDC_EN, 0, NULL, 0),
746 	SND_SOC_DAPM_PGA_E("Ext Right PGA",
747 		CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_R_EN, 0,
748 		NULL, 0,
749 		cpcap_st_workaround,
750 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
751 	SND_SOC_DAPM_PGA_E("Ext Left PGA",
752 		CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_L_EN, 0,
753 		NULL, 0,
754 		cpcap_st_workaround,
755 		SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
756 
757 	/* Playback Switch */
758 	SND_SOC_DAPM_SWITCH("Ext Right Enable", SND_SOC_NOPM, 0, 0,
759 		&cpcap_extr_mute_control),
760 	SND_SOC_DAPM_SWITCH("Ext Left Enable", SND_SOC_NOPM, 0, 0,
761 		&cpcap_extl_mute_control),
762 
763 	/* Loopback Switch */
764 	SND_SOC_DAPM_SWITCH("Voice Loopback", SND_SOC_NOPM, 0, 0,
765 		&cpcap_voice_loopback),
766 
767 	/* Mono Mixer */
768 	SOC_MIXER_ARRAY("HiFi Mono Left Mixer", SND_SOC_NOPM, 0, 0,
769 		cpcap_hifi_mono_mixer_controls),
770 	SOC_MIXER_ARRAY("HiFi Mono Right Mixer", SND_SOC_NOPM, 0, 0,
771 		cpcap_hifi_mono_mixer_controls),
772 	SOC_MIXER_ARRAY("Ext Mono Left Mixer", SND_SOC_NOPM, 0, 0,
773 		cpcap_ext_mono_mixer_controls),
774 	SOC_MIXER_ARRAY("Ext Mono Right Mixer", SND_SOC_NOPM, 0, 0,
775 		cpcap_ext_mono_mixer_controls),
776 
777 	/* Output Routes */
778 	SND_SOC_DAPM_MUX("Earpiece Playback Route", SND_SOC_NOPM, 0, 0,
779 		&cpcap_earpiece_mux),
780 	SND_SOC_DAPM_MUX("Speaker Right Playback Route", SND_SOC_NOPM, 0, 0,
781 		&cpcap_speaker_right_mux),
782 	SND_SOC_DAPM_MUX("Speaker Left Playback Route", SND_SOC_NOPM, 0, 0,
783 		&cpcap_speaker_left_mux),
784 	SND_SOC_DAPM_MUX("Lineout Right Playback Route", SND_SOC_NOPM, 0, 0,
785 		&cpcap_line_right_mux),
786 	SND_SOC_DAPM_MUX("Lineout Left Playback Route", SND_SOC_NOPM, 0, 0,
787 		&cpcap_line_left_mux),
788 	SND_SOC_DAPM_MUX("Headset Right Playback Route", SND_SOC_NOPM, 0, 0,
789 		&cpcap_hs_right_mux),
790 	SND_SOC_DAPM_MUX("Headset Left Playback Route", SND_SOC_NOPM, 0, 0,
791 		&cpcap_hs_left_mux),
792 	SND_SOC_DAPM_MUX("EMU Right Playback Route", SND_SOC_NOPM, 0, 0,
793 		&cpcap_emu_right_mux),
794 	SND_SOC_DAPM_MUX("EMU Left Playback Route", SND_SOC_NOPM, 0, 0,
795 		&cpcap_emu_left_mux),
796 
797 	/* Output Amplifier */
798 	SND_SOC_DAPM_PGA("Earpiece PGA",
799 		CPCAP_REG_RXOA, CPCAP_BIT_A1_EAR_EN, 0, NULL, 0),
800 	SND_SOC_DAPM_PGA("Speaker Right PGA",
801 		CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_R_EN, 0, NULL, 0),
802 	SND_SOC_DAPM_PGA("Speaker Left PGA",
803 		CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_L_EN, 0, NULL, 0),
804 	SND_SOC_DAPM_PGA("Lineout Right PGA",
805 		CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_R_EN, 0, NULL, 0),
806 	SND_SOC_DAPM_PGA("Lineout Left PGA",
807 		CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_L_EN, 0, NULL, 0),
808 	SND_SOC_DAPM_PGA("Headset Right PGA",
809 		CPCAP_REG_RXOA, CPCAP_BIT_HS_R_EN, 0, NULL, 0),
810 	SND_SOC_DAPM_PGA("Headset Left PGA",
811 		CPCAP_REG_RXOA, CPCAP_BIT_HS_L_EN, 0, NULL, 0),
812 	SND_SOC_DAPM_PGA("EMU Right PGA",
813 		CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_R_EN, 0, NULL, 0),
814 	SND_SOC_DAPM_PGA("EMU Left PGA",
815 		CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_L_EN, 0, NULL, 0),
816 
817 	/* Headet Charge Pump */
818 	SND_SOC_DAPM_SUPPLY("Headset Charge Pump",
819 		CPCAP_REG_RXOA, CPCAP_BIT_ST_HS_CP_EN, 0, NULL, 0),
820 
821 	/* Outputs */
822 	SND_SOC_DAPM_OUTPUT("EP"),
823 	SND_SOC_DAPM_OUTPUT("SPKR"),
824 	SND_SOC_DAPM_OUTPUT("SPKL"),
825 	SND_SOC_DAPM_OUTPUT("LINER"),
826 	SND_SOC_DAPM_OUTPUT("LINEL"),
827 	SND_SOC_DAPM_OUTPUT("HSR"),
828 	SND_SOC_DAPM_OUTPUT("HSL"),
829 	SND_SOC_DAPM_OUTPUT("EMUR"),
830 	SND_SOC_DAPM_OUTPUT("EMUL"),
831 };
832 
833 static const struct snd_soc_dapm_route intercon[] = {
834 	/* Power Supply */
835 	{"HiFi PGA", NULL, "VAUDIO"},
836 	{"Voice PGA", NULL, "VAUDIO"},
837 	{"Ext Right PGA", NULL, "VAUDIO"},
838 	{"Ext Left PGA", NULL, "VAUDIO"},
839 	{"Microphone 1 PGA", NULL, "VAUDIO"},
840 	{"Microphone 2 PGA", NULL, "VAUDIO"},
841 
842 	/* Stream -> AIF */
843 	{"HiFi RX", NULL, "HiFi Playback"},
844 	{"Voice RX", NULL, "Voice Playback"},
845 	{"Voice Capture", NULL, "Voice TX"},
846 
847 	/* AIF clocks */
848 	{"HiFi RX", NULL, "HiFi DAI Clock"},
849 	{"Voice RX", NULL, "Voice DAI Clock"},
850 	{"Voice TX", NULL, "Voice DAI Clock"},
851 
852 	/* Digital Loopback */
853 	{"Voice Loopback", "Switch", "Voice TX"},
854 	{"Voice RX", NULL, "Voice Loopback"},
855 
856 	/* Highpass Filters */
857 	{"Highpass Filter RX", NULL, "Voice RX"},
858 	{"Voice TX", NULL, "Highpass Filter TX"},
859 
860 	/* AIF -> DAC mapping */
861 	{"DAC HiFi", NULL, "HiFi RX"},
862 	{"DAC Voice", NULL, "Highpass Filter RX"},
863 
864 	/* DAC -> PGA */
865 	{"HiFi PGA", NULL, "DAC HiFi"},
866 	{"Voice PGA", NULL, "DAC Voice"},
867 
868 	/* Ext Input -> PGA */
869 	{"Ext Right PGA", NULL, "EXTR"},
870 	{"Ext Left PGA", NULL, "EXTL"},
871 
872 	/* Ext PGA -> Ext Playback Switch */
873 	{"Ext Right Enable", "Switch", "Ext Right PGA"},
874 	{"Ext Left Enable", "Switch", "Ext Left PGA"},
875 
876 	/* HiFi PGA -> Mono Mixer */
877 	{"HiFi Mono Left Mixer", NULL, "HiFi PGA"},
878 	{"HiFi Mono Left Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
879 	{"HiFi Mono Right Mixer", NULL, "HiFi PGA"},
880 	{"HiFi Mono Right Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
881 
882 	/* Ext Playback Switch -> Ext Mono Mixer */
883 	{"Ext Mono Right Mixer", NULL, "Ext Right Enable"},
884 	{"Ext Mono Right Mixer", "Ext Mono Playback Switch", "Ext Left Enable"},
885 	{"Ext Mono Left Mixer", NULL, "Ext Left Enable"},
886 	{"Ext Mono Left Mixer", "Ext Mono Playback Switch", "Ext Right Enable"},
887 
888 	/* HiFi Mono Mixer -> Output Route */
889 	{"Earpiece Playback Route", "HiFi", "HiFi Mono Right Mixer"},
890 	{"Speaker Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
891 	{"Speaker Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
892 	{"Lineout Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
893 	{"Lineout Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
894 	{"Headset Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
895 	{"Headset Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
896 	{"EMU Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
897 	{"EMU Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
898 
899 	/* Voice PGA -> Output Route */
900 	{"Earpiece Playback Route", "Voice", "Voice PGA"},
901 	{"Speaker Right Playback Route", "Voice", "Voice PGA"},
902 	{"Speaker Left Playback Route", "Voice", "Voice PGA"},
903 	{"Lineout Right Playback Route", "Voice", "Voice PGA"},
904 	{"Lineout Left Playback Route", "Voice", "Voice PGA"},
905 	{"Headset Right Playback Route", "Voice", "Voice PGA"},
906 	{"Headset Left Playback Route", "Voice", "Voice PGA"},
907 	{"EMU Right Playback Route", "Voice", "Voice PGA"},
908 	{"EMU Left Playback Route", "Voice", "Voice PGA"},
909 
910 	/* Ext Mono Mixer -> Output Route */
911 	{"Earpiece Playback Route", "Ext", "Ext Mono Right Mixer"},
912 	{"Speaker Right Playback Route", "Ext", "Ext Mono Right Mixer"},
913 	{"Speaker Left Playback Route", "Ext", "Ext Mono Left Mixer"},
914 	{"Lineout Right Playback Route", "Ext", "Ext Mono Right Mixer"},
915 	{"Lineout Left Playback Route", "Ext", "Ext Mono Left Mixer"},
916 	{"Headset Right Playback Route", "Ext", "Ext Mono Right Mixer"},
917 	{"Headset Left Playback Route", "Ext", "Ext Mono Left Mixer"},
918 	{"EMU Right Playback Route", "Ext", "Ext Mono Right Mixer"},
919 	{"EMU Left Playback Route", "Ext", "Ext Mono Left Mixer"},
920 
921 	/* Output Route -> Output Amplifier */
922 	{"Earpiece PGA", NULL, "Earpiece Playback Route"},
923 	{"Speaker Right PGA", NULL, "Speaker Right Playback Route"},
924 	{"Speaker Left PGA", NULL, "Speaker Left Playback Route"},
925 	{"Lineout Right PGA", NULL, "Lineout Right Playback Route"},
926 	{"Lineout Left PGA", NULL, "Lineout Left Playback Route"},
927 	{"Headset Right PGA", NULL, "Headset Right Playback Route"},
928 	{"Headset Left PGA", NULL, "Headset Left Playback Route"},
929 	{"EMU Right PGA", NULL, "EMU Right Playback Route"},
930 	{"EMU Left PGA", NULL, "EMU Left Playback Route"},
931 
932 	/* Output Amplifier -> Output */
933 	{"EP", NULL, "Earpiece PGA"},
934 	{"SPKR", NULL, "Speaker Right PGA"},
935 	{"SPKL", NULL, "Speaker Left PGA"},
936 	{"LINER", NULL, "Lineout Right PGA"},
937 	{"LINEL", NULL, "Lineout Left PGA"},
938 	{"HSR", NULL, "Headset Right PGA"},
939 	{"HSL", NULL, "Headset Left PGA"},
940 	{"EMUR", NULL, "EMU Right PGA"},
941 	{"EMUL", NULL, "EMU Left PGA"},
942 
943 	/* Headset Charge Pump -> Headset */
944 	{"HSR", NULL, "Headset Charge Pump"},
945 	{"HSL", NULL, "Headset Charge Pump"},
946 
947 	/* Mic -> Mic Route */
948 	{"Right Capture Route", "Mic 1", "MICR"},
949 	{"Right Capture Route", "Headset Mic", "HSMIC"},
950 	{"Right Capture Route", "EMU Mic", "EMUMIC"},
951 	{"Right Capture Route", "Ext Right", "EXTR"},
952 	{"Left Capture Route", "Mic 2", "MICL"},
953 	{"Left Capture Route", "Ext Left", "EXTL"},
954 
955 	/* Input Route -> Microphone PGA */
956 	{"Microphone 1 PGA", NULL, "Right Capture Route"},
957 	{"Microphone 2 PGA", NULL, "Left Capture Route"},
958 
959 	/* Microphone PGA -> ADC */
960 	{"ADC Right", NULL, "Microphone 1 PGA"},
961 	{"ADC Left", NULL, "Microphone 2 PGA"},
962 
963 	/* ADC -> Stream */
964 	{"Highpass Filter TX", NULL, "ADC Right"},
965 	{"Highpass Filter TX", NULL, "ADC Left"},
966 
967 	/* Mic Bias */
968 	{"MICL", NULL, "MIC1L Bias"},
969 	{"MICR", NULL, "MIC1R Bias"},
970 };
971 
cpcap_set_sysclk(struct cpcap_audio * cpcap,enum cpcap_dai dai,int clk_id,int freq)972 static int cpcap_set_sysclk(struct cpcap_audio *cpcap, enum cpcap_dai dai,
973 			    int clk_id, int freq)
974 {
975 	u16 clkfreqreg, clkfreqshift;
976 	u16 clkfreqmask, clkfreqval;
977 	u16 clkidreg, clkidshift;
978 	u16 mask, val;
979 	int err;
980 
981 	switch (dai) {
982 	case CPCAP_DAI_HIFI:
983 		clkfreqreg = CPCAP_REG_SDAC;
984 		clkfreqshift = CPCAP_BIT_ST_DAC_CLK0;
985 		clkidreg = CPCAP_REG_SDACDI;
986 		clkidshift = CPCAP_BIT_ST_DAC_CLK_IN_SEL;
987 		break;
988 	case CPCAP_DAI_VOICE:
989 		clkfreqreg = CPCAP_REG_CC;
990 		clkfreqshift = CPCAP_BIT_CDC_CLK0;
991 		clkidreg = CPCAP_REG_CDI;
992 		clkidshift = CPCAP_BIT_CLK_IN_SEL;
993 		break;
994 	default:
995 		dev_err(cpcap->component->dev, "invalid DAI: %d", dai);
996 		return -EINVAL;
997 	}
998 
999 	/* setup clk id */
1000 	if (clk_id < 0 || clk_id > 1) {
1001 		dev_err(cpcap->component->dev, "invalid clk id %d", clk_id);
1002 		return -EINVAL;
1003 	}
1004 	err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift),
1005 				 clk_id ? BIT(clkidshift) : 0);
1006 	if (err)
1007 		return err;
1008 
1009 	/* enable PLL for Voice DAI */
1010 	if (dai == CPCAP_DAI_VOICE) {
1011 		mask = BIT(CPCAP_BIT_CDC_PLL_SEL);
1012 		val = BIT(CPCAP_BIT_CDC_PLL_SEL);
1013 		err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
1014 					 mask, val);
1015 		if (err)
1016 			return err;
1017 	}
1018 
1019 	/* setup frequency */
1020 	clkfreqmask = 0x7 << clkfreqshift;
1021 	switch (freq) {
1022 	case 15360000:
1023 		clkfreqval = 0x01 << clkfreqshift;
1024 		break;
1025 	case 16800000:
1026 		clkfreqval = 0x02 << clkfreqshift;
1027 		break;
1028 	case 19200000:
1029 		clkfreqval = 0x03 << clkfreqshift;
1030 		break;
1031 	case 26000000:
1032 		clkfreqval = 0x04 << clkfreqshift;
1033 		break;
1034 	case 33600000:
1035 		clkfreqval = 0x05 << clkfreqshift;
1036 		break;
1037 	case 38400000:
1038 		clkfreqval = 0x06 << clkfreqshift;
1039 		break;
1040 	default:
1041 		dev_err(cpcap->component->dev, "unsupported freq %u", freq);
1042 		return -EINVAL;
1043 	}
1044 
1045 	err = regmap_update_bits(cpcap->regmap, clkfreqreg,
1046 				 clkfreqmask, clkfreqval);
1047 	if (err)
1048 		return err;
1049 
1050 	if (dai == CPCAP_DAI_VOICE) {
1051 		cpcap->codec_clk_id = clk_id;
1052 		cpcap->codec_freq = freq;
1053 	}
1054 
1055 	return 0;
1056 }
1057 
cpcap_set_samprate(struct cpcap_audio * cpcap,enum cpcap_dai dai,int samplerate)1058 static int cpcap_set_samprate(struct cpcap_audio *cpcap, enum cpcap_dai dai,
1059 			      int samplerate)
1060 {
1061 	struct snd_soc_component *component = cpcap->component;
1062 	u16 sampreg, sampmask, sampshift, sampval, sampreset;
1063 	int err, sampreadval;
1064 
1065 	switch (dai) {
1066 	case CPCAP_DAI_HIFI:
1067 		sampreg = CPCAP_REG_SDAC;
1068 		sampshift = CPCAP_BIT_ST_SR0;
1069 		sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) |
1070 			    BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET);
1071 		break;
1072 	case CPCAP_DAI_VOICE:
1073 		sampreg = CPCAP_REG_CC;
1074 		sampshift = CPCAP_BIT_CDC_SR0;
1075 		sampreset = BIT(CPCAP_BIT_DF_RESET) |
1076 			    BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET);
1077 		break;
1078 	default:
1079 		dev_err(component->dev, "invalid DAI: %d", dai);
1080 		return -EINVAL;
1081 	}
1082 
1083 	sampmask = 0xF << sampshift | sampreset;
1084 	switch (samplerate) {
1085 	case 48000:
1086 		sampval = 0x8 << sampshift;
1087 		break;
1088 	case 44100:
1089 		sampval = 0x7 << sampshift;
1090 		break;
1091 	case 32000:
1092 		sampval = 0x6 << sampshift;
1093 		break;
1094 	case 24000:
1095 		sampval = 0x5 << sampshift;
1096 		break;
1097 	case 22050:
1098 		sampval = 0x4 << sampshift;
1099 		break;
1100 	case 16000:
1101 		sampval = 0x3 << sampshift;
1102 		break;
1103 	case 12000:
1104 		sampval = 0x2 << sampshift;
1105 		break;
1106 	case 11025:
1107 		sampval = 0x1 << sampshift;
1108 		break;
1109 	case 8000:
1110 		sampval = 0x0 << sampshift;
1111 		break;
1112 	default:
1113 		dev_err(component->dev, "unsupported samplerate %d", samplerate);
1114 		return -EINVAL;
1115 	}
1116 	err = regmap_update_bits(cpcap->regmap, sampreg,
1117 				 sampmask, sampval | sampreset);
1118 	if (err)
1119 		return err;
1120 
1121 	/* Wait for clock tree reset to complete */
1122 	mdelay(CLOCK_TREE_RESET_TIME);
1123 
1124 	err = regmap_read(cpcap->regmap, sampreg, &sampreadval);
1125 	if (err)
1126 		return err;
1127 
1128 	if (sampreadval & sampreset) {
1129 		dev_err(component->dev, "reset self-clear failed: %04x",
1130 			sampreadval);
1131 		return -EIO;
1132 	}
1133 
1134 	return 0;
1135 }
1136 
cpcap_hifi_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1137 static int cpcap_hifi_hw_params(struct snd_pcm_substream *substream,
1138 				struct snd_pcm_hw_params *params,
1139 				struct snd_soc_dai *dai)
1140 {
1141 	struct snd_soc_component *component = dai->component;
1142 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1143 	int rate = params_rate(params);
1144 
1145 	dev_dbg(component->dev, "HiFi setup HW params: rate=%d", rate);
1146 	return cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, rate);
1147 }
1148 
cpcap_hifi_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1149 static int cpcap_hifi_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1150 				     unsigned int freq, int dir)
1151 {
1152 	struct snd_soc_component *component = codec_dai->component;
1153 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1154 	struct device *dev = component->dev;
1155 
1156 	dev_dbg(dev, "HiFi setup sysclk: clk_id=%u, freq=%u", clk_id, freq);
1157 	return cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, clk_id, freq);
1158 }
1159 
cpcap_hifi_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1160 static int cpcap_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
1161 				  unsigned int fmt)
1162 {
1163 	struct snd_soc_component *component = codec_dai->component;
1164 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1165 	struct device *dev = component->dev;
1166 	static const u16 reg = CPCAP_REG_SDACDI;
1167 	static const u16 mask =
1168 		BIT(CPCAP_BIT_SMB_ST_DAC) |
1169 		BIT(CPCAP_BIT_ST_CLK_INV) |
1170 		BIT(CPCAP_BIT_ST_FS_INV) |
1171 		BIT(CPCAP_BIT_ST_DIG_AUD_FS0) |
1172 		BIT(CPCAP_BIT_ST_DIG_AUD_FS1) |
1173 		BIT(CPCAP_BIT_ST_L_TIMESLOT0) |
1174 		BIT(CPCAP_BIT_ST_L_TIMESLOT1) |
1175 		BIT(CPCAP_BIT_ST_L_TIMESLOT2) |
1176 		BIT(CPCAP_BIT_ST_R_TIMESLOT0) |
1177 		BIT(CPCAP_BIT_ST_R_TIMESLOT1) |
1178 		BIT(CPCAP_BIT_ST_R_TIMESLOT2);
1179 	u16 val = 0x0000;
1180 
1181 	dev_dbg(dev, "HiFi setup dai format (%08x)", fmt);
1182 
1183 	/*
1184 	 * "HiFi Playback" should always be configured as
1185 	 * SND_SOC_DAIFMT_CBP_CFP - codec clk & frm provider
1186 	 * SND_SOC_DAIFMT_I2S - I2S mode
1187 	 */
1188 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1189 	case SND_SOC_DAIFMT_CBP_CFP:
1190 		val &= ~BIT(CPCAP_BIT_SMB_ST_DAC);
1191 		break;
1192 	default:
1193 		dev_err(dev, "HiFi dai fmt failed: CPCAP should be provider");
1194 		return -EINVAL;
1195 	}
1196 
1197 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1198 	case SND_SOC_DAIFMT_IB_IF:
1199 		val |= BIT(CPCAP_BIT_ST_FS_INV);
1200 		val |= BIT(CPCAP_BIT_ST_CLK_INV);
1201 		break;
1202 	case SND_SOC_DAIFMT_IB_NF:
1203 		val &= ~BIT(CPCAP_BIT_ST_FS_INV);
1204 		val |= BIT(CPCAP_BIT_ST_CLK_INV);
1205 		break;
1206 	case SND_SOC_DAIFMT_NB_IF:
1207 		val |= BIT(CPCAP_BIT_ST_FS_INV);
1208 		val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
1209 		break;
1210 	case SND_SOC_DAIFMT_NB_NF:
1211 		val &= ~BIT(CPCAP_BIT_ST_FS_INV);
1212 		val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
1213 		break;
1214 	default:
1215 		dev_err(dev, "HiFi dai fmt failed: unsupported clock invert mode");
1216 		return -EINVAL;
1217 	}
1218 
1219 	if (val & BIT(CPCAP_BIT_ST_CLK_INV))
1220 		val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
1221 	else
1222 		val |= BIT(CPCAP_BIT_ST_CLK_INV);
1223 
1224 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1225 	case SND_SOC_DAIFMT_I2S:
1226 		val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
1227 		val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
1228 		break;
1229 	default:
1230 		/* 01 - 4 slots network mode */
1231 		val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
1232 		val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
1233 		/* L on slot 1 */
1234 		val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0);
1235 		break;
1236 	}
1237 
1238 	dev_dbg(dev, "HiFi dai format: val=%04x", val);
1239 	return regmap_update_bits(cpcap->regmap, reg, mask, val);
1240 }
1241 
cpcap_hifi_set_mute(struct snd_soc_dai * dai,int mute,int direction)1242 static int cpcap_hifi_set_mute(struct snd_soc_dai *dai, int mute, int direction)
1243 {
1244 	struct snd_soc_component *component = dai->component;
1245 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1246 	static const u16 reg = CPCAP_REG_RXSDOA;
1247 	static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW);
1248 	u16 val;
1249 
1250 	if (mute)
1251 		val = 0;
1252 	else
1253 		val = BIT(CPCAP_BIT_ST_DAC_SW);
1254 
1255 	dev_dbg(component->dev, "HiFi mute: %d", mute);
1256 	return regmap_update_bits(cpcap->regmap, reg, mask, val);
1257 }
1258 
1259 static const struct snd_soc_dai_ops cpcap_dai_hifi_ops = {
1260 	.hw_params	= cpcap_hifi_hw_params,
1261 	.set_sysclk	= cpcap_hifi_set_dai_sysclk,
1262 	.set_fmt	= cpcap_hifi_set_dai_fmt,
1263 	.mute_stream	= cpcap_hifi_set_mute,
1264 	.no_capture_mute = 1,
1265 };
1266 
cpcap_voice_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1267 static int cpcap_voice_hw_params(struct snd_pcm_substream *substream,
1268 				 struct snd_pcm_hw_params *params,
1269 				 struct snd_soc_dai *dai)
1270 {
1271 	struct snd_soc_component *component = dai->component;
1272 	struct device *dev = component->dev;
1273 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1274 	static const u16 reg_cdi = CPCAP_REG_CDI;
1275 	int rate = params_rate(params);
1276 	int channels = params_channels(params);
1277 	int direction = substream->stream;
1278 	u16 val, mask;
1279 	int err;
1280 
1281 	dev_dbg(dev, "Voice setup HW params: rate=%d, direction=%d, chan=%d",
1282 		rate, direction, channels);
1283 
1284 	err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, rate);
1285 	if (err)
1286 		return err;
1287 
1288 	if (direction == SNDRV_PCM_STREAM_CAPTURE) {
1289 		mask = 0x0000;
1290 		mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
1291 		mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT1);
1292 		mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT2);
1293 		mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT0);
1294 		mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT1);
1295 		mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT2);
1296 		val = 0x0000;
1297 		if (channels >= 2)
1298 			val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
1299 		err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val);
1300 		if (err)
1301 			return err;
1302 	}
1303 
1304 	return 0;
1305 }
1306 
cpcap_voice_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)1307 static int cpcap_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
1308 				      unsigned int freq, int dir)
1309 {
1310 	struct snd_soc_component *component = codec_dai->component;
1311 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1312 
1313 	dev_dbg(component->dev, "Voice setup sysclk: clk_id=%u, freq=%u",
1314 		clk_id, freq);
1315 	return cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, clk_id, freq);
1316 }
1317 
cpcap_voice_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1318 static int cpcap_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1319 				   unsigned int fmt)
1320 {
1321 	struct snd_soc_component *component = codec_dai->component;
1322 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1323 	static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) |
1324 				BIT(CPCAP_BIT_CLK_INV) |
1325 				BIT(CPCAP_BIT_FS_INV) |
1326 				BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) |
1327 				BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
1328 	u16 val = 0x0000;
1329 	int err;
1330 
1331 	dev_dbg(component->dev, "Voice setup dai format (%08x)", fmt);
1332 
1333 	/*
1334 	 * "Voice Playback" and "Voice Capture" should always be
1335 	 * configured as SND_SOC_DAIFMT_CBP_CFP - codec clk & frm
1336 	 * provider
1337 	 */
1338 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1339 	case SND_SOC_DAIFMT_CBP_CFP:
1340 		val &= ~BIT(CPCAP_BIT_SMB_CDC);
1341 		break;
1342 	default:
1343 		dev_err(component->dev, "Voice dai fmt failed: CPCAP should be the provider");
1344 		val &= ~BIT(CPCAP_BIT_SMB_CDC);
1345 		break;
1346 	}
1347 
1348 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1349 	case SND_SOC_DAIFMT_IB_IF:
1350 		val |= BIT(CPCAP_BIT_CLK_INV);
1351 		val |= BIT(CPCAP_BIT_FS_INV);
1352 		break;
1353 	case SND_SOC_DAIFMT_IB_NF:
1354 		val |= BIT(CPCAP_BIT_CLK_INV);
1355 		val &= ~BIT(CPCAP_BIT_FS_INV);
1356 		break;
1357 	case SND_SOC_DAIFMT_NB_IF:
1358 		val &= ~BIT(CPCAP_BIT_CLK_INV);
1359 		val |= BIT(CPCAP_BIT_FS_INV);
1360 		break;
1361 	case SND_SOC_DAIFMT_NB_NF:
1362 		val &= ~BIT(CPCAP_BIT_CLK_INV);
1363 		val &= ~BIT(CPCAP_BIT_FS_INV);
1364 		break;
1365 	default:
1366 		dev_err(component->dev, "Voice dai fmt failed: unsupported clock invert mode");
1367 		break;
1368 	}
1369 
1370 	if (val & BIT(CPCAP_BIT_CLK_INV))
1371 		val &= ~BIT(CPCAP_BIT_CLK_INV);
1372 	else
1373 		val |= BIT(CPCAP_BIT_CLK_INV);
1374 
1375 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1376 	case SND_SOC_DAIFMT_I2S:
1377 		/* 11 - true I2S mode */
1378 		val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
1379 		val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
1380 		break;
1381 	default:
1382 		/* 4 timeslots network mode */
1383 		val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
1384 		val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
1385 		break;
1386 	}
1387 
1388 	dev_dbg(component->dev, "Voice dai format: val=%04x", val);
1389 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val);
1390 	if (err)
1391 		return err;
1392 
1393 	cpcap->codec_format = val;
1394 	return 0;
1395 }
1396 
1397 
1398 /*
1399  * Configure codec for voice call if requested.
1400  *
1401  * We can configure most with snd_soc_dai_set_sysclk(), snd_soc_dai_set_fmt()
1402  * and snd_soc_dai_set_tdm_slot(). This function configures the rest of the
1403  * cpcap related hardware as CPU is not involved in the voice call.
1404  */
cpcap_voice_call(struct cpcap_audio * cpcap,struct snd_soc_dai * dai,bool voice_call)1405 static int cpcap_voice_call(struct cpcap_audio *cpcap, struct snd_soc_dai *dai,
1406 			    bool voice_call)
1407 {
1408 	int mask, err;
1409 
1410 	/* Modem to codec VAUDIO_MODE1 */
1411 	mask = BIT(CPCAP_BIT_VAUDIO_MODE1);
1412 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_VAUDIOC,
1413 				 mask, voice_call ? mask : 0);
1414 	if (err)
1415 		return err;
1416 
1417 	/* Clear MIC1_MUX for call */
1418 	mask = BIT(CPCAP_BIT_MIC1_MUX);
1419 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
1420 				 mask, voice_call ? 0 : mask);
1421 	if (err)
1422 		return err;
1423 
1424 	/* Set MIC2_MUX for call */
1425 	mask = BIT(CPCAP_BIT_MB_ON1L) | BIT(CPCAP_BIT_MB_ON1R) |
1426 		BIT(CPCAP_BIT_MIC2_MUX) | BIT(CPCAP_BIT_MIC2_PGA_EN);
1427 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
1428 				 mask, voice_call ? mask : 0);
1429 	if (err)
1430 		return err;
1431 
1432 	/* Enable LDSP for call */
1433 	mask = BIT(CPCAP_BIT_A2_LDSP_L_EN) | BIT(CPCAP_BIT_A2_LDSP_R_EN);
1434 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXOA,
1435 				 mask, voice_call ? mask : 0);
1436 	if (err)
1437 		return err;
1438 
1439 	/* Enable CPCAP_BIT_PGA_CDC_EN for call */
1440 	mask = BIT(CPCAP_BIT_PGA_CDC_EN);
1441 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
1442 				 mask, voice_call ? mask : 0);
1443 	if (err)
1444 		return err;
1445 
1446 	/* Unmute voice for call */
1447 	if (dai) {
1448 		err = snd_soc_dai_digital_mute(dai, !voice_call,
1449 					       SNDRV_PCM_STREAM_PLAYBACK);
1450 		if (err)
1451 			return err;
1452 	}
1453 
1454 	/* Set modem to codec mic CDC and HPF for call */
1455 	mask = BIT(CPCAP_BIT_MIC2_CDC_EN) | BIT(CPCAP_BIT_CDC_EN_RX) |
1456 	       BIT(CPCAP_BIT_AUDOHPF_1) | BIT(CPCAP_BIT_AUDOHPF_0) |
1457 	       BIT(CPCAP_BIT_AUDIHPF_1) | BIT(CPCAP_BIT_AUDIHPF_0);
1458 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CC,
1459 				 mask, voice_call ? mask : 0);
1460 	if (err)
1461 		return err;
1462 
1463 	/* Enable modem to codec CDC for call*/
1464 	mask = BIT(CPCAP_BIT_CDC_CLK_EN);
1465 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
1466 				 mask, voice_call ? mask : 0);
1467 
1468 	return err;
1469 }
1470 
cpcap_voice_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1471 static int cpcap_voice_set_tdm_slot(struct snd_soc_dai *dai,
1472 				    unsigned int tx_mask, unsigned int rx_mask,
1473 				    int slots, int slot_width)
1474 {
1475 	struct snd_soc_component *component = dai->component;
1476 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1477 	int err, ts_mask, mask;
1478 	bool voice_call;
1479 
1480 	/*
1481 	 * Primitive test for voice call, probably needs more checks
1482 	 * later on for 16-bit calls detected, Bluetooth headset etc.
1483 	 */
1484 	if (tx_mask == 0 && rx_mask == 1 && slot_width == 8)
1485 		voice_call = true;
1486 	else
1487 		voice_call = false;
1488 
1489 	ts_mask = 0x7 << CPCAP_BIT_MIC2_TIMESLOT0;
1490 	ts_mask |= 0x7 << CPCAP_BIT_MIC1_RX_TIMESLOT0;
1491 
1492 	mask = (tx_mask & 0x7) << CPCAP_BIT_MIC2_TIMESLOT0;
1493 	mask |= (rx_mask & 0x7) << CPCAP_BIT_MIC1_RX_TIMESLOT0;
1494 
1495 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
1496 				 ts_mask, mask);
1497 	if (err)
1498 		return err;
1499 
1500 	err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, slot_width * 1000);
1501 	if (err)
1502 		return err;
1503 
1504 	err = cpcap_voice_call(cpcap, dai, voice_call);
1505 	if (err)
1506 		return err;
1507 
1508 	return 0;
1509 }
1510 
cpcap_voice_set_mute(struct snd_soc_dai * dai,int mute,int direction)1511 static int cpcap_voice_set_mute(struct snd_soc_dai *dai, int mute, int direction)
1512 {
1513 	struct snd_soc_component *component = dai->component;
1514 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1515 	static const u16 reg = CPCAP_REG_RXCOA;
1516 	static const u16 mask = BIT(CPCAP_BIT_CDC_SW);
1517 	u16 val;
1518 
1519 	if (mute)
1520 		val = 0;
1521 	else
1522 		val = BIT(CPCAP_BIT_CDC_SW);
1523 
1524 	dev_dbg(component->dev, "Voice mute: %d", mute);
1525 	return regmap_update_bits(cpcap->regmap, reg, mask, val);
1526 };
1527 
1528 static const struct snd_soc_dai_ops cpcap_dai_voice_ops = {
1529 	.hw_params	= cpcap_voice_hw_params,
1530 	.set_sysclk	= cpcap_voice_set_dai_sysclk,
1531 	.set_fmt	= cpcap_voice_set_dai_fmt,
1532 	.set_tdm_slot	= cpcap_voice_set_tdm_slot,
1533 	.mute_stream	= cpcap_voice_set_mute,
1534 	.no_capture_mute = 1,
1535 };
1536 
1537 static struct snd_soc_dai_driver cpcap_dai[] = {
1538 {
1539 	.id = 0,
1540 	.name = "cpcap-hifi",
1541 	.playback = {
1542 		.stream_name = "HiFi Playback",
1543 		.channels_min = 2,
1544 		.channels_max = 2,
1545 		.rates = SNDRV_PCM_RATE_8000_48000,
1546 		.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,
1547 	},
1548 	.ops = &cpcap_dai_hifi_ops,
1549 },
1550 {
1551 	.id = 1,
1552 	.name = "cpcap-voice",
1553 	.playback = {
1554 		.stream_name = "Voice Playback",
1555 		.channels_min = 1,
1556 		.channels_max = 1,
1557 		.rates = SNDRV_PCM_RATE_8000_48000,
1558 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
1559 	},
1560 	.capture = {
1561 		.stream_name = "Voice Capture",
1562 		.channels_min = 1,
1563 		.channels_max = 2,
1564 		.rates = SNDRV_PCM_RATE_8000_48000,
1565 		.formats = SNDRV_PCM_FMTBIT_S16_LE,
1566 	},
1567 	.ops = &cpcap_dai_voice_ops,
1568 },
1569 };
1570 
cpcap_dai_mux(struct cpcap_audio * cpcap,bool swap_dai_configuration)1571 static int cpcap_dai_mux(struct cpcap_audio *cpcap, bool swap_dai_configuration)
1572 {
1573 	u16 hifi_val, voice_val;
1574 	u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC);
1575 	u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN);
1576 	int err;
1577 
1578 
1579 
1580 	if (!swap_dai_configuration) {
1581 		/* Codec on DAI0, HiFi on DAI1 */
1582 		voice_val = 0;
1583 		hifi_val = hifi_mask;
1584 	} else {
1585 		/* Codec on DAI1, HiFi on DAI0 */
1586 		voice_val = voice_mask;
1587 		hifi_val = 0;
1588 	}
1589 
1590 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
1591 				 voice_mask, voice_val);
1592 	if (err)
1593 		return err;
1594 
1595 	err = regmap_update_bits(cpcap->regmap, CPCAP_REG_SDACDI,
1596 				 hifi_mask, hifi_val);
1597 	if (err)
1598 		return err;
1599 
1600 	return 0;
1601 }
1602 
cpcap_audio_reset(struct snd_soc_component * component,bool swap_dai_configuration)1603 static int cpcap_audio_reset(struct snd_soc_component *component,
1604 			     bool swap_dai_configuration)
1605 {
1606 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1607 	int i, err = 0;
1608 
1609 	dev_dbg(component->dev, "init audio codec");
1610 
1611 	for (i = 0; i < ARRAY_SIZE(cpcap_default_regs); i++) {
1612 		err = regmap_update_bits(cpcap->regmap,
1613 					 cpcap_default_regs[i].reg,
1614 					 cpcap_default_regs[i].mask,
1615 					 cpcap_default_regs[i].val);
1616 		if (err)
1617 			return err;
1618 	}
1619 
1620 	/* setup default settings */
1621 	err = cpcap_dai_mux(cpcap, swap_dai_configuration);
1622 	if (err)
1623 		return err;
1624 
1625 	err = cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, 0, 26000000);
1626 	if (err)
1627 		return err;
1628 	err = cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, 0, 26000000);
1629 	if (err)
1630 		return err;
1631 
1632 	err = cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, 48000);
1633 	if (err)
1634 		return err;
1635 
1636 	err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, 48000);
1637 	if (err)
1638 		return err;
1639 
1640 	return 0;
1641 }
1642 
cpcap_hs_irq_thread(int irq,void * data)1643 static irqreturn_t cpcap_hs_irq_thread(int irq, void *data)
1644 {
1645 	struct snd_soc_component *component = data;
1646 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1647 	struct regmap *regmap = cpcap->regmap;
1648 	int status = 0;
1649 	int mask = SND_JACK_HEADSET;
1650 	int val;
1651 
1652 	if (!regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_HS_S))) {
1653 		val = BIT(CPCAP_BIT_MB_ON2) | BIT(CPCAP_BIT_PTT_CMP_EN);
1654 		regmap_update_bits(regmap, CPCAP_REG_TXI, val, val);
1655 
1656 		val = BIT(CPCAP_BIT_ST_HS_CP_EN);
1657 		regmap_update_bits(regmap, CPCAP_REG_RXOA, val, val);
1658 
1659 		regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_NORMAL);
1660 
1661 		/* Give PTTS time to settle */
1662 		msleep(20);
1663 
1664 		if (!regmap_test_bits(regmap, CPCAP_REG_INTS2,
1665 				      BIT(CPCAP_BIT_PTT_S))) {
1666 			/* Headphones detected. (May also be a headset with the
1667 			 * MFB pressed.)
1668 			 */
1669 			status = SND_JACK_HEADPHONE;
1670 			dev_info(component->dev, "HP plugged in\n");
1671 		} else if (regmap_test_bits(regmap, CPCAP_REG_INTS1,
1672 					    BIT(CPCAP_BIT_MB2_S)) == 1) {
1673 			status = SND_JACK_HEADSET;
1674 			dev_info(component->dev, "HS plugged in\n");
1675 		} else
1676 			dev_info(component->dev, "Unsupported HS plugged in\n");
1677 	} else {
1678 		bool mic = cpcap->jack.status & SND_JACK_MICROPHONE;
1679 
1680 		dev_info(component->dev, "H%s disconnect\n", mic ? "S" : "P");
1681 		val = BIT(CPCAP_BIT_MB_ON2) | BIT(CPCAP_BIT_PTT_CMP_EN);
1682 		regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI, val, 0);
1683 
1684 		val = BIT(CPCAP_BIT_ST_HS_CP_EN);
1685 		regmap_update_bits(cpcap->regmap, CPCAP_REG_RXOA, val, 0);
1686 
1687 		regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_STANDBY);
1688 
1689 		mask |= SND_JACK_BTN_0;
1690 	}
1691 
1692 	snd_soc_jack_report(&cpcap->jack, status, mask);
1693 
1694 	return IRQ_HANDLED;
1695 }
1696 
cpcap_mb2_irq_thread(int irq,void * data)1697 static irqreturn_t cpcap_mb2_irq_thread(int irq, void *data)
1698 {
1699 	struct snd_soc_component *component = data;
1700 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1701 	struct regmap *regmap = cpcap->regmap;
1702 	int status = 0;
1703 	int mb2;
1704 	int ptt;
1705 
1706 	if (regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_HS_S)) == 1)
1707 		return IRQ_HANDLED;
1708 
1709 	mb2 = regmap_test_bits(regmap, CPCAP_REG_INTS1, BIT(CPCAP_BIT_MB2_S));
1710 	ptt = regmap_test_bits(regmap, CPCAP_REG_INTS2, BIT(CPCAP_BIT_PTT_S));
1711 
1712 	/* Initial detection might have been with MFB pressed */
1713 	if (!(cpcap->jack.status & SND_JACK_MICROPHONE)) {
1714 		if (ptt == 1 && mb2 == 1) {
1715 			dev_info(component->dev, "MIC plugged in\n");
1716 			snd_soc_jack_report(&cpcap->jack, SND_JACK_MICROPHONE,
1717 					    SND_JACK_MICROPHONE);
1718 		}
1719 
1720 		return IRQ_HANDLED;
1721 	}
1722 
1723 	if (!mb2 || !ptt)
1724 		status = SND_JACK_BTN_0;
1725 
1726 	snd_soc_jack_report(&cpcap->jack, status, SND_JACK_BTN_0);
1727 
1728 	return IRQ_HANDLED;
1729 }
1730 
cpcap_soc_probe(struct snd_soc_component * component)1731 static int cpcap_soc_probe(struct snd_soc_component *component)
1732 {
1733 	struct platform_device *pdev = to_platform_device(component->dev);
1734 	struct snd_soc_card *card = component->card;
1735 	struct cpcap_audio *cpcap;
1736 	int err;
1737 
1738 	cpcap = devm_kzalloc(component->dev, sizeof(*cpcap), GFP_KERNEL);
1739 	if (!cpcap)
1740 		return -ENOMEM;
1741 
1742 	snd_soc_component_set_drvdata(component, cpcap);
1743 	cpcap->component = component;
1744 
1745 	cpcap->vaudio = devm_regulator_get(component->dev, "VAUDIO");
1746 	if (IS_ERR(cpcap->vaudio))
1747 		return dev_err_probe(component->dev, PTR_ERR(cpcap->vaudio),
1748 				     "Cannot get VAUDIO regulator\n");
1749 
1750 	err = snd_soc_card_jack_new(card, "Headphones",
1751 				    SND_JACK_HEADSET | SND_JACK_BTN_0,
1752 				    &cpcap->jack);
1753 	if (err < 0) {
1754 		dev_err(component->dev, "Cannot create HS jack: %i\n", err);
1755 		return err;
1756 	}
1757 
1758 	snd_jack_set_key(cpcap->jack.jack, SND_JACK_BTN_0, KEY_MEDIA);
1759 
1760 	cpcap->regmap = dev_get_regmap(component->dev->parent, NULL);
1761 	if (!cpcap->regmap)
1762 		return -ENODEV;
1763 	snd_soc_component_init_regmap(component, cpcap->regmap);
1764 
1765 	err = cpcap_get_vendor(component->dev, cpcap->regmap, &cpcap->vendor);
1766 	if (err)
1767 		return err;
1768 
1769 	cpcap->hsirq = platform_get_irq_byname(pdev, "hs");
1770 	if (cpcap->hsirq < 0)
1771 		return cpcap->hsirq;
1772 
1773 	err = devm_request_threaded_irq(component->dev, cpcap->hsirq, NULL,
1774 					cpcap_hs_irq_thread,
1775 					IRQF_TRIGGER_RISING |
1776 					IRQF_TRIGGER_FALLING |
1777 					IRQF_ONESHOT,
1778 					"cpcap-codec-hs",
1779 					component);
1780 	if (err) {
1781 		dev_warn(component->dev, "no HS irq%i: %i\n",
1782 			 cpcap->hsirq, err);
1783 		return err;
1784 	}
1785 
1786 	cpcap->mb2irq = platform_get_irq_byname(pdev, "mb2");
1787 	if (cpcap->mb2irq < 0)
1788 		return cpcap->mb2irq;
1789 
1790 	err = devm_request_threaded_irq(component->dev, cpcap->mb2irq, NULL,
1791 					cpcap_mb2_irq_thread,
1792 					IRQF_TRIGGER_RISING |
1793 					IRQF_TRIGGER_FALLING |
1794 					IRQF_ONESHOT,
1795 					"cpcap-codec-mb2",
1796 					component);
1797 	if (err) {
1798 		dev_warn(component->dev, "no MB2 irq%i: %i\n",
1799 			 cpcap->mb2irq, err);
1800 		return err;
1801 	}
1802 
1803 	err = cpcap_audio_reset(component, false);
1804 	if (err)
1805 		return err;
1806 
1807 	cpcap_hs_irq_thread(cpcap->hsirq, component);
1808 
1809 	enable_irq_wake(cpcap->hsirq);
1810 	enable_irq_wake(cpcap->mb2irq);
1811 
1812 	return 0;
1813 }
1814 
cpcap_soc_remove(struct snd_soc_component * component)1815 static void cpcap_soc_remove(struct snd_soc_component *component)
1816 {
1817 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1818 
1819 	disable_irq_wake(cpcap->hsirq);
1820 	disable_irq_wake(cpcap->mb2irq);
1821 }
1822 
cpcap_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1823 static int cpcap_set_bias_level(struct snd_soc_component *component,
1824 		enum snd_soc_bias_level level)
1825 {
1826 	struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
1827 
1828 	/* VAIDIO should be kept in normal mode in order MIC/PTT to work */
1829 	if (cpcap->jack.status & SND_JACK_MICROPHONE)
1830 		return 0;
1831 
1832 	switch (level) {
1833 	case SND_SOC_BIAS_OFF:
1834 		break;
1835 	case SND_SOC_BIAS_PREPARE:
1836 		regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_NORMAL);
1837 		break;
1838 	case SND_SOC_BIAS_STANDBY:
1839 		regulator_set_mode(cpcap->vaudio, REGULATOR_MODE_STANDBY);
1840 		break;
1841 	case SND_SOC_BIAS_ON:
1842 		break;
1843 	}
1844 
1845 	return 0;
1846 }
1847 
1848 static const struct snd_soc_component_driver soc_codec_dev_cpcap = {
1849 	.probe			= cpcap_soc_probe,
1850 	.remove			= cpcap_soc_remove,
1851 	.controls		= cpcap_snd_controls,
1852 	.num_controls		= ARRAY_SIZE(cpcap_snd_controls),
1853 	.dapm_widgets		= cpcap_dapm_widgets,
1854 	.num_dapm_widgets	= ARRAY_SIZE(cpcap_dapm_widgets),
1855 	.dapm_routes		= intercon,
1856 	.num_dapm_routes	= ARRAY_SIZE(intercon),
1857 	.set_bias_level		= cpcap_set_bias_level,
1858 	.idle_bias_on		= 1,
1859 	.use_pmdown_time	= 1,
1860 	.endianness		= 1,
1861 };
1862 
cpcap_codec_probe(struct platform_device * pdev)1863 static int cpcap_codec_probe(struct platform_device *pdev)
1864 {
1865 	struct device_node *codec_node =
1866 		of_get_child_by_name(pdev->dev.parent->of_node, "audio-codec");
1867 	if (!codec_node)
1868 		return -ENODEV;
1869 
1870 	pdev->dev.of_node = codec_node;
1871 
1872 	return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cpcap,
1873 				      cpcap_dai, ARRAY_SIZE(cpcap_dai));
1874 }
1875 
1876 static struct platform_driver cpcap_codec_driver = {
1877 	.probe		= cpcap_codec_probe,
1878 	.driver		= {
1879 		.name	= "cpcap-codec",
1880 	},
1881 };
1882 module_platform_driver(cpcap_codec_driver);
1883 
1884 MODULE_ALIAS("platform:cpcap-codec");
1885 MODULE_DESCRIPTION("ASoC CPCAP codec driver");
1886 MODULE_AUTHOR("Sebastian Reichel");
1887 MODULE_LICENSE("GPL v2");
1888