1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11 #ifndef __AMD_ACP_H
12 #define __AMD_ACP_H
13
14 #include <sound/pcm.h>
15 #include <sound/soc.h>
16 #include <sound/soc-acpi.h>
17 #include <sound/soc-dai.h>
18
19 #include "acp_common.h"
20 #include "chip_offset_byte.h"
21
22 #define DMIC_INSTANCE 0x00
23 #define I2S_SP_INSTANCE 0x01
24 #define I2S_BT_INSTANCE 0x02
25 #define I2S_HS_INSTANCE 0x03
26
27 #define MEM_WINDOW_START 0x4080000
28
29 #define ACP_I2S_REG_START 0x1242400
30 #define ACP_I2S_REG_END 0x1242810
31 #define ACP3x_I2STDM_REG_START 0x1242400
32 #define ACP3x_I2STDM_REG_END 0x1242410
33 #define ACP3x_BT_TDM_REG_START 0x1242800
34 #define ACP3x_BT_TDM_REG_END 0x1242810
35
36 #define THRESHOLD(bit, base) ((bit) + (base))
37 #define I2S_RX_THRESHOLD(base) THRESHOLD(7, base)
38 #define I2S_TX_THRESHOLD(base) THRESHOLD(8, base)
39 #define BT_TX_THRESHOLD(base) THRESHOLD(6, base)
40 #define BT_RX_THRESHOLD(base) THRESHOLD(5, base)
41 #define HS_TX_THRESHOLD(base) THRESHOLD(4, base)
42 #define HS_RX_THRESHOLD(base) THRESHOLD(3, base)
43
44 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
45 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
46 #define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
47 #define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
48 #define ACP_SRAM_PDM_PTE_OFFSET 0x400
49 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x500
50 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x600
51 #define PAGE_SIZE_4K_ENABLE 0x2
52
53 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
54 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
55 #define I2S_BT_TX_MEM_WINDOW_START 0x4040000
56 #define I2S_BT_RX_MEM_WINDOW_START 0x4060000
57 #define I2S_HS_TX_MEM_WINDOW_START 0x40A0000
58 #define I2S_HS_RX_MEM_WINDOW_START 0x40C0000
59
60 #define ACP7x_I2S_SP_TX_MEM_WINDOW_START 0x4000000
61 #define ACP7x_I2S_SP_RX_MEM_WINDOW_START 0x4200000
62 #define ACP7x_I2S_BT_TX_MEM_WINDOW_START 0x4400000
63 #define ACP7x_I2S_BT_RX_MEM_WINDOW_START 0x4600000
64 #define ACP7x_I2S_HS_TX_MEM_WINDOW_START 0x4800000
65 #define ACP7x_I2S_HS_RX_MEM_WINDOW_START 0x4A00000
66 #define ACP7x_DMIC_MEM_WINDOW_START 0x4C00000
67
68 #define SP_PB_FIFO_ADDR_OFFSET 0x500
69 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
70 #define BT_PB_FIFO_ADDR_OFFSET 0x900
71 #define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
72 #define HS_PB_FIFO_ADDR_OFFSET 0xD00
73 #define HS_CAPT_FIFO_ADDR_OFFSET 0xF00
74 #define PLAYBACK_MIN_NUM_PERIODS 2
75 #define PLAYBACK_MAX_NUM_PERIODS 8
76 #define PLAYBACK_MAX_PERIOD_SIZE 8192
77 #define PLAYBACK_MIN_PERIOD_SIZE 1024
78 #define CAPTURE_MIN_NUM_PERIODS 2
79 #define CAPTURE_MAX_NUM_PERIODS 8
80 #define CAPTURE_MAX_PERIOD_SIZE 8192
81 #define CAPTURE_MIN_PERIOD_SIZE 1024
82
83 #define MAX_BUFFER 65536
84 #define MIN_BUFFER MAX_BUFFER
85 #define FIFO_SIZE 0x100
86 #define DMA_SIZE 0x40
87 #define FRM_LEN 0x100
88
89 #define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
90
91 #define ACP_MAX_STREAM 8
92
93 #define TDM_ENABLE 1
94 #define TDM_DISABLE 0
95
96 #define SLOT_WIDTH_8 0x8
97 #define SLOT_WIDTH_16 0x10
98 #define SLOT_WIDTH_24 0x18
99 #define SLOT_WIDTH_32 0x20
100
101 #define ACP6X_PGFSM_CONTROL 0x1024
102 #define ACP6X_PGFSM_STATUS 0x1028
103
104 #define ACP63_PGFSM_CONTROL ACP6X_PGFSM_CONTROL
105 #define ACP63_PGFSM_STATUS ACP6X_PGFSM_STATUS
106
107 #define ACP70_PGFSM_CONTROL ACP6X_PGFSM_CONTROL
108 #define ACP70_PGFSM_STATUS ACP6X_PGFSM_STATUS
109
110 #define ACP_ZSC_DSP_CTRL 0x0001014
111 #define ACP_ZSC_STS 0x0001018
112 #define ACP_SOFT_RST_DONE_MASK 0x00010001
113
114 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0xffffffff
115 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
116 #define ACP_PGFSM_STATUS_MASK 0x03
117 #define ACP_POWERED_ON 0x00
118 #define ACP_POWER_ON_IN_PROGRESS 0x01
119 #define ACP_POWERED_OFF 0x02
120 #define ACP_POWER_OFF_IN_PROGRESS 0x03
121
122 #define ACP_ERROR_MASK 0x20000000
123 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xffffffff
124
125 #define ACP_TIMEOUT 500
126 #define DELAY_US 5
127 #define ACP_SUSPEND_DELAY_MS 2000
128
129 #define PDM_DMA_STAT 0x10
130 #define PDM_DMA_INTR_MASK 0x10000
131 #define PDM_DEC_64 0x2
132 #define PDM_CLK_FREQ_MASK 0x07
133 #define PDM_MISC_CTRL_MASK 0x10
134 #define PDM_ENABLE 0x01
135 #define PDM_DISABLE 0x00
136 #define DMA_EN_MASK 0x02
137 #define DELAY_US 5
138 #define PDM_TIMEOUT 1000
139 #define ACP_REGION2_OFFSET 0x02000000
140
141 struct acp_chip_info {
142 char *name; /* Platform name */
143 struct resource *res;
144 struct device *dev;
145 struct snd_soc_dai_driver *dai_driver;
146
147 unsigned int acp_rev; /* ACP Revision id */
148 void __iomem *base; /* ACP memory PCI base */
149 struct snd_acp_hw_ops *acp_hw_ops;
150 int (*acp_hw_ops_init)(struct acp_chip_info *chip);
151 struct platform_device *chip_pdev;
152 struct acp_resource *rsrc; /* Platform specific resources*/
153 struct list_head stream_list;
154 spinlock_t acp_lock; /* Used to protect stream_list */
155 struct platform_device *dmic_codec_dev;
156 struct platform_device *acp_plat_dev;
157 struct platform_device *mach_dev;
158 struct snd_soc_acpi_mach *machines;
159 int num_dai;
160 u32 addr;
161 u32 bclk_div;
162 u32 lrclk_div;
163 u32 ch_mask;
164 u32 tdm_tx_fmt[3];
165 u32 tdm_rx_fmt[3];
166 u32 xfer_tx_resolution[3];
167 u32 xfer_rx_resolution[3];
168 unsigned int flag; /* Distinguish b/w Legacy or Only PDM */
169 bool is_pdm_dev; /* flag set to true when ACP PDM controller exists */
170 bool is_pdm_config; /* flag set to true when PDM configuration is selected from BIOS */
171 bool is_i2s_config; /* flag set to true when I2S configuration is selected from BIOS */
172 bool tdm_mode;
173 };
174
175 struct acp_stream {
176 struct list_head list;
177 struct snd_pcm_substream *substream;
178 int irq_bit;
179 int dai_id;
180 int id;
181 int dir;
182 u64 bytescount;
183 u32 reg_offset;
184 u32 pte_offset;
185 u32 fifo_offset;
186 };
187
188 struct acp_resource {
189 int offset;
190 int no_of_ctrls;
191 int irqp_used;
192 bool soc_mclk;
193 u32 irq_reg_offset;
194 u64 scratch_reg_offset;
195 u64 sram_pte_offset;
196 };
197
198 /**
199 * struct snd_acp_hw_ops - ACP PCI driver platform specific ops
200 * @acp_init: ACP initialization
201 * @acp_deinit: ACP de-initialization
202 * @irq: ACP irq handler
203 * @en_interrupts: ACP enable interrupts
204 * @dis_interrupts: ACP disable interrupts
205 */
206 struct snd_acp_hw_ops {
207 /* ACP hardware initilizations */
208 int (*acp_init)(struct acp_chip_info *chip);
209 int (*acp_deinit)(struct acp_chip_info *chip);
210
211 /* ACP Interrupts*/
212 irqreturn_t (*irq)(int irq, void *data);
213 int (*en_interrupts)(struct acp_chip_info *chip);
214 int (*dis_interrupts)(struct acp_chip_info *chip);
215 };
216
217 enum acp_config {
218 ACP_CONFIG_0 = 0,
219 ACP_CONFIG_1,
220 ACP_CONFIG_2,
221 ACP_CONFIG_3,
222 ACP_CONFIG_4,
223 ACP_CONFIG_5,
224 ACP_CONFIG_6,
225 ACP_CONFIG_7,
226 ACP_CONFIG_8,
227 ACP_CONFIG_9,
228 ACP_CONFIG_10,
229 ACP_CONFIG_11,
230 ACP_CONFIG_12,
231 ACP_CONFIG_13,
232 ACP_CONFIG_14,
233 ACP_CONFIG_15,
234 ACP_CONFIG_16,
235 ACP_CONFIG_17,
236 ACP_CONFIG_18,
237 ACP_CONFIG_19,
238 ACP_CONFIG_20,
239 };
240
241 extern struct acp_resource rn_rsrc;
242 extern struct acp_resource rmb_rsrc;
243 extern struct acp_resource acp63_rsrc;
244 extern struct acp_resource acp70_rsrc;
245
246 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp_machines;
247 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_rmb_acp_machines;
248 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_acp_machines;
249 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp70_acp_machines;
250
251 extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
252 extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
253
254 int acp_platform_register(struct device *dev);
255 int acp_platform_unregister(struct device *dev);
256
257 int acp_machine_select(struct acp_chip_info *chip);
258
259 int acp_init(struct acp_chip_info *chip);
260 int acp_deinit(struct acp_chip_info *chip);
261 int acp_enable_interrupts(struct acp_chip_info *chip);
262 int acp_disable_interrupts(struct acp_chip_info *chip);
263 irqreturn_t acp_irq_handler(int irq, void *data);
264
265 extern struct snd_acp_hw_ops acp31_common_hw_ops;
266 extern struct snd_acp_hw_ops acp6x_common_hw_ops;
267 extern struct snd_acp_hw_ops acp63_common_hw_ops;
268 extern struct snd_acp_hw_ops acp70_common_hw_ops;
269 extern int acp31_hw_ops_init(struct acp_chip_info *chip);
270 extern int acp6x_hw_ops_init(struct acp_chip_info *chip);
271 extern int acp63_hw_ops_init(struct acp_chip_info *chip);
272 extern int acp70_hw_ops_init(struct acp_chip_info *chip);
273 /* Machine configuration */
274 int snd_amd_acp_find_config(struct pci_dev *pci);
275
276 void config_pte_for_stream(struct acp_chip_info *chip, struct acp_stream *stream);
277 void config_acp_dma(struct acp_chip_info *chip, struct acp_stream *stream, int size);
278 void restore_acp_pdm_params(struct snd_pcm_substream *substream,
279 struct acp_chip_info *chip);
280
281 int restore_acp_i2s_params(struct snd_pcm_substream *substream,
282 struct acp_chip_info *chip, struct acp_stream *stream);
283
284 void check_acp_config(struct pci_dev *pci, struct acp_chip_info *chip);
285
acp_hw_init(struct acp_chip_info * chip)286 static inline int acp_hw_init(struct acp_chip_info *chip)
287 {
288 if (chip && chip->acp_hw_ops && chip->acp_hw_ops->acp_init)
289 return chip->acp_hw_ops->acp_init(chip);
290 return -EOPNOTSUPP;
291 }
292
acp_hw_deinit(struct acp_chip_info * chip)293 static inline int acp_hw_deinit(struct acp_chip_info *chip)
294 {
295 if (chip && chip->acp_hw_ops && chip->acp_hw_ops->acp_deinit)
296 return chip->acp_hw_ops->acp_deinit(chip);
297 return -EOPNOTSUPP;
298 }
299
acp_hw_en_interrupts(struct acp_chip_info * chip)300 static inline int acp_hw_en_interrupts(struct acp_chip_info *chip)
301 {
302 if (chip && chip->acp_hw_ops && chip->acp_hw_ops->en_interrupts)
303 return chip->acp_hw_ops->en_interrupts(chip);
304 return -EOPNOTSUPP;
305 }
306
acp_hw_dis_interrupts(struct acp_chip_info * chip)307 static inline int acp_hw_dis_interrupts(struct acp_chip_info *chip)
308 {
309 if (chip && chip->acp_hw_ops && chip->acp_hw_ops->dis_interrupts)
310 chip->acp_hw_ops->dis_interrupts(chip);
311 return -EOPNOTSUPP;
312 }
313
acp_get_byte_count(struct acp_chip_info * chip,int dai_id,int direction)314 static inline u64 acp_get_byte_count(struct acp_chip_info *chip, int dai_id, int direction)
315 {
316 u64 byte_count = 0, low = 0, high = 0;
317
318 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
319 switch (dai_id) {
320 case I2S_BT_INSTANCE:
321 high = readl(chip->base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH(chip));
322 low = readl(chip->base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW(chip));
323 break;
324 case I2S_SP_INSTANCE:
325 high = readl(chip->base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH(chip));
326 low = readl(chip->base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW(chip));
327 break;
328 case I2S_HS_INSTANCE:
329 high = readl(chip->base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
330 low = readl(chip->base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
331 break;
332 default:
333 dev_err(chip->dev, "Invalid dai id %x\n", dai_id);
334 goto POINTER_RETURN_BYTES;
335 }
336 } else {
337 switch (dai_id) {
338 case I2S_BT_INSTANCE:
339 high = readl(chip->base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH(chip));
340 low = readl(chip->base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW(chip));
341 break;
342 case I2S_SP_INSTANCE:
343 high = readl(chip->base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH(chip));
344 low = readl(chip->base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW(chip));
345 break;
346 case I2S_HS_INSTANCE:
347 high = readl(chip->base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
348 low = readl(chip->base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
349 break;
350 case DMIC_INSTANCE:
351 high = readl(chip->base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
352 low = readl(chip->base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
353 break;
354 default:
355 dev_err(chip->dev, "Invalid dai id %x\n", dai_id);
356 goto POINTER_RETURN_BYTES;
357 }
358 }
359 /* Get 64 bit value from two 32 bit registers */
360 byte_count = (high << 32) | low;
361
362 POINTER_RETURN_BYTES:
363 return byte_count;
364 }
365 #endif
366