1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/slab.h>
23 #include <linux/time.h>
24 #include <linux/string.h>
25 #include <linux/pm_runtime.h>
26
27 #include <sound/core.h>
28 #include <sound/initval.h>
29
30 #include <sound/hda_codec.h>
31 #include "hda_controller.h"
32
33 /* Defines for Nvidia Tegra HDA support */
34 #define HDA_BAR0 0x8000
35
36 #define HDA_CFG_CMD 0x1004
37 #define HDA_CFG_BAR0 0x1010
38
39 #define HDA_ENABLE_IO_SPACE (1 << 0)
40 #define HDA_ENABLE_MEM_SPACE (1 << 1)
41 #define HDA_ENABLE_BUS_MASTER (1 << 2)
42 #define HDA_ENABLE_SERR (1 << 8)
43 #define HDA_DISABLE_INTR (1 << 10)
44 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
45 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
46
47 /* IPFS */
48 #define HDA_IPFS_CONFIG 0x180
49 #define HDA_IPFS_EN_FPCI 0x1
50
51 #define HDA_IPFS_FPCI_BAR0 0x80
52 #define HDA_FPCI_BAR0_START 0x40
53
54 #define HDA_IPFS_INTR_MASK 0x188
55 #define HDA_IPFS_EN_INTR (1 << 16)
56
57 /* FPCI */
58 #define FPCI_DBG_CFG_2 0x10F4
59 #define FPCI_GCAP_NSDO_SHIFT 18
60 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
61
62 /* max number of SDs */
63 #define NUM_CAPTURE_SD 1
64 #define NUM_PLAYBACK_SD 1
65
66 /*
67 * Tegra194 does not reflect correct number of SDO lines. Below macro
68 * is used to update the GCAP register to workaround the issue.
69 */
70 #define TEGRA194_NUM_SDO_LINES 4
71
72 struct hda_tegra_soc {
73 bool has_hda2codec_2x_reset;
74 bool has_hda2hdmi;
75 };
76
77 struct hda_tegra {
78 struct azx chip;
79 struct device *dev;
80 struct reset_control_bulk_data resets[3];
81 struct clk_bulk_data clocks[3];
82 unsigned int nresets;
83 unsigned int nclocks;
84 void __iomem *regs;
85 struct work_struct probe_work;
86 const struct hda_tegra_soc *soc;
87 };
88
89 #ifdef CONFIG_PM
90 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
91 module_param(power_save, bint, 0644);
92 MODULE_PARM_DESC(power_save,
93 "Automatic power-saving timeout (in seconds, 0 = disable).");
94 #else
95 #define power_save 0
96 #endif
97
98 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
99
hda_tegra_init(struct hda_tegra * hda)100 static void hda_tegra_init(struct hda_tegra *hda)
101 {
102 u32 v;
103
104 /* Enable PCI access */
105 v = readl(hda->regs + HDA_IPFS_CONFIG);
106 v |= HDA_IPFS_EN_FPCI;
107 writel(v, hda->regs + HDA_IPFS_CONFIG);
108
109 /* Enable MEM/IO space and bus master */
110 v = readl(hda->regs + HDA_CFG_CMD);
111 v &= ~HDA_DISABLE_INTR;
112 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
113 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
114 writel(v, hda->regs + HDA_CFG_CMD);
115
116 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
117 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
118 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
119
120 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
121 v |= HDA_IPFS_EN_INTR;
122 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
123 }
124
125 /*
126 * power management
127 */
hda_tegra_suspend(struct device * dev)128 static int hda_tegra_suspend(struct device *dev)
129 {
130 struct snd_card *card = dev_get_drvdata(dev);
131 int rc;
132
133 rc = pm_runtime_force_suspend(dev);
134 if (rc < 0)
135 return rc;
136 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
137
138 return 0;
139 }
140
hda_tegra_resume(struct device * dev)141 static int hda_tegra_resume(struct device *dev)
142 {
143 struct snd_card *card = dev_get_drvdata(dev);
144 int rc;
145
146 rc = pm_runtime_force_resume(dev);
147 if (rc < 0)
148 return rc;
149 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
150
151 return 0;
152 }
153
hda_tegra_runtime_suspend(struct device * dev)154 static int hda_tegra_runtime_suspend(struct device *dev)
155 {
156 struct snd_card *card = dev_get_drvdata(dev);
157 struct azx *chip = card->private_data;
158 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
159
160 if (chip && chip->running) {
161 /* enable controller wake up event */
162 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
163 STATESTS_INT_MASK);
164
165 azx_stop_chip(chip);
166 azx_enter_link_reset(chip);
167 }
168 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
169
170 return 0;
171 }
172
hda_tegra_runtime_resume(struct device * dev)173 static int hda_tegra_runtime_resume(struct device *dev)
174 {
175 struct snd_card *card = dev_get_drvdata(dev);
176 struct azx *chip = card->private_data;
177 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
178 int rc;
179
180 if (!chip->running) {
181 rc = reset_control_bulk_assert(hda->nresets, hda->resets);
182 if (rc)
183 return rc;
184 }
185
186 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
187 if (rc != 0)
188 return rc;
189 if (chip->running) {
190 hda_tegra_init(hda);
191 azx_init_chip(chip, 1);
192 /* disable controller wake up event*/
193 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
194 ~STATESTS_INT_MASK);
195 } else {
196 usleep_range(10, 100);
197
198 rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
199 if (rc)
200 return rc;
201 }
202
203 return 0;
204 }
205
206 static const struct dev_pm_ops hda_tegra_pm = {
207 SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
208 RUNTIME_PM_OPS(hda_tegra_runtime_suspend, hda_tegra_runtime_resume, NULL)
209 };
210
hda_tegra_dev_disconnect(struct snd_device * device)211 static int hda_tegra_dev_disconnect(struct snd_device *device)
212 {
213 struct azx *chip = device->device_data;
214
215 chip->bus.shutdown = 1;
216 return 0;
217 }
218
219 /*
220 * destructor
221 */
hda_tegra_dev_free(struct snd_device * device)222 static int hda_tegra_dev_free(struct snd_device *device)
223 {
224 struct azx *chip = device->device_data;
225 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
226
227 cancel_work_sync(&hda->probe_work);
228 if (azx_bus(chip)->chip_init) {
229 azx_stop_all_streams(chip);
230 azx_stop_chip(chip);
231 }
232
233 azx_free_stream_pages(chip);
234 azx_free_streams(chip);
235 snd_hdac_bus_exit(azx_bus(chip));
236
237 return 0;
238 }
239
hda_tegra_init_chip(struct azx * chip,struct platform_device * pdev)240 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
241 {
242 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
243 struct hdac_bus *bus = azx_bus(chip);
244 struct resource *res;
245
246 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
247 if (IS_ERR(hda->regs))
248 return PTR_ERR(hda->regs);
249
250 bus->remap_addr = hda->regs + HDA_BAR0;
251 bus->addr = res->start + HDA_BAR0;
252
253 hda_tegra_init(hda);
254
255 return 0;
256 }
257
hda_tegra_first_init(struct azx * chip,struct platform_device * pdev)258 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
259 {
260 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
261 struct hdac_bus *bus = azx_bus(chip);
262 struct snd_card *card = chip->card;
263 int err;
264 unsigned short gcap;
265 int irq_id = platform_get_irq(pdev, 0);
266 const char *sname, *drv_name = "tegra-hda";
267 struct device_node *np = pdev->dev.of_node;
268
269 if (irq_id < 0)
270 return irq_id;
271
272 err = hda_tegra_init_chip(chip, pdev);
273 if (err)
274 return err;
275
276 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
277 IRQF_SHARED, KBUILD_MODNAME, chip);
278 if (err) {
279 dev_err(chip->card->dev,
280 "unable to request IRQ %d, disabling device\n",
281 irq_id);
282 return err;
283 }
284 bus->irq = irq_id;
285 bus->dma_stop_delay = 100;
286 card->sync_irq = bus->irq;
287
288 /*
289 * Tegra194 has 4 SDO lines and the STRIPE can be used to
290 * indicate how many of the SDO lines the stream should be
291 * striped. But GCAP register does not reflect the true
292 * capability of HW. Below workaround helps to fix this.
293 *
294 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
295 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
296 */
297 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
298 u32 val;
299
300 dev_info(card->dev, "Override SDO lines to %u\n",
301 TEGRA194_NUM_SDO_LINES);
302
303 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
304 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
305 writel(val, hda->regs + FPCI_DBG_CFG_2);
306 }
307
308 gcap = azx_readw(chip, GCAP);
309 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
310
311 chip->align_buffer_size = 1;
312
313 /* read number of streams from GCAP register instead of using
314 * hardcoded value
315 */
316 chip->capture_streams = (gcap >> 8) & 0x0f;
317
318 /* The GCAP register on Tegra234 implies no Input Streams(ISS) support,
319 * but the HW output stream descriptor programming should start with
320 * offset 0x20*4 from base stream descriptor address. This will be a
321 * problem while calculating the offset for output stream descriptor
322 * which will be considering input stream also. So here output stream
323 * starts with offset 0 which is wrong as HW register for output stream
324 * offset starts with 4.
325 */
326 if (of_device_is_compatible(np, "nvidia,tegra234-hda"))
327 chip->capture_streams = 4;
328
329 chip->playback_streams = (gcap >> 12) & 0x0f;
330 if (!chip->playback_streams && !chip->capture_streams) {
331 /* gcap didn't give any info, switching to old method */
332 chip->playback_streams = NUM_PLAYBACK_SD;
333 chip->capture_streams = NUM_CAPTURE_SD;
334 }
335 chip->capture_index_offset = 0;
336 chip->playback_index_offset = chip->capture_streams;
337 chip->num_streams = chip->playback_streams + chip->capture_streams;
338
339 /* initialize streams */
340 err = azx_init_streams(chip);
341 if (err < 0) {
342 dev_err(card->dev, "failed to initialize streams: %d\n", err);
343 return err;
344 }
345
346 err = azx_alloc_stream_pages(chip);
347 if (err < 0) {
348 dev_err(card->dev, "failed to allocate stream pages: %d\n",
349 err);
350 return err;
351 }
352
353 /* initialize chip */
354 azx_init_chip(chip, 1);
355
356 /*
357 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
358 * 4 SDO lines due to legacy design limitation. Following
359 * is, from HD Audio Specification (Revision 1.0a), used to
360 * control striping of the stream across multiple SDO lines
361 * for sample rates <= 48K.
362 *
363 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
364 *
365 * Due to legacy design issue it is recommended that above
366 * ratio must be greater than 8. Since number of SDO lines is
367 * in powers of 2, next available ratio is 16 which can be
368 * used as a limiting factor here.
369 */
370 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
371 chip->bus.core.sdo_limit = 16;
372
373 /* codec detection */
374 if (!bus->codec_mask) {
375 dev_err(card->dev, "no codecs found!\n");
376 return -ENODEV;
377 }
378
379 /* driver name */
380 strscpy(card->driver, drv_name, sizeof(card->driver));
381 /* shortname for card */
382 sname = of_get_property(np, "nvidia,model", NULL);
383 if (!sname)
384 sname = drv_name;
385 if (strlen(sname) > sizeof(card->shortname))
386 dev_info(card->dev, "truncating shortname for card\n");
387 strscpy(card->shortname, sname, sizeof(card->shortname));
388
389 /* longname for card */
390 snprintf(card->longname, sizeof(card->longname),
391 "%s at 0x%lx irq %i",
392 card->shortname, bus->addr, bus->irq);
393
394 return 0;
395 }
396
397 /*
398 * constructor
399 */
400
401 static void hda_tegra_probe_work(struct work_struct *work);
402
hda_tegra_create(struct snd_card * card,unsigned int driver_caps,struct hda_tegra * hda)403 static int hda_tegra_create(struct snd_card *card,
404 unsigned int driver_caps,
405 struct hda_tegra *hda)
406 {
407 static const struct snd_device_ops ops = {
408 .dev_disconnect = hda_tegra_dev_disconnect,
409 .dev_free = hda_tegra_dev_free,
410 };
411 struct azx *chip;
412 int err;
413
414 chip = &hda->chip;
415
416 mutex_init(&chip->open_mutex);
417 chip->card = card;
418 chip->ops = &hda_tegra_ops;
419 chip->driver_caps = driver_caps;
420 chip->driver_type = driver_caps & 0xff;
421 chip->dev_index = 0;
422 chip->jackpoll_interval = msecs_to_jiffies(5000);
423 INIT_LIST_HEAD(&chip->pcm_list);
424
425 chip->codec_probe_mask = -1;
426
427 chip->single_cmd = false;
428 chip->snoop = true;
429
430 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
431
432 err = azx_bus_init(chip, NULL);
433 if (err < 0)
434 return err;
435
436 chip->bus.core.sync_write = 0;
437 chip->bus.core.needs_damn_long_delay = 1;
438 chip->bus.core.aligned_mmio = 1;
439 chip->bus.jackpoll_in_suspend = 1;
440
441 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
442 if (err < 0) {
443 dev_err(card->dev, "Error creating device\n");
444 return err;
445 }
446
447 return 0;
448 }
449
450 static const struct hda_tegra_soc tegra30_data = {
451 .has_hda2codec_2x_reset = true,
452 .has_hda2hdmi = true,
453 };
454
455 static const struct hda_tegra_soc tegra194_data = {
456 .has_hda2codec_2x_reset = false,
457 .has_hda2hdmi = true,
458 };
459
460 static const struct hda_tegra_soc tegra234_data = {
461 .has_hda2codec_2x_reset = true,
462 .has_hda2hdmi = false,
463 };
464
465 static const struct of_device_id hda_tegra_match[] = {
466 { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
467 { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
468 { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data },
469 {},
470 };
471 MODULE_DEVICE_TABLE(of, hda_tegra_match);
472
hda_tegra_probe(struct platform_device * pdev)473 static int hda_tegra_probe(struct platform_device *pdev)
474 {
475 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
476 AZX_DCAPS_PM_RUNTIME |
477 AZX_DCAPS_4K_BDLE_BOUNDARY;
478 struct snd_card *card;
479 struct azx *chip;
480 struct hda_tegra *hda;
481 int err;
482
483 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
484 if (!hda)
485 return -ENOMEM;
486 hda->dev = &pdev->dev;
487 chip = &hda->chip;
488
489 hda->soc = of_device_get_match_data(&pdev->dev);
490
491 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
492 THIS_MODULE, 0, &card);
493 if (err < 0) {
494 dev_err(&pdev->dev, "Error creating card!\n");
495 return err;
496 }
497
498 hda->resets[hda->nresets++].id = "hda";
499
500 /*
501 * "hda2hdmi" is not applicable for Tegra234. This is because the
502 * codec is separate IP and not under display SOR partition now.
503 */
504 if (hda->soc->has_hda2hdmi)
505 hda->resets[hda->nresets++].id = "hda2hdmi";
506
507 /*
508 * "hda2codec_2x" reset is not present on Tegra194. Though DT would
509 * be updated to reflect this, but to have backward compatibility
510 * below is necessary.
511 */
512 if (hda->soc->has_hda2codec_2x_reset)
513 hda->resets[hda->nresets++].id = "hda2codec_2x";
514
515 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
516 hda->resets);
517 if (err)
518 goto out_free;
519
520 hda->clocks[hda->nclocks++].id = "hda";
521 if (hda->soc->has_hda2hdmi)
522 hda->clocks[hda->nclocks++].id = "hda2hdmi";
523 hda->clocks[hda->nclocks++].id = "hda2codec_2x";
524
525 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
526 if (err < 0)
527 goto out_free;
528
529 err = hda_tegra_create(card, driver_flags, hda);
530 if (err < 0)
531 goto out_free;
532 card->private_data = chip;
533
534 dev_set_drvdata(&pdev->dev, card);
535
536 pm_runtime_enable(hda->dev);
537 if (!azx_has_pm_runtime(chip))
538 pm_runtime_forbid(hda->dev);
539
540 schedule_work(&hda->probe_work);
541
542 return 0;
543
544 out_free:
545 snd_card_free(card);
546 return err;
547 }
548
hda_tegra_probe_work(struct work_struct * work)549 static void hda_tegra_probe_work(struct work_struct *work)
550 {
551 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
552 struct azx *chip = &hda->chip;
553 struct platform_device *pdev = to_platform_device(hda->dev);
554 int err;
555
556 pm_runtime_get_sync(hda->dev);
557 err = hda_tegra_first_init(chip, pdev);
558 if (err < 0)
559 goto out_free;
560
561 /* create codec instances */
562 err = azx_probe_codecs(chip, 8);
563 if (err < 0)
564 goto out_free;
565
566 err = azx_codec_configure(chip);
567 if (err < 0)
568 goto out_free;
569
570 err = snd_card_register(chip->card);
571 if (err < 0)
572 goto out_free;
573
574 chip->running = 1;
575 snd_hda_set_power_save(&chip->bus, power_save * 1000);
576
577 out_free:
578 pm_runtime_put(hda->dev);
579 return; /* no error return from async probe */
580 }
581
hda_tegra_remove(struct platform_device * pdev)582 static void hda_tegra_remove(struct platform_device *pdev)
583 {
584 snd_card_free(dev_get_drvdata(&pdev->dev));
585 pm_runtime_disable(&pdev->dev);
586 }
587
hda_tegra_shutdown(struct platform_device * pdev)588 static void hda_tegra_shutdown(struct platform_device *pdev)
589 {
590 struct snd_card *card = dev_get_drvdata(&pdev->dev);
591 struct azx *chip;
592
593 if (!card)
594 return;
595 chip = card->private_data;
596 if (chip && chip->running)
597 azx_stop_chip(chip);
598 }
599
600 static struct platform_driver tegra_platform_hda = {
601 .driver = {
602 .name = "tegra-hda",
603 .pm = pm_ptr(&hda_tegra_pm),
604 .of_match_table = hda_tegra_match,
605 },
606 .probe = hda_tegra_probe,
607 .remove = hda_tegra_remove,
608 .shutdown = hda_tegra_shutdown,
609 };
610 module_platform_driver(tegra_platform_hda);
611
612 MODULE_DESCRIPTION("Tegra HDA bus driver");
613 MODULE_LICENSE("GPL v2");
614