1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
4 */
5
6/dts-v1/;
7#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8#include <dt-bindings/clock/sophgo,sg2042-pll.h>
9#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/reset/sophgo,sg2042-reset.h>
12
13#include "sg2042-cpus.dtsi"
14
15/ {
16	compatible = "sophgo,sg2042";
17	#address-cells = <2>;
18	#size-cells = <2>;
19	dma-noncoherent;
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	cgi_main: oscillator0 {
26		compatible = "fixed-clock";
27		clock-output-names = "cgi_main";
28		#clock-cells = <0>;
29	};
30
31	cgi_dpll0: oscillator1 {
32		compatible = "fixed-clock";
33		clock-output-names = "cgi_dpll0";
34		#clock-cells = <0>;
35	};
36
37	cgi_dpll1: oscillator2 {
38		compatible = "fixed-clock";
39		clock-output-names = "cgi_dpll1";
40		#clock-cells = <0>;
41	};
42
43	soc: soc {
44		compatible = "simple-bus";
45		#address-cells = <2>;
46		#size-cells = <2>;
47		interrupt-parent = <&intc>;
48		ranges;
49
50		i2c0: i2c@7030005000 {
51			compatible = "snps,designware-i2c";
52			reg = <0x70 0x30005000 0x0 0x1000>;
53			#address-cells = <1>;
54			#size-cells = <0>;
55			clocks = <&clkgen GATE_CLK_APB_I2C>;
56			clock-names = "ref";
57			clock-frequency = <100000>;
58			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
59			resets = <&rstgen RST_I2C0>;
60			status = "disabled";
61		};
62
63		i2c1: i2c@7030006000 {
64			compatible = "snps,designware-i2c";
65			reg = <0x70 0x30006000 0x0 0x1000>;
66			#address-cells = <1>;
67			#size-cells = <0>;
68			clocks = <&clkgen GATE_CLK_APB_I2C>;
69			clock-names = "ref";
70			clock-frequency = <100000>;
71			interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
72			resets = <&rstgen RST_I2C1>;
73			status = "disabled";
74		};
75
76		i2c2: i2c@7030007000 {
77			compatible = "snps,designware-i2c";
78			reg = <0x70 0x30007000 0x0 0x1000>;
79			#address-cells = <1>;
80			#size-cells = <0>;
81			clocks = <&clkgen GATE_CLK_APB_I2C>;
82			clock-names = "ref";
83			clock-frequency = <100000>;
84			interrupts = <103 IRQ_TYPE_LEVEL_HIGH>;
85			resets = <&rstgen RST_I2C2>;
86			status = "disabled";
87		};
88
89		i2c3: i2c@7030008000 {
90			compatible = "snps,designware-i2c";
91			reg = <0x70 0x30008000 0x0 0x1000>;
92			#address-cells = <1>;
93			#size-cells = <0>;
94			clocks = <&clkgen GATE_CLK_APB_I2C>;
95			clock-names = "ref";
96			clock-frequency = <100000>;
97			interrupts = <104 IRQ_TYPE_LEVEL_HIGH>;
98			resets = <&rstgen RST_I2C3>;
99			status = "disabled";
100		};
101
102		gpio0: gpio@7030009000 {
103			compatible = "snps,dw-apb-gpio";
104			reg = <0x70 0x30009000 0x0 0x400>;
105			#address-cells = <1>;
106			#size-cells = <0>;
107			clocks = <&clkgen GATE_CLK_APB_GPIO>,
108				 <&clkgen GATE_CLK_GPIO_DB>;
109			clock-names = "bus", "db";
110
111			port0a: gpio-controller@0 {
112				compatible = "snps,dw-apb-gpio-port";
113				gpio-controller;
114				#gpio-cells = <2>;
115				ngpios = <32>;
116				reg = <0>;
117				interrupt-controller;
118				#interrupt-cells = <2>;
119				interrupt-parent = <&intc>;
120				interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
121			};
122		};
123
124		gpio1: gpio@703000a000 {
125			compatible = "snps,dw-apb-gpio";
126			reg = <0x70 0x3000a000 0x0 0x400>;
127			#address-cells = <1>;
128			#size-cells = <0>;
129			clocks = <&clkgen GATE_CLK_APB_GPIO>,
130				 <&clkgen GATE_CLK_GPIO_DB>;
131			clock-names = "bus", "db";
132
133			port1a: gpio-controller@0 {
134				compatible = "snps,dw-apb-gpio-port";
135				gpio-controller;
136				#gpio-cells = <2>;
137				ngpios = <32>;
138				reg = <0>;
139				interrupt-controller;
140				#interrupt-cells = <2>;
141				interrupt-parent = <&intc>;
142				interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
143			};
144		};
145
146		gpio2: gpio@703000b000 {
147			compatible = "snps,dw-apb-gpio";
148			reg = <0x70 0x3000b000 0x0 0x400>;
149			#address-cells = <1>;
150			#size-cells = <0>;
151			clocks = <&clkgen GATE_CLK_APB_GPIO>,
152				 <&clkgen GATE_CLK_GPIO_DB>;
153			clock-names = "bus", "db";
154
155			port2a: gpio-controller@0 {
156				compatible = "snps,dw-apb-gpio-port";
157				gpio-controller;
158				#gpio-cells = <2>;
159				ngpios = <32>;
160				reg = <0>;
161				interrupt-controller;
162				#interrupt-cells = <2>;
163				interrupt-parent = <&intc>;
164				interrupts = <98 IRQ_TYPE_LEVEL_HIGH>;
165			};
166		};
167
168		pwm: pwm@703000c000 {
169			compatible = "sophgo,sg2042-pwm";
170			reg = <0x70 0x3000c000 0x0 0x20>;
171			#pwm-cells = <3>;
172			clocks = <&clkgen GATE_CLK_APB_PWM>;
173			clock-names = "apb";
174			resets = <&rstgen RST_PWM>;
175		};
176
177		pllclk: clock-controller@70300100c0 {
178			compatible = "sophgo,sg2042-pll";
179			reg = <0x70 0x300100c0 0x0 0x40>;
180			clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
181			clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
182			#clock-cells = <1>;
183		};
184
185		msi: msi-controller@7030010304 {
186			compatible = "sophgo,sg2042-msi";
187			reg = <0x70 0x30010304 0x0 0x4>,
188			      <0x70 0x30010300 0x0 0x4>;
189			reg-names = "clr", "doorbell";
190			msi-controller;
191			#msi-cells = <0>;
192			msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>;
193		};
194
195		rpgate: clock-controller@7030010368 {
196			compatible = "sophgo,sg2042-rpgate";
197			reg = <0x70 0x30010368 0x0 0x98>;
198			clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
199			clock-names = "rpgate";
200			#clock-cells = <1>;
201		};
202
203		clkgen: clock-controller@7030012000 {
204			compatible = "sophgo,sg2042-clkgen";
205			reg = <0x70 0x30012000 0x0 0x1000>;
206			clocks = <&pllclk MPLL_CLK>,
207				 <&pllclk FPLL_CLK>,
208				 <&pllclk DPLL0_CLK>,
209				 <&pllclk DPLL1_CLK>;
210			clock-names = "mpll",
211				      "fpll",
212				      "dpll0",
213				      "dpll1";
214			#clock-cells = <1>;
215		};
216
217		clint_mswi: interrupt-controller@7094000000 {
218			compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
219			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
220			interrupts-extended = <&cpu0_intc 3>,
221					      <&cpu1_intc 3>,
222					      <&cpu2_intc 3>,
223					      <&cpu3_intc 3>,
224					      <&cpu4_intc 3>,
225					      <&cpu5_intc 3>,
226					      <&cpu6_intc 3>,
227					      <&cpu7_intc 3>,
228					      <&cpu8_intc 3>,
229					      <&cpu9_intc 3>,
230					      <&cpu10_intc 3>,
231					      <&cpu11_intc 3>,
232					      <&cpu12_intc 3>,
233					      <&cpu13_intc 3>,
234					      <&cpu14_intc 3>,
235					      <&cpu15_intc 3>,
236					      <&cpu16_intc 3>,
237					      <&cpu17_intc 3>,
238					      <&cpu18_intc 3>,
239					      <&cpu19_intc 3>,
240					      <&cpu20_intc 3>,
241					      <&cpu21_intc 3>,
242					      <&cpu22_intc 3>,
243					      <&cpu23_intc 3>,
244					      <&cpu24_intc 3>,
245					      <&cpu25_intc 3>,
246					      <&cpu26_intc 3>,
247					      <&cpu27_intc 3>,
248					      <&cpu28_intc 3>,
249					      <&cpu29_intc 3>,
250					      <&cpu30_intc 3>,
251					      <&cpu31_intc 3>,
252					      <&cpu32_intc 3>,
253					      <&cpu33_intc 3>,
254					      <&cpu34_intc 3>,
255					      <&cpu35_intc 3>,
256					      <&cpu36_intc 3>,
257					      <&cpu37_intc 3>,
258					      <&cpu38_intc 3>,
259					      <&cpu39_intc 3>,
260					      <&cpu40_intc 3>,
261					      <&cpu41_intc 3>,
262					      <&cpu42_intc 3>,
263					      <&cpu43_intc 3>,
264					      <&cpu44_intc 3>,
265					      <&cpu45_intc 3>,
266					      <&cpu46_intc 3>,
267					      <&cpu47_intc 3>,
268					      <&cpu48_intc 3>,
269					      <&cpu49_intc 3>,
270					      <&cpu50_intc 3>,
271					      <&cpu51_intc 3>,
272					      <&cpu52_intc 3>,
273					      <&cpu53_intc 3>,
274					      <&cpu54_intc 3>,
275					      <&cpu55_intc 3>,
276					      <&cpu56_intc 3>,
277					      <&cpu57_intc 3>,
278					      <&cpu58_intc 3>,
279					      <&cpu59_intc 3>,
280					      <&cpu60_intc 3>,
281					      <&cpu61_intc 3>,
282					      <&cpu62_intc 3>,
283					      <&cpu63_intc 3>;
284		};
285
286		clint_mtimer0: timer@70ac004000 {
287			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
288			reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
289			reg-names = "mtimecmp";
290			interrupts-extended = <&cpu0_intc 7>,
291					      <&cpu1_intc 7>,
292					      <&cpu2_intc 7>,
293					      <&cpu3_intc 7>;
294		};
295
296		clint_mtimer1: timer@70ac014000 {
297			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
298			reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
299			reg-names = "mtimecmp";
300			interrupts-extended = <&cpu4_intc 7>,
301					      <&cpu5_intc 7>,
302					      <&cpu6_intc 7>,
303					      <&cpu7_intc 7>;
304		};
305
306		clint_mtimer2: timer@70ac024000 {
307			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
308			reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
309			reg-names = "mtimecmp";
310			interrupts-extended = <&cpu8_intc 7>,
311					      <&cpu9_intc 7>,
312					      <&cpu10_intc 7>,
313					      <&cpu11_intc 7>;
314		};
315
316		clint_mtimer3: timer@70ac034000 {
317			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
318			reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
319			reg-names = "mtimecmp";
320			interrupts-extended = <&cpu12_intc 7>,
321					      <&cpu13_intc 7>,
322					      <&cpu14_intc 7>,
323					      <&cpu15_intc 7>;
324		};
325
326		clint_mtimer4: timer@70ac044000 {
327			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
328			reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
329			reg-names = "mtimecmp";
330			interrupts-extended = <&cpu16_intc 7>,
331					      <&cpu17_intc 7>,
332					      <&cpu18_intc 7>,
333					      <&cpu19_intc 7>;
334		};
335
336		clint_mtimer5: timer@70ac054000 {
337			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
338			reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
339			reg-names = "mtimecmp";
340			interrupts-extended = <&cpu20_intc 7>,
341					      <&cpu21_intc 7>,
342					      <&cpu22_intc 7>,
343					      <&cpu23_intc 7>;
344		};
345
346		clint_mtimer6: timer@70ac064000 {
347			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
348			reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
349			reg-names = "mtimecmp";
350			interrupts-extended = <&cpu24_intc 7>,
351					      <&cpu25_intc 7>,
352					      <&cpu26_intc 7>,
353					      <&cpu27_intc 7>;
354		};
355
356		clint_mtimer7: timer@70ac074000 {
357			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
358			reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
359			reg-names = "mtimecmp";
360			interrupts-extended = <&cpu28_intc 7>,
361					      <&cpu29_intc 7>,
362					      <&cpu30_intc 7>,
363					      <&cpu31_intc 7>;
364		};
365
366		clint_mtimer8: timer@70ac084000 {
367			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
368			reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
369			reg-names = "mtimecmp";
370			interrupts-extended = <&cpu32_intc 7>,
371					      <&cpu33_intc 7>,
372					      <&cpu34_intc 7>,
373					      <&cpu35_intc 7>;
374		};
375
376		clint_mtimer9: timer@70ac094000 {
377			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
378			reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
379			reg-names = "mtimecmp";
380			interrupts-extended = <&cpu36_intc 7>,
381					      <&cpu37_intc 7>,
382					      <&cpu38_intc 7>,
383					      <&cpu39_intc 7>;
384		};
385
386		clint_mtimer10: timer@70ac0a4000 {
387			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
388			reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
389			reg-names = "mtimecmp";
390			interrupts-extended = <&cpu40_intc 7>,
391					      <&cpu41_intc 7>,
392					      <&cpu42_intc 7>,
393					      <&cpu43_intc 7>;
394		};
395
396		clint_mtimer11: timer@70ac0b4000 {
397			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
398			reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
399			reg-names = "mtimecmp";
400			interrupts-extended = <&cpu44_intc 7>,
401					      <&cpu45_intc 7>,
402					      <&cpu46_intc 7>,
403					      <&cpu47_intc 7>;
404		};
405
406		clint_mtimer12: timer@70ac0c4000 {
407			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
408			reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
409			reg-names = "mtimecmp";
410			interrupts-extended = <&cpu48_intc 7>,
411					      <&cpu49_intc 7>,
412					      <&cpu50_intc 7>,
413					      <&cpu51_intc 7>;
414		};
415
416		clint_mtimer13: timer@70ac0d4000 {
417			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
418			reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
419			reg-names = "mtimecmp";
420			interrupts-extended = <&cpu52_intc 7>,
421					      <&cpu53_intc 7>,
422					      <&cpu54_intc 7>,
423					      <&cpu55_intc 7>;
424		};
425
426		clint_mtimer14: timer@70ac0e4000 {
427			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
428			reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
429			reg-names = "mtimecmp";
430			interrupts-extended = <&cpu56_intc 7>,
431					      <&cpu57_intc 7>,
432					      <&cpu58_intc 7>,
433					      <&cpu59_intc 7>;
434		};
435
436		clint_mtimer15: timer@70ac0f4000 {
437			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
438			reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
439			reg-names = "mtimecmp";
440			interrupts-extended = <&cpu60_intc 7>,
441					      <&cpu61_intc 7>,
442					      <&cpu62_intc 7>,
443					      <&cpu63_intc 7>;
444		};
445
446		intc: interrupt-controller@7090000000 {
447			compatible = "sophgo,sg2042-plic", "thead,c900-plic";
448			#address-cells = <0>;
449			#interrupt-cells = <2>;
450			reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
451			interrupt-controller;
452			interrupts-extended =
453				<&cpu0_intc 11>,  <&cpu0_intc 9>,
454				<&cpu1_intc 11>,  <&cpu1_intc 9>,
455				<&cpu2_intc 11>,  <&cpu2_intc 9>,
456				<&cpu3_intc 11>,  <&cpu3_intc 9>,
457				<&cpu4_intc 11>,  <&cpu4_intc 9>,
458				<&cpu5_intc 11>,  <&cpu5_intc 9>,
459				<&cpu6_intc 11>,  <&cpu6_intc 9>,
460				<&cpu7_intc 11>,  <&cpu7_intc 9>,
461				<&cpu8_intc 11>,  <&cpu8_intc 9>,
462				<&cpu9_intc 11>,  <&cpu9_intc 9>,
463				<&cpu10_intc 11>, <&cpu10_intc 9>,
464				<&cpu11_intc 11>, <&cpu11_intc 9>,
465				<&cpu12_intc 11>, <&cpu12_intc 9>,
466				<&cpu13_intc 11>, <&cpu13_intc 9>,
467				<&cpu14_intc 11>, <&cpu14_intc 9>,
468				<&cpu15_intc 11>, <&cpu15_intc 9>,
469				<&cpu16_intc 11>, <&cpu16_intc 9>,
470				<&cpu17_intc 11>, <&cpu17_intc 9>,
471				<&cpu18_intc 11>, <&cpu18_intc 9>,
472				<&cpu19_intc 11>, <&cpu19_intc 9>,
473				<&cpu20_intc 11>, <&cpu20_intc 9>,
474				<&cpu21_intc 11>, <&cpu21_intc 9>,
475				<&cpu22_intc 11>, <&cpu22_intc 9>,
476				<&cpu23_intc 11>, <&cpu23_intc 9>,
477				<&cpu24_intc 11>, <&cpu24_intc 9>,
478				<&cpu25_intc 11>, <&cpu25_intc 9>,
479				<&cpu26_intc 11>, <&cpu26_intc 9>,
480				<&cpu27_intc 11>, <&cpu27_intc 9>,
481				<&cpu28_intc 11>, <&cpu28_intc 9>,
482				<&cpu29_intc 11>, <&cpu29_intc 9>,
483				<&cpu30_intc 11>, <&cpu30_intc 9>,
484				<&cpu31_intc 11>, <&cpu31_intc 9>,
485				<&cpu32_intc 11>, <&cpu32_intc 9>,
486				<&cpu33_intc 11>, <&cpu33_intc 9>,
487				<&cpu34_intc 11>, <&cpu34_intc 9>,
488				<&cpu35_intc 11>, <&cpu35_intc 9>,
489				<&cpu36_intc 11>, <&cpu36_intc 9>,
490				<&cpu37_intc 11>, <&cpu37_intc 9>,
491				<&cpu38_intc 11>, <&cpu38_intc 9>,
492				<&cpu39_intc 11>, <&cpu39_intc 9>,
493				<&cpu40_intc 11>, <&cpu40_intc 9>,
494				<&cpu41_intc 11>, <&cpu41_intc 9>,
495				<&cpu42_intc 11>, <&cpu42_intc 9>,
496				<&cpu43_intc 11>, <&cpu43_intc 9>,
497				<&cpu44_intc 11>, <&cpu44_intc 9>,
498				<&cpu45_intc 11>, <&cpu45_intc 9>,
499				<&cpu46_intc 11>, <&cpu46_intc 9>,
500				<&cpu47_intc 11>, <&cpu47_intc 9>,
501				<&cpu48_intc 11>, <&cpu48_intc 9>,
502				<&cpu49_intc 11>, <&cpu49_intc 9>,
503				<&cpu50_intc 11>, <&cpu50_intc 9>,
504				<&cpu51_intc 11>, <&cpu51_intc 9>,
505				<&cpu52_intc 11>, <&cpu52_intc 9>,
506				<&cpu53_intc 11>, <&cpu53_intc 9>,
507				<&cpu54_intc 11>, <&cpu54_intc 9>,
508				<&cpu55_intc 11>, <&cpu55_intc 9>,
509				<&cpu56_intc 11>, <&cpu56_intc 9>,
510				<&cpu57_intc 11>, <&cpu57_intc 9>,
511				<&cpu58_intc 11>, <&cpu58_intc 9>,
512				<&cpu59_intc 11>, <&cpu59_intc 9>,
513				<&cpu60_intc 11>, <&cpu60_intc 9>,
514				<&cpu61_intc 11>, <&cpu61_intc 9>,
515				<&cpu62_intc 11>, <&cpu62_intc 9>,
516				<&cpu63_intc 11>, <&cpu63_intc 9>;
517			riscv,ndev = <224>;
518		};
519
520		rstgen: reset-controller@7030013000 {
521			compatible = "sophgo,sg2042-reset";
522			reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
523			#reset-cells = <1>;
524		};
525
526		uart0: serial@7040000000 {
527			compatible = "snps,dw-apb-uart";
528			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
529			interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
530			clock-frequency = <500000000>;
531			clocks = <&clkgen GATE_CLK_UART_500M>,
532				 <&clkgen GATE_CLK_APB_UART>;
533			clock-names = "baudclk", "apb_pclk";
534			reg-shift = <2>;
535			reg-io-width = <4>;
536			resets = <&rstgen RST_UART0>;
537			status = "disabled";
538		};
539
540		emmc: mmc@704002a000 {
541			compatible = "sophgo,sg2042-dwcmshc";
542			reg = <0x70 0x4002a000 0x0 0x1000>;
543			interrupt-parent = <&intc>;
544			interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
545			clocks = <&clkgen GATE_CLK_EMMC_100M>,
546				 <&clkgen GATE_CLK_AXI_EMMC>,
547				 <&clkgen GATE_CLK_100K_EMMC>;
548			clock-names = "core",
549				      "bus",
550				      "timer";
551			status = "disabled";
552		};
553
554		sd: mmc@704002b000 {
555			compatible = "sophgo,sg2042-dwcmshc";
556			reg = <0x70 0x4002b000 0x0 0x1000>;
557			interrupt-parent = <&intc>;
558			interrupts = <136 IRQ_TYPE_LEVEL_HIGH>;
559			clocks = <&clkgen GATE_CLK_SD_100M>,
560				 <&clkgen GATE_CLK_AXI_SD>,
561				 <&clkgen GATE_CLK_100K_SD>;
562			clock-names = "core",
563				      "bus",
564				      "timer";
565			status = "disabled";
566		};
567	};
568};
569