1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree file for the J722S EVM 4 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Schematics: https://www.ti.com/lit/zip/sprr495 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy.h> 13#include "k3-j722s.dtsi" 14#include "k3-serdes.h" 15 16/ { 17 compatible = "ti,j722s-evm", "ti,j722s"; 18 model = "Texas Instruments J722S EVM"; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart5; 24 mmc0 = &sdhci0; 25 mmc1 = &sdhci1; 26 }; 27 28 chosen { 29 stdout-path = &main_uart0; 30 }; 31 32 memory@80000000 { 33 /* 8G RAM */ 34 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 35 <0x00000008 0x80000000 0x00000001 0x80000000>; 36 device_type = "memory"; 37 bootph-pre-ram; 38 }; 39 40 reserved_memory: reserved-memory { 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges; 44 45 secure_tfa_ddr: tfa@9e780000 { 46 reg = <0x00 0x9e780000 0x00 0x80000>; 47 no-map; 48 }; 49 50 secure_ddr: optee@9e800000 { 51 reg = <0x00 0x9e800000 0x00 0x01800000>; 52 no-map; 53 }; 54 55 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa0000000 0x00 0x100000>; 58 no-map; 59 }; 60 61 wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa0100000 0x00 0xf00000>; 64 no-map; 65 }; 66 67 mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa1000000 0x00 0x100000>; 70 no-map; 71 }; 72 73 mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa1100000 0x00 0xf00000>; 76 no-map; 77 }; 78 79 main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa2000000 0x00 0x100000>; 82 no-map; 83 }; 84 85 main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa2100000 0x00 0xf00000>; 88 no-map; 89 }; 90 91 c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa3000000 0x00 0x100000>; 94 no-map; 95 }; 96 97 c7x_0_memory_region: c7x-memory@a3100000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa3100000 0x00 0xf00000>; 100 no-map; 101 }; 102 103 c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa4000000 0x00 0x100000>; 106 no-map; 107 }; 108 109 c7x_1_memory_region: c7x-memory@a4100000 { 110 compatible = "shared-dma-pool"; 111 reg = <0x00 0xa4100000 0x00 0xf00000>; 112 no-map; 113 }; 114 115 rtos_ipc_memory_region: ipc-memories@a5000000 { 116 reg = <0x00 0xa5000000 0x00 0x1c00000>; 117 alignment = <0x1000>; 118 no-map; 119 }; 120 }; 121 122 vmain_pd: regulator-0 { 123 /* TPS65988 PD CONTROLLER OUTPUT */ 124 compatible = "regulator-fixed"; 125 regulator-name = "vmain_pd"; 126 regulator-min-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>; 128 regulator-always-on; 129 regulator-boot-on; 130 bootph-all; 131 }; 132 133 vsys_5v0: regulator-vsys5v0 { 134 /* Output of LM5140 */ 135 compatible = "regulator-fixed"; 136 regulator-name = "vsys_5v0"; 137 regulator-min-microvolt = <5000000>; 138 regulator-max-microvolt = <5000000>; 139 vin-supply = <&vmain_pd>; 140 regulator-always-on; 141 regulator-boot-on; 142 }; 143 144 vdd_mmc1: regulator-mmc1 { 145 /* TPS22918DBVR */ 146 compatible = "regulator-fixed"; 147 regulator-name = "vdd_mmc1"; 148 regulator-min-microvolt = <3300000>; 149 regulator-max-microvolt = <3300000>; 150 regulator-boot-on; 151 enable-active-high; 152 gpio = <&exp1 15 GPIO_ACTIVE_HIGH>; 153 bootph-all; 154 }; 155 156 vdd_sd_dv: regulator-TLV71033 { 157 compatible = "regulator-gpio"; 158 regulator-name = "tlv71033"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&vdd_sd_dv_pins_default>; 161 regulator-min-microvolt = <1800000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 vin-supply = <&vsys_5v0>; 165 gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>; 166 states = <1800000 0x0>, 167 <3300000 0x1>; 168 }; 169 170 vsys_io_3v3: regulator-vsys-io-3v3 { 171 compatible = "regulator-fixed"; 172 regulator-name = "vsys_io_3v3"; 173 regulator-min-microvolt = <3300000>; 174 regulator-max-microvolt = <3300000>; 175 regulator-always-on; 176 regulator-boot-on; 177 }; 178 179 vsys_io_1v8: regulator-vsys-io-1v8 { 180 compatible = "regulator-fixed"; 181 regulator-name = "vsys_io_1v8"; 182 regulator-min-microvolt = <1800000>; 183 regulator-max-microvolt = <1800000>; 184 regulator-always-on; 185 regulator-boot-on; 186 }; 187 188 vsys_io_1v2: regulator-vsys-io-1v2 { 189 compatible = "regulator-fixed"; 190 regulator-name = "vsys_io_1v2"; 191 regulator-min-microvolt = <1200000>; 192 regulator-max-microvolt = <1200000>; 193 regulator-always-on; 194 regulator-boot-on; 195 }; 196 197 codec_audio: sound { 198 compatible = "simple-audio-card"; 199 simple-audio-card,name = "J722S-EVM"; 200 simple-audio-card,widgets = 201 "Headphone", "Headphone Jack", 202 "Line", "Line In", 203 "Microphone", "Microphone Jack"; 204 simple-audio-card,routing = 205 "Headphone Jack", "HPLOUT", 206 "Headphone Jack", "HPROUT", 207 "LINE1L", "Line In", 208 "LINE1R", "Line In", 209 "MIC3R", "Microphone Jack", 210 "Microphone Jack", "Mic Bias"; 211 simple-audio-card,format = "dsp_b"; 212 simple-audio-card,bitclock-master = <&sound_master>; 213 simple-audio-card,frame-master = <&sound_master>; 214 simple-audio-card,bitclock-inversion; 215 216 simple-audio-card,cpu { 217 sound-dai = <&mcasp1>; 218 }; 219 220 sound_master: simple-audio-card,codec { 221 sound-dai = <&tlv320aic3106>; 222 clocks = <&audio_refclk1>; 223 }; 224 }; 225 226 transceiver0: can-phy0 { 227 compatible = "ti,tcan1042"; 228 #phy-cells = <0>; 229 max-bitrate = <5000000>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 232 standby-gpios = <&mcu_gpio0 12 GPIO_ACTIVE_HIGH>; 233 }; 234 235 transceiver1: can-phy1 { 236 compatible = "ti,tcan1042"; 237 #phy-cells = <0>; 238 max-bitrate = <5000000>; 239 }; 240 241 transceiver2: can-phy2 { 242 compatible = "ti,tcan1042"; 243 #phy-cells = <0>; 244 max-bitrate = <5000000>; 245 standby-gpios = <&exp1 17 GPIO_ACTIVE_HIGH>; 246 }; 247}; 248 249&main_pmx0 { 250 251 main_mcan0_pins_default: main-mcan0-default-pins { 252 pinctrl-single,pins = < 253 J722S_IOPAD(0x1dc, PIN_INPUT, 0) /* (C22) MCAN0_RX */ 254 J722S_IOPAD(0x1d8, PIN_OUTPUT, 0) /*(D22) MCAN0_TX */ 255 >; 256 }; 257 258 main_i2c0_pins_default: main-i2c0-default-pins { 259 pinctrl-single,pins = < 260 J722S_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D23) I2C0_SCL */ 261 J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ 262 >; 263 bootph-all; 264 }; 265 266 main_i2c2_pins_default: main-i2c2-default-pins { 267 pinctrl-single,pins = < 268 J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ 269 J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ 270 >; 271 }; 272 273 main_uart0_pins_default: main-uart0-default-pins { 274 pinctrl-single,pins = < 275 J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ 276 J722S_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ 277 >; 278 bootph-all; 279 }; 280 281 main_uart5_pins_default: main-uart5-default-pins { 282 pinctrl-single,pins = < 283 J722S_IOPAD(0x0108, PIN_INPUT, 3) /* (J27) UART5_RXD */ 284 J722S_IOPAD(0x010c, PIN_OUTPUT, 3) /* (H27) UART5_TXD */ 285 >; 286 }; 287 288 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 289 pinctrl-single,pins = < 290 J722S_IOPAD(0x0120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ 291 >; 292 bootph-all; 293 }; 294 295 main_mmc1_pins_default: main-mmc1-default-pins { 296 pinctrl-single,pins = < 297 J722S_IOPAD(0x023c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ 298 J722S_IOPAD(0x0234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ 299 J722S_IOPAD(0x0230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ 300 J722S_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H20) MMC1_DAT1 */ 301 J722S_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (J23) MMC1_DAT2 */ 302 J722S_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ 303 J722S_IOPAD(0x0240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ 304 >; 305 bootph-all; 306 }; 307 308 mdio_pins_default: mdio-default-pins { 309 pinctrl-single,pins = < 310 J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ 311 J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ 312 >; 313 }; 314 315 ospi0_pins_default: ospi0-default-pins { 316 pinctrl-single,pins = < 317 J722S_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ 318 J722S_IOPAD(0x002c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ 319 J722S_IOPAD(0x000c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ 320 J722S_IOPAD(0x0010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ 321 J722S_IOPAD(0x0014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ 322 J722S_IOPAD(0x0018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ 323 J722S_IOPAD(0x001c, PIN_INPUT, 0) /* (L21) OSPI0_D4 */ 324 J722S_IOPAD(0x0020, PIN_INPUT, 0) /* (M26) OSPI0_D5 */ 325 J722S_IOPAD(0x0024, PIN_INPUT, 0) /* (N27) OSPI0_D6 */ 326 J722S_IOPAD(0x0028, PIN_INPUT, 0) /* (M27) OSPI0_D7 */ 327 J722S_IOPAD(0x0008, PIN_INPUT, 0) /* (L22) OSPI0_DQS */ 328 >; 329 bootph-all; 330 }; 331 332 rgmii1_pins_default: rgmii1-default-pins { 333 pinctrl-single,pins = < 334 J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ 335 J722S_IOPAD(0x0150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ 336 J722S_IOPAD(0x0154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ 337 J722S_IOPAD(0x0158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ 338 J722S_IOPAD(0x0148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ 339 J722S_IOPAD(0x0144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ 340 J722S_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ 341 J722S_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ 342 J722S_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ 343 J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ 344 J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ 345 J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ 346 >; 347 }; 348 349 main_usb1_pins_default: main-usb1-default-pins { 350 pinctrl-single,pins = < 351 J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ 352 >; 353 }; 354 355 main_mcasp1_pins_default: main-mcasp1-default-pins { 356 pinctrl-single,pins = < 357 J722S_IOPAD(0x0090, PIN_INPUT, 2) /* (P27) GPMC0_BE0n_CLE.MCASP1_ACLKX */ 358 J722S_IOPAD(0x0098, PIN_INPUT, 2) /* (V21) GPMC0_WAIT0.MCASP1_AFSX */ 359 J722S_IOPAD(0x008c, PIN_OUTPUT, 2) /* (N23) GPMC0_WEn.MCASP1_AXR0 */ 360 J722S_IOPAD(0x0084, PIN_INPUT, 2) /* (N21) GPMC0_ADVn_ALE.MCASP1_AXR2 */ 361 >; 362 }; 363 364 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 365 pinctrl-single,pins = < 366 J722S_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ 367 >; 368 }; 369 370 pmic_irq_pins_default: pmic-irq-default-pins { 371 pinctrl-single,pins = < 372 J722S_IOPAD(0x030, PIN_INPUT, 7) /* (K23) GPIO0_12 */ 373 >; 374 }; 375 376}; 377 378&cpsw3g { 379 status = "okay"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&rgmii1_pins_default>; 382}; 383 384&cpsw3g_mdio { 385 status = "okay"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&mdio_pins_default>; 388 389 cpsw3g_phy0: ethernet-phy@0 { 390 reg = <0>; 391 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 392 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 393 ti,min-output-impedance; 394 }; 395}; 396 397&cpsw_port1 { 398 phy-mode = "rgmii-rxid"; 399 phy-handle = <&cpsw3g_phy0>; 400 status = "okay"; 401}; 402 403&main_gpio1 { 404 status = "okay"; 405}; 406 407&main_uart0 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&main_uart0_pins_default>; 410 status = "okay"; 411 bootph-all; 412}; 413 414&main_uart5 { 415 /* MAIN UART 5 is used by System firmware */ 416 pinctrl-names = "default"; 417 pinctrl-0 = <&main_uart5_pins_default>; 418 status = "reserved"; 419}; 420 421&mcu_pmx0 { 422 423 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 424 pinctrl-single,pins = < 425 J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ 426 J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ 427 >; 428 }; 429 430 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 431 pinctrl-single,pins = < 432 J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ 433 J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ 434 >; 435 }; 436 437 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 438 pinctrl-single,pins = < 439 J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ 440 J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */ 441 >; 442 }; 443 444 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 445 pinctrl-single,pins = < 446 J722S_MCU_IOPAD(0x0030, PIN_OUTPUT, 7) /* (C3) MCU_GPIO0_12 */ 447 >; 448 }; 449 450 wkup_uart0_pins_default: wkup-uart0-default-pins { 451 pinctrl-single,pins = < 452 J722S_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ 453 J722S_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ 454 J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ 455 J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ 456 >; 457 bootph-all; 458 }; 459 460 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 461 pinctrl-single,pins = < 462 J722S_MCU_IOPAD(0x04c, PIN_INPUT_PULLUP, 0) /* (C7) WKUP_I2C0_SCL */ 463 J722S_MCU_IOPAD(0x050, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_I2C1_SDA */ 464 >; 465 bootph-all; 466 }; 467}; 468 469&wkup_uart0 { 470 /* WKUP UART0 is used by Device Manager firmware */ 471 pinctrl-names = "default"; 472 pinctrl-0 = <&wkup_uart0_pins_default>; 473 status = "reserved"; 474 bootph-all; 475}; 476 477&wkup_i2c0 { 478 pinctrl-names = "default"; 479 pinctrl-0 = <&wkup_i2c0_pins_default>; 480 clock-frequency = <400000>; 481 status = "okay"; 482 bootph-all; 483 484 tps65224: pmic@48 { 485 compatible = "ti,tps65224-q1"; 486 reg = <0x48>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pmic_irq_pins_default>; 489 interrupt-parent = <&main_gpio0>; 490 interrupts = <0 IRQ_TYPE_EDGE_FALLING>; 491 ti,primary-pmic; 492 493 gpio-controller; 494 #gpio-cells = <2>; 495 496 buck12-supply = <&vsys_io_3v3>; 497 buck3-supply = <&vsys_io_3v3>; 498 buck4-supply = <&vsys_io_3v3>; 499 500 ldo1-supply = <&vsys_io_3v3>; 501 ldo2-supply = <&vsys_io_3v3>; 502 ldo3-supply = <&vsys_io_3v3>; 503 504 regulators { 505 506 buck1: buck1 { 507 regulator-name = "vcc1v8_io_buck1"; 508 regulator-min-microvolt = <1800000>; 509 regulator-max-microvolt = <1800000>; 510 regulator-boot-on; 511 regulator-always-on; 512 bootph-all; 513 }; 514 515 buck2: buck2 { 516 regulator-name = "vcc1v1_ddr_buck2"; 517 regulator-min-microvolt = <1100000>; 518 regulator-max-microvolt = <1100000>; 519 regulator-boot-on; 520 regulator-always-on; 521 }; 522 523 buck3: buck3 { 524 regulator-name = "vcc0v85_ram_buck3"; 525 regulator-min-microvolt = <850000>; 526 regulator-max-microvolt = <850000>; 527 regulator-boot-on; 528 regulator-always-on; 529 }; 530 531 buck4: buck4 { 532 regulator-name = "vcc0v75_ioret_buck4"; 533 regulator-min-microvolt = <750000>; 534 regulator-max-microvolt = <750000>; 535 regulator-boot-on; 536 regulator-always-on; 537 }; 538 539 ldo1: ldo1 { 540 regulator-name = "vdda1v8_pll_ldo1"; 541 regulator-min-microvolt = <1800000>; 542 regulator-max-microvolt = <1800000>; 543 regulator-boot-on; 544 regulator-always-on; 545 }; 546 547 ldo2: ldo2 { 548 regulator-name = "dvdd3v3_ldo2"; 549 regulator-min-microvolt = <3300000>; 550 regulator-max-microvolt = <3300000>; 551 regulator-boot-on; 552 regulator-always-on; 553 }; 554 555 ldo3: ldo3 { 556 regulator-name = "vdd1v85_phy_ldo3"; 557 regulator-min-microvolt = <1800000>; 558 regulator-max-microvolt = <1800000>; 559 regulator-boot-on; 560 regulator-always-on; 561 }; 562 }; 563 }; 564}; 565 566&k3_clks { 567 /* Configure AUDIO_EXT_REFCLK1 pin as output */ 568 pinctrl-names = "default"; 569 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 570}; 571 572&main_i2c0 { 573 pinctrl-names = "default"; 574 pinctrl-0 = <&main_i2c0_pins_default>; 575 clock-frequency = <400000>; 576 status = "okay"; 577 bootph-all; 578 579 exp1: gpio@23 { 580 compatible = "ti,tca6424"; 581 reg = <0x23>; 582 gpio-controller; 583 #gpio-cells = <2>; 584 gpio-line-names = "TRC_MUX_SEL", "OSPI/ONAND_MUX_SEL", 585 "MCASP1_FET_SEL", "CTRL_PM_I2C_OE#", 586 "CSI_VIO_SEL", "USB2.0_MUX_SEL", 587 "CSI01_MUX_SEL_2", "CSI23_MUX_SEL_2", 588 "LMK1_OE1", "LMK1_OE0", 589 "LMK2_OE0", "LMK2_OE1", 590 "GPIO_RGMII1_RST#", "GPIO_AUD_RSTn", 591 "GPIO_eMMC_RSTn", "GPIO_uSD_PWR_EN", 592 "USER_LED2", "MCAN0_STB", 593 "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", 594 "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", 595 "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; 596 597 p05-hog { 598 /* P05 - USB2.0_MUX_SEL */ 599 gpio-hog; 600 gpios = <5 GPIO_ACTIVE_LOW>; 601 output-high; 602 }; 603 604 p01_hog: p01-hog { 605 /* P01 - TRC_MUX_SEL */ 606 gpio-hog; 607 gpios = <0 GPIO_ACTIVE_HIGH>; 608 output-low; 609 line-name = "TRC_MUX_SEL"; 610 }; 611 612 p02_hog: p02-hog { 613 /* P02 - MCASP1_FET_SEL */ 614 gpio-hog; 615 gpios = <2 GPIO_ACTIVE_HIGH>; 616 output-high; 617 line-name = "MCASP1_FET_SEL"; 618 }; 619 620 p13_hog: p13-hog { 621 /* P13 - GPIO_AUD_RSTn */ 622 gpio-hog; 623 gpios = <13 GPIO_ACTIVE_HIGH>; 624 output-high; 625 line-name = "GPIO_AUD_RSTn"; 626 }; 627 }; 628 629 tlv320aic3106: audio-codec@1b { 630 #sound-dai-cells = <0>; 631 compatible = "ti,tlv320aic3106"; 632 reg = <0x1b>; 633 ai3x-micbias-vg = <1>; /* 2.0V */ 634 AVDD-supply = <&vsys_io_3v3>; 635 IOVDD-supply = <&vsys_io_3v3>; 636 DRVDD-supply = <&vsys_io_3v3>; 637 DVDD-supply = <&vsys_io_1v8>; 638 }; 639}; 640 641&main_i2c2 { 642 status = "okay"; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&main_i2c2_pins_default>; 645 clock-frequency = <400000>; 646 647 pca9543_0: i2c-mux@70 { 648 compatible = "nxp,pca9543"; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 reg = <0x70>; 652 }; 653 654 pca9543_1: i2c-mux@71 { 655 compatible = "nxp,pca9543"; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 reg = <0x71>; 659 }; 660}; 661 662&ospi0 { 663 pinctrl-names = "default"; 664 pinctrl-0 = <&ospi0_pins_default>; 665 status = "okay"; 666 667 flash@0 { 668 compatible = "jedec,spi-nor"; 669 reg = <0x0>; 670 spi-tx-bus-width = <8>; 671 spi-rx-bus-width = <8>; 672 spi-max-frequency = <25000000>; 673 cdns,tshsl-ns = <60>; 674 cdns,tsd2d-ns = <60>; 675 cdns,tchsh-ns = <60>; 676 cdns,tslch-ns = <60>; 677 cdns,read-delay = <4>; 678 bootph-all; 679 680 partitions { 681 compatible = "fixed-partitions"; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 685 partition@0 { 686 label = "ospi.tiboot3"; 687 reg = <0x00 0x80000>; 688 }; 689 690 partition@80000 { 691 label = "ospi.tispl"; 692 reg = <0x80000 0x200000>; 693 }; 694 695 partition@280000 { 696 label = "ospi.u-boot"; 697 reg = <0x280000 0x400000>; 698 }; 699 700 partition@680000 { 701 label = "ospi.env"; 702 reg = <0x680000 0x40000>; 703 }; 704 705 partition@6c0000 { 706 label = "ospi.env.backup"; 707 reg = <0x6c0000 0x40000>; 708 }; 709 710 partition@800000 { 711 label = "ospi.rootfs"; 712 reg = <0x800000 0x37c0000>; 713 }; 714 715 partition@3fc0000 { 716 label = "ospi.phypattern"; 717 reg = <0x3fc0000 0x40000>; 718 }; 719 }; 720 }; 721 722}; 723 724&sdhci0 { 725 disable-wp; 726 bootph-all; 727 ti,driver-strength-ohm = <50>; 728 status = "okay"; 729}; 730 731&sdhci1 { 732 /* SD/MMC */ 733 vmmc-supply = <&vdd_mmc1>; 734 vqmmc-supply = <&vdd_sd_dv>; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&main_mmc1_pins_default>; 737 ti,driver-strength-ohm = <50>; 738 disable-wp; 739 status = "okay"; 740 bootph-all; 741}; 742 743&mailbox0_cluster0 { 744 status = "okay"; 745 746 mbox_wkup_r5_0: mbox-wkup-r5-0 { 747 ti,mbox-rx = <0 0 0>; 748 ti,mbox-tx = <1 0 0>; 749 }; 750}; 751 752&mailbox0_cluster1 { 753 status = "okay"; 754 755 mbox_mcu_r5_0: mbox-mcu-r5-0 { 756 ti,mbox-rx = <0 0 0>; 757 ti,mbox-tx = <1 0 0>; 758 }; 759}; 760 761&mailbox0_cluster2 { 762 status = "okay"; 763 764 mbox_c7x_0: mbox-c7x-0 { 765 ti,mbox-rx = <0 0 0>; 766 ti,mbox-tx = <1 0 0>; 767 }; 768}; 769 770&mailbox0_cluster3 { 771 status = "okay"; 772 773 mbox_main_r5_0: mbox-main-r5-0 { 774 ti,mbox-rx = <0 0 0>; 775 ti,mbox-tx = <1 0 0>; 776 }; 777 778 mbox_c7x_1: mbox-c7x-1 { 779 ti,mbox-rx = <2 0 0>; 780 ti,mbox-tx = <3 0 0>; 781 }; 782}; 783 784/* Timers are used by Remoteproc firmware */ 785&main_timer0 { 786 status = "reserved"; 787}; 788 789&main_timer1 { 790 status = "reserved"; 791}; 792 793&main_timer2 { 794 status = "reserved"; 795}; 796 797&wkup_r5fss0 { 798 status = "okay"; 799}; 800 801&wkup_r5fss0_core0 { 802 mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; 803 memory-region = <&wkup_r5fss0_core0_dma_memory_region>, 804 <&wkup_r5fss0_core0_memory_region>; 805}; 806 807&mcu_r5fss0 { 808 status = "okay"; 809}; 810 811&mcu_r5fss0_core0 { 812 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; 813 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 814 <&mcu_r5fss0_core0_memory_region>; 815}; 816 817&main_r5fss0 { 818 status = "okay"; 819}; 820 821&main_r5fss0_core0 { 822 mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; 823 memory-region = <&main_r5fss0_core0_dma_memory_region>, 824 <&main_r5fss0_core0_memory_region>; 825}; 826 827&c7x_0 { 828 mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; 829 memory-region = <&c7x_0_dma_memory_region>, 830 <&c7x_0_memory_region>; 831 status = "okay"; 832}; 833 834&c7x_1 { 835 mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; 836 memory-region = <&c7x_1_dma_memory_region>, 837 <&c7x_1_memory_region>; 838 status = "okay"; 839}; 840 841&serdes_ln_ctrl { 842 idle-states = <J722S_SERDES0_LANE0_USB>, 843 <J722S_SERDES1_LANE0_PCIE0_LANE0>; 844}; 845 846&serdes0 { 847 status = "okay"; 848 serdes0_usb_link: phy@0 { 849 reg = <0>; 850 cdns,num-lanes = <1>; 851 #phy-cells = <0>; 852 cdns,phy-type = <PHY_TYPE_USB3>; 853 resets = <&serdes_wiz0 1>; 854 }; 855}; 856 857&serdes1 { 858 status = "okay"; 859 serdes1_pcie_link: phy@0 { 860 reg = <0>; 861 cdns,num-lanes = <1>; 862 #phy-cells = <0>; 863 cdns,phy-type = <PHY_TYPE_PCIE>; 864 resets = <&serdes_wiz1 1>; 865 }; 866}; 867 868&pcie0_rc { 869 reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; 870 phys = <&serdes1_pcie_link>; 871 phy-names = "pcie-phy"; 872 status = "okay"; 873}; 874 875&usbss0 { 876 ti,vbus-divider; 877 status = "okay"; 878}; 879 880&usb0 { 881 dr_mode = "otg"; 882 usb-role-switch; 883}; 884 885&usbss1 { 886 pinctrl-names = "default"; 887 pinctrl-0 = <&main_usb1_pins_default>; 888 ti,vbus-divider; 889 status = "okay"; 890}; 891 892&usb1 { 893 dr_mode = "host"; 894 maximum-speed = "super-speed"; 895 phys = <&serdes0_usb_link>; 896 phy-names = "cdns3,usb3-phy"; 897}; 898 899&mcasp1 { 900 status = "okay"; 901 #sound-dai-cells = <0>; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&main_mcasp1_pins_default>; 904 op-mode = <0>; /* MCASP_IIS_MODE */ 905 tdm-slots = <2>; 906 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 907 1 0 2 0 908 0 0 0 0 909 0 0 0 0 910 0 0 0 0 911 >; 912}; 913 914&mcu_mcan0 { 915 pinctrl-names = "default"; 916 pinctrl-0 = <&mcu_mcan0_pins_default>; 917 phys = <&transceiver0>; 918 status = "okay"; 919}; 920 921&mcu_mcan1 { 922 pinctrl-names = "default"; 923 pinctrl-0 = <&mcu_mcan1_pins_default>; 924 phys = <&transceiver1>; 925 status = "okay"; 926}; 927 928&main_mcan0 { 929 pinctrl-names = "default"; 930 pinctrl-0 = <&main_mcan0_pins_default>; 931 phys = <&transceiver2>; 932 status = "okay"; 933}; 934 935&mcu_gpio0 { 936 status = "okay"; 937}; 938 939&mcu_i2c0 { 940 pinctrl-names = "default"; 941 pinctrl-0 = <&mcu_i2c0_pins_default>; 942 clock-frequency = <400000>; 943 status = "okay"; 944}; 945