1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include "rk3588.dtsi" 10 11/ { 12 compatible = "tsd,rk3588-tiger", "rockchip,rk3588"; 13 14 aliases { 15 i2c10 = &i2c10; 16 mmc0 = &sdhci; 17 rtc0 = &rtc_twi; 18 }; 19 20 emmc_pwrseq: emmc-pwrseq { 21 compatible = "mmc-pwrseq-emmc"; 22 pinctrl-0 = <&emmc_reset>; 23 pinctrl-names = "default"; 24 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; 25 }; 26 27 extcon_usb3: extcon-usb3 { 28 compatible = "linux,extcon-usb-gpio"; 29 id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&usb3_id>; 32 status = "disabled"; 33 }; 34 35 leds { 36 compatible = "gpio-leds"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&module_led_pin>; 39 40 /* Named LED1 on the board */ 41 led-1 { 42 gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 43 function = LED_FUNCTION_HEARTBEAT; 44 linux,default-trigger = "heartbeat"; 45 color = <LED_COLOR_ID_AMBER>; 46 }; 47 }; 48 49 /* 50 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE 51 * clock generator. 52 * The clock output is gated via the OE pin on the clock generator. 53 * This is modeled as a fixed-clock plus a gpio-gate-clock. 54 */ 55 pcie_refclk_gen: pcie-refclk-gen-clock { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <100000000>; 59 }; 60 61 pcie_refclk: pcie-refclk-clock { 62 compatible = "gpio-gate-clock"; 63 clocks = <&pcie_refclk_gen>; 64 #clock-cells = <0>; 65 enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ 66 }; 67 68 vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { 69 compatible = "regulator-fixed"; 70 regulator-name = "vcc_1v1_nldo_s3"; 71 regulator-always-on; 72 regulator-boot-on; 73 regulator-min-microvolt = <1100000>; 74 regulator-max-microvolt = <1100000>; 75 vin-supply = <&vcc5v0_sys>; 76 }; 77 78 vcc_1v2_s3: regulator-vcc-1v2-s3 { 79 compatible = "regulator-fixed"; 80 regulator-name = "vcc_1v2_s3"; 81 regulator-always-on; 82 regulator-boot-on; 83 regulator-min-microvolt = <1200000>; 84 regulator-max-microvolt = <1200000>; 85 vin-supply = <&vcc5v0_sys>; 86 }; 87 88 vcc5v0_sys: regulator-vcc5v0-sys { 89 compatible = "regulator-fixed"; 90 regulator-name = "vcc5v0_sys"; 91 regulator-always-on; 92 regulator-boot-on; 93 regulator-min-microvolt = <5000000>; 94 regulator-max-microvolt = <5000000>; 95 vin-supply = <&vcc5v0_baseboard>; 96 }; 97}; 98 99&cpu_b0 { 100 cpu-supply = <&vdd_cpu_big0_s0>; 101}; 102 103&cpu_b1 { 104 cpu-supply = <&vdd_cpu_big0_s0>; 105}; 106 107&cpu_b2 { 108 cpu-supply = <&vdd_cpu_big1_s0>; 109}; 110 111&cpu_b3 { 112 cpu-supply = <&vdd_cpu_big1_s0>; 113}; 114 115&cpu_l0 { 116 cpu-supply = <&vdd_cpu_lit_s0>; 117}; 118 119&cpu_l1 { 120 cpu-supply = <&vdd_cpu_lit_s0>; 121}; 122 123&cpu_l2 { 124 cpu-supply = <&vdd_cpu_lit_s0>; 125}; 126 127&cpu_l3 { 128 cpu-supply = <&vdd_cpu_lit_s0>; 129}; 130 131&gmac0 { 132 clock_in_out = "output"; 133 phy-handle = <&rgmii_phy>; 134 phy-mode = "rgmii"; 135 phy-supply = <&vcc_1v2_s3>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&gmac0_miim 138 &gmac0_rx_bus2 139 &gmac0_tx_bus2 140 &gmac0_rgmii_clk 141 &gmac0_rgmii_bus 142 ð0_pins 143 ð_reset>; 144 tx_delay = <0x10>; 145 rx_delay = <0x10>; 146 snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; 147 snps,reset-active-low; 148 snps,reset-delays-us = <0 10000 100000>; 149}; 150 151&gpu { 152 mali-supply = <&vdd_gpu_s0>; 153 status = "okay"; 154}; 155 156&hdmi0 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&hdmim1_tx0_cec &hdmim0_tx0_hpd &hdmim1_tx0_scl 159 &hdmim1_tx0_sda>; 160}; 161 162&i2c1 { 163 pinctrl-0 = <&i2c1m0_xfer>; 164}; 165 166&i2c1m0_xfer { 167 rockchip,pins = 168 /* i2c1_scl_m0 */ 169 <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>, 170 /* i2c1_sda_m0 */ 171 <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>; 172}; 173 174&i2c2 { 175 pinctrl-0 = <&i2c2m3_xfer>; 176}; 177 178&i2c2m3_xfer { 179 rockchip,pins = 180 /* i2c2_scl_m3 */ 181 <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>, 182 /* i2c2_sda_m3 */ 183 <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>; 184}; 185 186&i2c3 { 187 pinctrl-0 = <&i2c3m0_xfer>; 188}; 189 190&i2c4 { 191 pinctrl-0 = <&i2c4m4_xfer>; 192 status = "okay"; 193 194 vdd_npu_s0: regulator@42 { 195 compatible = "rockchip,rk8602"; 196 reg = <0x42>; 197 fcs,suspend-voltage-selector = <1>; 198 regulator-name = "vdd_npu_s0"; 199 regulator-always-on; 200 regulator-boot-on; 201 regulator-min-microvolt = <550000>; 202 regulator-max-microvolt = <950000>; 203 regulator-ramp-delay = <2300>; 204 vin-supply = <&vcc5v0_sys>; 205 206 regulator-state-mem { 207 regulator-off-in-suspend; 208 }; 209 }; 210}; 211 212&i2c5 { 213 pinctrl-0 = <&i2c5m1_xfer>; 214}; 215 216&i2c5m1_xfer { 217 rockchip,pins = 218 /* i2c5_scl_m1 */ 219 <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>, 220 /* i2c5_sda_m1 */ 221 <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>; 222}; 223 224&i2c6 { 225 /* 226 * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus, 227 * but SOC can handle only up to (400kHz). 228 */ 229 clock-frequency = <400000>; 230 status = "okay"; 231 232 fan@18 { 233 compatible = "tsd,mule", "ti,amc6821"; 234 reg = <0x18>; 235 236 i2c-mux { 237 compatible = "tsd,mule-i2c-mux"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 i2c10: i2c@0 { 242 reg = <0x0>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 rtc_twi: rtc@6f { 247 compatible = "isil,isl1208"; 248 reg = <0x6f>; 249 }; 250 }; 251 }; 252 }; 253}; 254 255&i2c6m0_xfer { 256 rockchip,pins = 257 /* i2c6_scl_m0 */ 258 <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 259 /* i2c6_sda_m0 */ 260 <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>; 261}; 262 263&i2c7 { 264 status = "okay"; 265 266 vdd_cpu_big0_s0: regulator@42 { 267 compatible = "rockchip,rk8602"; 268 reg = <0x42>; 269 fcs,suspend-voltage-selector = <1>; 270 regulator-name = "vdd_cpu_big0_s0"; 271 regulator-always-on; 272 regulator-boot-on; 273 regulator-min-microvolt = <550000>; 274 regulator-max-microvolt = <1050000>; 275 regulator-ramp-delay = <2300>; 276 vin-supply = <&vcc5v0_sys>; 277 278 regulator-state-mem { 279 regulator-off-in-suspend; 280 }; 281 }; 282 283 vdd_cpu_big1_s0: regulator@43 { 284 compatible = "rockchip,rk8603", "rockchip,rk8602"; 285 reg = <0x43>; 286 fcs,suspend-voltage-selector = <1>; 287 regulator-name = "vdd_cpu_big1_s0"; 288 regulator-always-on; 289 regulator-boot-on; 290 regulator-min-microvolt = <550000>; 291 regulator-max-microvolt = <1050000>; 292 regulator-ramp-delay = <2300>; 293 vin-supply = <&vcc5v0_sys>; 294 295 regulator-state-mem { 296 regulator-off-in-suspend; 297 }; 298 }; 299}; 300 301&i2c7m0_xfer { 302 rockchip,pins = 303 /* i2c7_scl_m0 */ 304 <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 305 /* i2c7_sda_m0 */ 306 <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>; 307}; 308 309&i2c8 { 310 pinctrl-0 = <&i2c8m2_xfer>; 311}; 312 313&mdio0 { 314 rgmii_phy: ethernet-phy@6 { 315 /* KSZ9031 or KSZ9131 */ 316 compatible = "ethernet-phy-ieee802.3-c22"; 317 reg = <0x6>; 318 clocks = <&cru REFCLKO25M_ETH0_OUT>; 319 }; 320}; 321 322&pcie3x4 { 323 /* 324 * The board has a gpio-controlled "pcie_refclk" generator, 325 * so add it to the list of clocks. 326 */ 327 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 328 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 329 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, 330 <&pcie_refclk>; 331 clock-names = "aclk_mst", "aclk_slv", 332 "aclk_dbi", "pclk", 333 "aux", "pipe", 334 "ref"; 335 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; 336}; 337 338&pd_gpu { 339 domain-supply = <&vdd_gpu_s0>; 340}; 341 342&pinctrl { 343 emmc { 344 emmc_reset: emmc-reset { 345 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 346 }; 347 }; 348 349 ethernet { 350 eth_reset: eth-reset { 351 rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 352 }; 353 }; 354 355 leds { 356 module_led_pin: module-led-pin { 357 rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 358 }; 359 }; 360 361 usb3 { 362 usb3_id: usb3-id { 363 rockchip,pins = 364 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 365 }; 366 }; 367}; 368 369&pwm0 { 370 pinctrl-0 = <&pwm0m1_pins>; 371 pinctrl-names = "default"; 372}; 373 374&saradc { 375 vref-supply = <&vcc_1v8_s0>; 376 status = "okay"; 377}; 378 379&sdhci { 380 bus-width = <8>; 381 cap-mmc-highspeed; 382 mmc-ddr-1_8v; 383 mmc-hs200-1_8v; 384 mmc-hs400-1_8v; 385 mmc-hs400-enhanced-strobe; 386 mmc-pwrseq = <&emmc_pwrseq>; 387 no-sdio; 388 no-sd; 389 non-removable; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; 392 vmmc-supply = <&vcc_3v3_s3>; 393 vqmmc-supply = <&vcc_1v8_s3>; 394 status = "okay"; 395}; 396 397&sdmmc { 398 bus-width = <4>; 399 cap-sd-highspeed; 400 max-frequency = <150000000>; 401 vqmmc-supply = <&vccio_sd_s0>; 402}; 403 404&spi0 { 405 pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; 406}; 407 408&spi2 { 409 assigned-clocks = <&cru CLK_SPI2>; 410 assigned-clock-rates = <200000000>; 411 num-cs = <1>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 414 status = "okay"; 415 416 pmic@0 { 417 compatible = "rockchip,rk806"; 418 reg = <0x0>; 419 interrupt-parent = <&gpio0>; 420 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 425 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 426 spi-max-frequency = <1000000>; 427 system-power-controller; 428 vcc1-supply = <&vcc5v0_sys>; 429 vcc2-supply = <&vcc5v0_sys>; 430 vcc3-supply = <&vcc5v0_sys>; 431 vcc4-supply = <&vcc5v0_sys>; 432 vcc5-supply = <&vcc5v0_sys>; 433 vcc6-supply = <&vcc5v0_sys>; 434 vcc7-supply = <&vcc5v0_sys>; 435 vcc8-supply = <&vcc5v0_sys>; 436 vcc9-supply = <&vcc5v0_sys>; 437 vcc10-supply = <&vcc5v0_sys>; 438 vcc11-supply = <&vcc_2v0_pldo_s3>; 439 vcc12-supply = <&vcc5v0_sys>; 440 vcc13-supply = <&vcc_1v1_nldo_s3>; 441 vcc14-supply = <&vcc_1v1_nldo_s3>; 442 vcca-supply = <&vcc5v0_sys>; 443 444 rk806_dvs1_null: dvs1-null-pins { 445 pins = "gpio_pwrctrl1"; 446 function = "pin_fun0"; 447 }; 448 449 rk806_dvs2_null: dvs2-null-pins { 450 pins = "gpio_pwrctrl2"; 451 function = "pin_fun0"; 452 }; 453 454 rk806_dvs3_null: dvs3-null-pins { 455 pins = "gpio_pwrctrl3"; 456 function = "pin_fun0"; 457 }; 458 459 regulators { 460 vdd_gpu_s0: dcdc-reg1 { 461 regulator-boot-on; 462 regulator-min-microvolt = <550000>; 463 regulator-max-microvolt = <950000>; 464 regulator-ramp-delay = <12500>; 465 regulator-name = "vdd_gpu_s0"; 466 regulator-enable-ramp-delay = <400>; 467 468 regulator-state-mem { 469 regulator-off-in-suspend; 470 }; 471 }; 472 473 vdd_cpu_lit_s0: dcdc-reg2 { 474 regulator-name = "vdd_cpu_lit_s0"; 475 regulator-always-on; 476 regulator-boot-on; 477 regulator-min-microvolt = <550000>; 478 regulator-max-microvolt = <950000>; 479 regulator-ramp-delay = <12500>; 480 481 regulator-state-mem { 482 regulator-off-in-suspend; 483 }; 484 }; 485 486 vdd_log_s0: dcdc-reg3 { 487 regulator-name = "vdd_log_s0"; 488 regulator-always-on; 489 regulator-boot-on; 490 regulator-min-microvolt = <675000>; 491 regulator-max-microvolt = <750000>; 492 regulator-ramp-delay = <12500>; 493 494 regulator-state-mem { 495 regulator-off-in-suspend; 496 regulator-suspend-microvolt = <750000>; 497 }; 498 }; 499 500 vdd_vdenc_s0: dcdc-reg4 { 501 regulator-name = "vdd_vdenc_s0"; 502 regulator-always-on; 503 regulator-boot-on; 504 regulator-min-microvolt = <550000>; 505 regulator-max-microvolt = <950000>; 506 regulator-ramp-delay = <12500>; 507 508 regulator-state-mem { 509 regulator-off-in-suspend; 510 }; 511 }; 512 513 vdd_ddr_s0: dcdc-reg5 { 514 regulator-name = "vdd_ddr_s0"; 515 regulator-always-on; 516 regulator-boot-on; 517 regulator-min-microvolt = <675000>; 518 regulator-max-microvolt = <900000>; 519 regulator-ramp-delay = <12500>; 520 521 regulator-state-mem { 522 regulator-off-in-suspend; 523 regulator-suspend-microvolt = <850000>; 524 }; 525 }; 526 527 vdd2_ddr_s3: dcdc-reg6 { 528 regulator-name = "vdd2_ddr_s3"; 529 regulator-always-on; 530 regulator-boot-on; 531 532 regulator-state-mem { 533 regulator-on-in-suspend; 534 }; 535 }; 536 537 vcc_2v0_pldo_s3: dcdc-reg7 { 538 regulator-name = "vcc_2v0_pldo_s3"; 539 regulator-always-on; 540 regulator-boot-on; 541 regulator-min-microvolt = <2000000>; 542 regulator-max-microvolt = <2000000>; 543 regulator-ramp-delay = <12500>; 544 545 regulator-state-mem { 546 regulator-on-in-suspend; 547 regulator-suspend-microvolt = <2000000>; 548 }; 549 }; 550 551 vcc_3v3_s3: dcdc-reg8 { 552 regulator-name = "vcc_3v3_s3"; 553 regulator-always-on; 554 regulator-boot-on; 555 regulator-min-microvolt = <3300000>; 556 regulator-max-microvolt = <3300000>; 557 558 regulator-state-mem { 559 regulator-on-in-suspend; 560 regulator-suspend-microvolt = <3300000>; 561 }; 562 }; 563 564 vddq_ddr_s0: dcdc-reg9 { 565 regulator-name = "vddq_ddr_s0"; 566 regulator-always-on; 567 regulator-boot-on; 568 569 regulator-state-mem { 570 regulator-off-in-suspend; 571 }; 572 }; 573 574 vcc_1v8_s3: dcdc-reg10 { 575 regulator-name = "vcc_1v8_s3"; 576 regulator-always-on; 577 regulator-boot-on; 578 regulator-min-microvolt = <1800000>; 579 regulator-max-microvolt = <1800000>; 580 581 regulator-state-mem { 582 regulator-on-in-suspend; 583 regulator-suspend-microvolt = <1800000>; 584 }; 585 }; 586 587 vcca_1v8_s0: pldo-reg1 { 588 regulator-name = "vcca_1v8_s0"; 589 regulator-always-on; 590 regulator-boot-on; 591 regulator-min-microvolt = <1800000>; 592 regulator-max-microvolt = <1800000>; 593 594 regulator-state-mem { 595 regulator-off-in-suspend; 596 }; 597 }; 598 599 vcc_1v8_s0: pldo-reg2 { 600 regulator-name = "vcc_1v8_s0"; 601 regulator-always-on; 602 regulator-boot-on; 603 regulator-min-microvolt = <1800000>; 604 regulator-max-microvolt = <1800000>; 605 606 regulator-state-mem { 607 regulator-off-in-suspend; 608 regulator-suspend-microvolt = <1800000>; 609 }; 610 }; 611 612 vdda_1v2_s0: pldo-reg3 { 613 regulator-name = "vdda_1v2_s0"; 614 regulator-always-on; 615 regulator-boot-on; 616 regulator-min-microvolt = <1200000>; 617 regulator-max-microvolt = <1200000>; 618 619 regulator-state-mem { 620 regulator-off-in-suspend; 621 }; 622 }; 623 624 vcca_3v3_s0: pldo-reg4 { 625 regulator-name = "vcca_3v3_s0"; 626 regulator-always-on; 627 regulator-boot-on; 628 regulator-min-microvolt = <3300000>; 629 regulator-max-microvolt = <3300000>; 630 regulator-ramp-delay = <12500>; 631 632 regulator-state-mem { 633 regulator-off-in-suspend; 634 }; 635 }; 636 637 vccio_sd_s0: pldo-reg5 { 638 regulator-name = "vccio_sd_s0"; 639 regulator-always-on; 640 regulator-boot-on; 641 regulator-min-microvolt = <1800000>; 642 regulator-max-microvolt = <3300000>; 643 regulator-ramp-delay = <12500>; 644 645 regulator-state-mem { 646 regulator-off-in-suspend; 647 }; 648 }; 649 650 pldo6_s3: pldo-reg6 { 651 regulator-name = "pldo6_s3"; 652 regulator-always-on; 653 regulator-boot-on; 654 regulator-min-microvolt = <1800000>; 655 regulator-max-microvolt = <1800000>; 656 657 regulator-state-mem { 658 regulator-on-in-suspend; 659 regulator-suspend-microvolt = <1800000>; 660 }; 661 }; 662 663 vdd_0v75_s3: nldo-reg1 { 664 regulator-name = "vdd_0v75_s3"; 665 regulator-always-on; 666 regulator-boot-on; 667 regulator-min-microvolt = <750000>; 668 regulator-max-microvolt = <750000>; 669 670 regulator-state-mem { 671 regulator-on-in-suspend; 672 regulator-suspend-microvolt = <750000>; 673 }; 674 }; 675 676 vdda_ddr_pll_s0: nldo-reg2 { 677 regulator-name = "vdda_ddr_pll_s0"; 678 regulator-always-on; 679 regulator-boot-on; 680 regulator-min-microvolt = <850000>; 681 regulator-max-microvolt = <850000>; 682 683 regulator-state-mem { 684 regulator-off-in-suspend; 685 regulator-suspend-microvolt = <850000>; 686 }; 687 }; 688 689 vdda_0v75_s0: nldo-reg3 { 690 regulator-name = "vdda_0v75_s0"; 691 regulator-always-on; 692 regulator-boot-on; 693 regulator-min-microvolt = <750000>; 694 regulator-max-microvolt = <750000>; 695 696 regulator-state-mem { 697 regulator-off-in-suspend; 698 }; 699 }; 700 701 vdda_0v85_s0: nldo-reg4 { 702 regulator-name = "vdda_0v85_s0"; 703 regulator-always-on; 704 regulator-boot-on; 705 regulator-min-microvolt = <850000>; 706 regulator-max-microvolt = <850000>; 707 708 regulator-state-mem { 709 regulator-off-in-suspend; 710 }; 711 }; 712 713 vdd_0v75_s0: nldo-reg5 { 714 regulator-name = "vdd_0v75_s0"; 715 regulator-always-on; 716 regulator-boot-on; 717 regulator-min-microvolt = <750000>; 718 regulator-max-microvolt = <750000>; 719 720 regulator-state-mem { 721 regulator-off-in-suspend; 722 }; 723 }; 724 }; 725 }; 726}; 727 728&tsadc { 729 status = "okay"; 730}; 731 732/* Routed to UART0 on the Q7 connector */ 733&uart2 { 734 pinctrl-0 = <&uart2m2_xfer>; 735}; 736 737/* Mule-ATtiny UPDI */ 738&uart4 { 739 pinctrl-0 = <&uart4m2_xfer>; 740 status = "okay"; 741}; 742