1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 MNT Research GmbH
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/pinctrl/rockchip.h>
12#include <dt-bindings/soc/rockchip,vop2.h>
13#include <dt-bindings/usb/pd.h>
14
15#include "rk3588-firefly-icore-3588q.dtsi"
16
17/ {
18	model = "MNT Reform 2 with RCORE RK3588 Module";
19	compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588";
20	chassis-type = "laptop";
21
22	aliases {
23		ethernet0 = &gmac0;
24		mmc1 = &sdmmc;
25	};
26
27	chosen {
28		stdout-path = "serial2:1500000n8";
29	};
30
31	backlight: backlight {
32		compatible = "pwm-backlight";
33		brightness-levels = <0 8 16 32 64 128 160 200 255>;
34		default-brightness-level = <128>;
35		enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
36		pwms = <&pwm8 0 10000 0>;
37	};
38
39	gmac0_clkin: external-gmac0-clock {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <125000000>;
43		clock-output-names = "gmac0_clkin";
44	};
45
46	pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
47		compatible = "regulator-fixed";
48		regulator-boot-on;
49		regulator-always-on;
50		regulator-min-microvolt = <1800000>;
51		regulator-max-microvolt = <1800000>;
52		regulator-name = "pcie30_avdd1v8";
53		vin-supply = <&avcc_1v8_s0>;
54	};
55
56	pcie30_avdd0v75: regulator-pcie30-avdd0v75 {
57		compatible = "regulator-fixed";
58		regulator-always-on;
59		regulator-boot-on;
60		regulator-min-microvolt = <750000>;
61		regulator-max-microvolt = <750000>;
62		regulator-name = "pcie30_avdd0v75";
63		vin-supply = <&avdd_0v75_s0>;
64	};
65
66	vcc12v_dcin: regulator-vcc12v-dcin {
67		compatible = "regulator-fixed";
68		regulator-always-on;
69		regulator-boot-on;
70		regulator-min-microvolt = <12000000>;
71		regulator-max-microvolt = <12000000>;
72		regulator-name = "vcc12v_dcin";
73	};
74
75	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
76		compatible = "regulator-fixed";
77		regulator-name = "vcc_1v1_nldo_s3";
78		regulator-always-on;
79		regulator-boot-on;
80		regulator-min-microvolt = <1100000>;
81		regulator-max-microvolt = <1100000>;
82		vin-supply = <&vcc5v0_sys>;
83	};
84
85	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
86		compatible = "regulator-fixed";
87		regulator-always-on;
88		regulator-boot-on;
89		regulator-min-microvolt = <3300000>;
90		regulator-max-microvolt = <3300000>;
91		regulator-name = "vcc3v3_pcie30";
92		vin-supply = <&vcc12v_dcin>;
93	};
94
95	vcc5v0_host: regulator-vcc5v0-host {
96		compatible = "regulator-fixed";
97		regulator-always-on;
98		regulator-boot-on;
99		regulator-min-microvolt = <5000000>;
100		regulator-max-microvolt = <5000000>;
101		regulator-name = "vcc5v0_host";
102	};
103
104	vcc5v0_sys: regulator-vcc5v0-sys {
105		compatible = "regulator-fixed";
106		regulator-always-on;
107		regulator-boot-on;
108		regulator-min-microvolt = <5000000>;
109		regulator-max-microvolt = <5000000>;
110		regulator-name = "vcc5v0_sys";
111		vin-supply = <&vcc12v_dcin>;
112	};
113
114	vcc5v0_usb: regulator-vcc5v0-usb {
115		compatible = "regulator-fixed";
116		regulator-always-on;
117		regulator-boot-on;
118		regulator-min-microvolt = <5000000>;
119		regulator-max-microvolt = <5000000>;
120		regulator-name = "vcc5v0_usb";
121		vin-supply = <&vcc12v_dcin>;
122	};
123};
124
125&combphy0_ps {
126	status = "okay";
127};
128
129&gmac0 {
130	clock_in_out = "output";
131	phy-handle = <&rgmii_phy>;
132	phy-mode = "rgmii-id";
133	pinctrl-names = "default";
134	pinctrl-0 = <&gmac0_miim
135		     &gmac0_tx_bus2
136		     &gmac0_rx_bus2
137		     &gmac0_rgmii_clk
138		     &gmac0_rgmii_bus
139		     &gmac0_clkinout
140		     &eth_phy_reset>;
141	status = "okay";
142};
143
144&gpu {
145	mali-supply = <&vdd_gpu_s0>;
146	sram-supply = <&vdd_gpu_mem_s0>;
147	status = "okay";
148};
149
150&hdmi0 {
151	status = "okay";
152};
153
154&hdmi0_in {
155	hdmi0_in_vp2: endpoint {
156		remote-endpoint = <&vp2_out_hdmi0>;
157	};
158};
159
160&hdptxphy0 {
161	status = "okay";
162};
163
164&i2c6 {
165	pinctrl-names = "default";
166	pinctrl-0 = <&i2c6m0_xfer>;
167	status = "okay";
168
169	rtc@68 {
170		compatible = "nxp,pcf8523";
171		reg = <0x68>;
172	};
173};
174
175&mdio0 {
176	rgmii_phy: ethernet-phy@0 {
177		compatible = "ethernet-phy-ieee802.3-c22";
178		reg = <0x0>;
179	};
180};
181
182&pcie2x1l2 {
183	pinctrl-0 = <&pcie2_0_rst>;
184	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
185	status = "okay";
186};
187
188&pcie30phy {
189	status = "okay";
190};
191
192&pcie3x4 {
193	num-lanes = <1>;
194	pinctrl-names = "default";
195	pinctrl-0 = <&pcie3_reset>;
196	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
197	vpcie3v3-supply = <&vcc3v3_pcie30>;
198	status = "okay";
199};
200
201&pinctrl {
202	dp {
203		dp1_hpd: dp1-hpd {
204			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
205		};
206	};
207
208	pcie2 {
209		pcie2_0_rst: pcie2-0-rst {
210			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
211		};
212	};
213
214	pcie3 {
215		pcie3_reset: pcie3-reset {
216			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
217		};
218	};
219
220	eth_phy {
221		eth_phy_reset: eth-phy-reset {
222			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
223		};
224	};
225};
226
227&pwm8 {
228	pinctrl-0 = <&pwm8m2_pins>;
229	status = "okay";
230};
231
232&saradc {
233	vref-supply = <&avcc_1v8_s0>;
234	status = "okay";
235};
236
237&sdmmc {
238	bus-width = <4>;
239	cap-sd-highspeed;
240	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
241	disable-wp;
242	max-frequency = <40000000>;
243	no-1-8-v;
244	no-mmc;
245	no-sdio;
246	vmmc-supply = <&vcc3v3_pcie30>;
247	vqmmc-supply = <&vcc3v3_pcie30>;
248	status = "okay";
249};
250
251&tsadc {
252	status = "okay";
253};
254
255&u2phy0 {
256	status = "okay";
257};
258
259&u2phy0_otg {
260	status = "okay";
261};
262
263&u2phy1 {
264	status = "okay";
265};
266
267&u2phy1_otg {
268	status = "okay";
269};
270
271&u2phy2 {
272	status = "okay";
273};
274
275&u2phy2_host {
276	phy-supply = <&vcc5v0_host>;
277	status = "okay";
278};
279
280&u2phy3 {
281	status = "okay";
282};
283
284&u2phy3_host {
285	phy-supply = <&vcc5v0_host>;
286	status = "okay";
287};
288
289&usbdp_phy0 {
290	status = "okay";
291};
292
293&usbdp_phy1 {
294	status = "okay";
295};
296
297&usb_host0_ehci {
298	status = "okay";
299};
300
301&usb_host0_ohci {
302	status = "okay";
303};
304
305&usb_host0_xhci {
306	dr_mode = "host";
307	status = "okay";
308};
309
310&usb_host1_ehci {
311	status = "okay";
312};
313
314&usb_host1_ohci {
315	status = "okay";
316};
317
318&usb_host1_xhci {
319	dr_mode = "host";
320	status = "okay";
321};
322
323&vop {
324	status = "okay";
325};
326
327&vop_mmu {
328	status = "okay";
329};
330
331&vp2 {
332	vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
333		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
334		remote-endpoint = <&hdmi0_in_vp2>;
335	};
336};
337