1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/power/rk3588-power.h> 10#include <dt-bindings/reset/rockchip,rk3588-cru.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/ata/ahci.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3588"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 gpio4 = &gpio4; 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 i2c6 = &i2c6; 35 i2c7 = &i2c7; 36 i2c8 = &i2c8; 37 serial0 = &uart0; 38 serial1 = &uart1; 39 serial2 = &uart2; 40 serial3 = &uart3; 41 serial4 = &uart4; 42 serial5 = &uart5; 43 serial6 = &uart6; 44 serial7 = &uart7; 45 serial8 = &uart8; 46 serial9 = &uart9; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu_l0>; 62 }; 63 core1 { 64 cpu = <&cpu_l1>; 65 }; 66 core2 { 67 cpu = <&cpu_l2>; 68 }; 69 core3 { 70 cpu = <&cpu_l3>; 71 }; 72 }; 73 cluster1 { 74 core0 { 75 cpu = <&cpu_b0>; 76 }; 77 core1 { 78 cpu = <&cpu_b1>; 79 }; 80 }; 81 cluster2 { 82 core0 { 83 cpu = <&cpu_b2>; 84 }; 85 core1 { 86 cpu = <&cpu_b3>; 87 }; 88 }; 89 }; 90 91 cpu_l0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <530>; 97 clocks = <&scmi_clk SCMI_CLK_CPUL>; 98 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; 99 assigned-clock-rates = <816000000>; 100 cpu-idle-states = <&CPU_SLEEP>; 101 i-cache-size = <32768>; 102 i-cache-line-size = <64>; 103 i-cache-sets = <128>; 104 d-cache-size = <32768>; 105 d-cache-line-size = <64>; 106 d-cache-sets = <128>; 107 next-level-cache = <&l2_cache_l0>; 108 dynamic-power-coefficient = <228>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu_l1: cpu@100 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x100>; 116 enable-method = "psci"; 117 capacity-dmips-mhz = <530>; 118 clocks = <&scmi_clk SCMI_CLK_CPUL>; 119 cpu-idle-states = <&CPU_SLEEP>; 120 i-cache-size = <32768>; 121 i-cache-line-size = <64>; 122 i-cache-sets = <128>; 123 d-cache-size = <32768>; 124 d-cache-line-size = <64>; 125 d-cache-sets = <128>; 126 next-level-cache = <&l2_cache_l1>; 127 dynamic-power-coefficient = <228>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu_l2: cpu@200 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x200>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <530>; 137 clocks = <&scmi_clk SCMI_CLK_CPUL>; 138 cpu-idle-states = <&CPU_SLEEP>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l2>; 146 dynamic-power-coefficient = <228>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu_l3: cpu@300 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a55"; 153 reg = <0x300>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <530>; 156 clocks = <&scmi_clk SCMI_CLK_CPUL>; 157 cpu-idle-states = <&CPU_SLEEP>; 158 i-cache-size = <32768>; 159 i-cache-line-size = <64>; 160 i-cache-sets = <128>; 161 d-cache-size = <32768>; 162 d-cache-line-size = <64>; 163 d-cache-sets = <128>; 164 next-level-cache = <&l2_cache_l3>; 165 dynamic-power-coefficient = <228>; 166 #cooling-cells = <2>; 167 }; 168 169 cpu_b0: cpu@400 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a76"; 172 reg = <0x400>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 176 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; 177 assigned-clock-rates = <816000000>; 178 cpu-idle-states = <&CPU_SLEEP>; 179 i-cache-size = <65536>; 180 i-cache-line-size = <64>; 181 i-cache-sets = <256>; 182 d-cache-size = <65536>; 183 d-cache-line-size = <64>; 184 d-cache-sets = <256>; 185 next-level-cache = <&l2_cache_b0>; 186 dynamic-power-coefficient = <416>; 187 #cooling-cells = <2>; 188 }; 189 190 cpu_b1: cpu@500 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-a76"; 193 reg = <0x500>; 194 enable-method = "psci"; 195 capacity-dmips-mhz = <1024>; 196 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 i-cache-size = <65536>; 199 i-cache-line-size = <64>; 200 i-cache-sets = <256>; 201 d-cache-size = <65536>; 202 d-cache-line-size = <64>; 203 d-cache-sets = <256>; 204 next-level-cache = <&l2_cache_b1>; 205 dynamic-power-coefficient = <416>; 206 #cooling-cells = <2>; 207 }; 208 209 cpu_b2: cpu@600 { 210 device_type = "cpu"; 211 compatible = "arm,cortex-a76"; 212 reg = <0x600>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 216 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; 217 assigned-clock-rates = <816000000>; 218 cpu-idle-states = <&CPU_SLEEP>; 219 i-cache-size = <65536>; 220 i-cache-line-size = <64>; 221 i-cache-sets = <256>; 222 d-cache-size = <65536>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <256>; 225 next-level-cache = <&l2_cache_b2>; 226 dynamic-power-coefficient = <416>; 227 #cooling-cells = <2>; 228 }; 229 230 cpu_b3: cpu@700 { 231 device_type = "cpu"; 232 compatible = "arm,cortex-a76"; 233 reg = <0x700>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1024>; 236 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 237 cpu-idle-states = <&CPU_SLEEP>; 238 i-cache-size = <65536>; 239 i-cache-line-size = <64>; 240 i-cache-sets = <256>; 241 d-cache-size = <65536>; 242 d-cache-line-size = <64>; 243 d-cache-sets = <256>; 244 next-level-cache = <&l2_cache_b3>; 245 dynamic-power-coefficient = <416>; 246 #cooling-cells = <2>; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 CPU_SLEEP: cpu-sleep { 252 compatible = "arm,idle-state"; 253 local-timer-stop; 254 arm,psci-suspend-param = <0x0010000>; 255 entry-latency-us = <100>; 256 exit-latency-us = <120>; 257 min-residency-us = <1000>; 258 }; 259 }; 260 261 l2_cache_l0: l2-cache-l0 { 262 compatible = "cache"; 263 cache-size = <131072>; 264 cache-line-size = <64>; 265 cache-sets = <512>; 266 cache-level = <2>; 267 cache-unified; 268 next-level-cache = <&l3_cache>; 269 }; 270 271 l2_cache_l1: l2-cache-l1 { 272 compatible = "cache"; 273 cache-size = <131072>; 274 cache-line-size = <64>; 275 cache-sets = <512>; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&l3_cache>; 279 }; 280 281 l2_cache_l2: l2-cache-l2 { 282 compatible = "cache"; 283 cache-size = <131072>; 284 cache-line-size = <64>; 285 cache-sets = <512>; 286 cache-level = <2>; 287 cache-unified; 288 next-level-cache = <&l3_cache>; 289 }; 290 291 l2_cache_l3: l2-cache-l3 { 292 compatible = "cache"; 293 cache-size = <131072>; 294 cache-line-size = <64>; 295 cache-sets = <512>; 296 cache-level = <2>; 297 cache-unified; 298 next-level-cache = <&l3_cache>; 299 }; 300 301 l2_cache_b0: l2-cache-b0 { 302 compatible = "cache"; 303 cache-size = <524288>; 304 cache-line-size = <64>; 305 cache-sets = <1024>; 306 cache-level = <2>; 307 cache-unified; 308 next-level-cache = <&l3_cache>; 309 }; 310 311 l2_cache_b1: l2-cache-b1 { 312 compatible = "cache"; 313 cache-size = <524288>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 cache-unified; 318 next-level-cache = <&l3_cache>; 319 }; 320 321 l2_cache_b2: l2-cache-b2 { 322 compatible = "cache"; 323 cache-size = <524288>; 324 cache-line-size = <64>; 325 cache-sets = <1024>; 326 cache-level = <2>; 327 cache-unified; 328 next-level-cache = <&l3_cache>; 329 }; 330 331 l2_cache_b3: l2-cache-b3 { 332 compatible = "cache"; 333 cache-size = <524288>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 cache-unified; 338 next-level-cache = <&l3_cache>; 339 }; 340 }; 341 342 /* 343 * The L3 cache belongs to the DynamIQ Shared Unit (DSU), 344 * so it's represented here, outside the "cpus" node 345 */ 346 l3_cache: l3-cache { 347 compatible = "cache"; 348 cache-size = <3145728>; 349 cache-line-size = <64>; 350 cache-sets = <4096>; 351 cache-level = <3>; 352 cache-unified; 353 }; 354 355 display_subsystem: display-subsystem { 356 compatible = "rockchip,display-subsystem"; 357 ports = <&vop_out>; 358 }; 359 360 firmware { 361 scmi: scmi { 362 compatible = "arm,scmi-smc"; 363 arm,smc-id = <0x82000010>; 364 shmem = <&scmi_shmem>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 368 scmi_clk: protocol@14 { 369 reg = <0x14>; 370 #clock-cells = <1>; 371 }; 372 373 scmi_reset: protocol@16 { 374 reg = <0x16>; 375 #reset-cells = <1>; 376 }; 377 }; 378 }; 379 380 hdmi0_sound: hdmi0-sound { 381 compatible = "simple-audio-card"; 382 simple-audio-card,format = "i2s"; 383 simple-audio-card,mclk-fs = <128>; 384 simple-audio-card,name = "hdmi0"; 385 status = "disabled"; 386 387 simple-audio-card,codec { 388 sound-dai = <&hdmi0>; 389 }; 390 391 simple-audio-card,cpu { 392 sound-dai = <&i2s5_8ch>; 393 }; 394 }; 395 396 pmu-a55 { 397 compatible = "arm,cortex-a55-pmu"; 398 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; 399 }; 400 401 pmu-a76 { 402 compatible = "arm,cortex-a76-pmu"; 403 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; 404 }; 405 406 psci { 407 compatible = "arm,psci-1.0"; 408 method = "smc"; 409 }; 410 411 spll: clock-0 { 412 compatible = "fixed-clock"; 413 clock-frequency = <702000000>; 414 clock-output-names = "spll"; 415 #clock-cells = <0>; 416 }; 417 418 timer { 419 compatible = "arm,armv8-timer"; 420 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 421 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 422 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 423 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, 424 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 425 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 426 }; 427 428 xin24m: clock-1 { 429 compatible = "fixed-clock"; 430 clock-frequency = <24000000>; 431 clock-output-names = "xin24m"; 432 #clock-cells = <0>; 433 }; 434 435 xin32k: clock-2 { 436 compatible = "fixed-clock"; 437 clock-frequency = <32768>; 438 clock-output-names = "xin32k"; 439 #clock-cells = <0>; 440 }; 441 442 pmu_sram: sram@10f000 { 443 compatible = "mmio-sram"; 444 reg = <0x0 0x0010f000 0x0 0x100>; 445 ranges = <0 0x0 0x0010f000 0x100>; 446 #address-cells = <1>; 447 #size-cells = <1>; 448 449 scmi_shmem: sram@0 { 450 compatible = "arm,scmi-shmem"; 451 reg = <0x0 0x100>; 452 }; 453 }; 454 455 gpu: gpu@fb000000 { 456 compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; 457 reg = <0x0 0xfb000000 0x0 0x200000>; 458 #cooling-cells = <2>; 459 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 460 assigned-clock-rates = <200000000>; 461 clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 462 <&cru CLK_GPU_STACKS>; 463 clock-names = "core", "coregroup", "stacks"; 464 dynamic-power-coefficient = <2982>; 465 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, 466 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, 467 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; 468 interrupt-names = "job", "mmu", "gpu"; 469 power-domains = <&power RK3588_PD_GPU>; 470 status = "disabled"; 471 }; 472 473 usb_host0_xhci: usb@fc000000 { 474 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 475 reg = <0x0 0xfc000000 0x0 0x400000>; 476 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 477 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 478 <&cru ACLK_USB3OTG0>; 479 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 480 dr_mode = "otg"; 481 phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; 482 phy-names = "usb2-phy", "usb3-phy"; 483 phy_type = "utmi_wide"; 484 power-domains = <&power RK3588_PD_USB>; 485 resets = <&cru SRST_A_USB3OTG0>; 486 snps,dis_enblslpm_quirk; 487 snps,dis-u1-entry-quirk; 488 snps,dis-u2-entry-quirk; 489 snps,dis-u2-freeclk-exists-quirk; 490 snps,dis-del-phy-power-chg-quirk; 491 snps,dis-tx-ipgap-linecheck-quirk; 492 status = "disabled"; 493 }; 494 495 usb_host0_ehci: usb@fc800000 { 496 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 497 reg = <0x0 0xfc800000 0x0 0x40000>; 498 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; 499 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 500 phys = <&u2phy2_host>; 501 phy-names = "usb"; 502 power-domains = <&power RK3588_PD_USB>; 503 status = "disabled"; 504 }; 505 506 usb_host0_ohci: usb@fc840000 { 507 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 508 reg = <0x0 0xfc840000 0x0 0x40000>; 509 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; 510 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; 511 phys = <&u2phy2_host>; 512 phy-names = "usb"; 513 power-domains = <&power RK3588_PD_USB>; 514 status = "disabled"; 515 }; 516 517 usb_host1_ehci: usb@fc880000 { 518 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 519 reg = <0x0 0xfc880000 0x0 0x40000>; 520 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; 521 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 522 phys = <&u2phy3_host>; 523 phy-names = "usb"; 524 power-domains = <&power RK3588_PD_USB>; 525 status = "disabled"; 526 }; 527 528 usb_host1_ohci: usb@fc8c0000 { 529 compatible = "rockchip,rk3588-ohci", "generic-ohci"; 530 reg = <0x0 0xfc8c0000 0x0 0x40000>; 531 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; 532 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; 533 phys = <&u2phy3_host>; 534 phy-names = "usb"; 535 power-domains = <&power RK3588_PD_USB>; 536 status = "disabled"; 537 }; 538 539 usb_host2_xhci: usb@fcd00000 { 540 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 541 reg = <0x0 0xfcd00000 0x0 0x400000>; 542 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 543 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 544 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 545 <&cru CLK_PIPEPHY2_PIPE_U3_G>; 546 clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; 547 dr_mode = "host"; 548 phys = <&combphy2_psu PHY_TYPE_USB3>; 549 phy-names = "usb3-phy"; 550 phy_type = "utmi_wide"; 551 resets = <&cru SRST_A_USB3OTG2>; 552 snps,dis_enblslpm_quirk; 553 snps,dis-u2-freeclk-exists-quirk; 554 snps,dis-del-phy-power-chg-quirk; 555 snps,dis-tx-ipgap-linecheck-quirk; 556 snps,dis_rxdet_inp3_quirk; 557 status = "disabled"; 558 }; 559 560 mmu600_pcie: iommu@fc900000 { 561 compatible = "arm,smmu-v3"; 562 reg = <0x0 0xfc900000 0x0 0x200000>; 563 interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING 0>, 564 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING 0>, 565 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>, 566 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>; 567 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 568 #iommu-cells = <1>; 569 }; 570 571 mmu600_php: iommu@fcb00000 { 572 compatible = "arm,smmu-v3"; 573 reg = <0x0 0xfcb00000 0x0 0x200000>; 574 interrupts = <GIC_SPI 381 IRQ_TYPE_EDGE_RISING 0>, 575 <GIC_SPI 383 IRQ_TYPE_EDGE_RISING 0>, 576 <GIC_SPI 386 IRQ_TYPE_EDGE_RISING 0>, 577 <GIC_SPI 379 IRQ_TYPE_EDGE_RISING 0>; 578 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 579 #iommu-cells = <1>; 580 status = "disabled"; 581 }; 582 583 pmu1grf: syscon@fd58a000 { 584 compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; 585 reg = <0x0 0xfd58a000 0x0 0x10000>; 586 }; 587 588 sys_grf: syscon@fd58c000 { 589 compatible = "rockchip,rk3588-sys-grf", "syscon"; 590 reg = <0x0 0xfd58c000 0x0 0x1000>; 591 }; 592 593 vop_grf: syscon@fd5a4000 { 594 compatible = "rockchip,rk3588-vop-grf", "syscon"; 595 reg = <0x0 0xfd5a4000 0x0 0x2000>; 596 }; 597 598 vo0_grf: syscon@fd5a6000 { 599 compatible = "rockchip,rk3588-vo0-grf", "syscon"; 600 reg = <0x0 0xfd5a6000 0x0 0x2000>; 601 clocks = <&cru PCLK_VO0GRF>; 602 }; 603 604 vo1_grf: syscon@fd5a8000 { 605 compatible = "rockchip,rk3588-vo1-grf", "syscon"; 606 reg = <0x0 0xfd5a8000 0x0 0x4000>; 607 clocks = <&cru PCLK_VO1GRF>; 608 }; 609 610 usb_grf: syscon@fd5ac000 { 611 compatible = "rockchip,rk3588-usb-grf", "syscon"; 612 reg = <0x0 0xfd5ac000 0x0 0x4000>; 613 }; 614 615 php_grf: syscon@fd5b0000 { 616 compatible = "rockchip,rk3588-php-grf", "syscon"; 617 reg = <0x0 0xfd5b0000 0x0 0x1000>; 618 }; 619 620 pipe_phy0_grf: syscon@fd5bc000 { 621 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 622 reg = <0x0 0xfd5bc000 0x0 0x100>; 623 }; 624 625 pipe_phy2_grf: syscon@fd5c4000 { 626 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 627 reg = <0x0 0xfd5c4000 0x0 0x100>; 628 }; 629 630 usbdpphy0_grf: syscon@fd5c8000 { 631 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 632 reg = <0x0 0xfd5c8000 0x0 0x4000>; 633 }; 634 635 usb2phy0_grf: syscon@fd5d0000 { 636 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 637 reg = <0x0 0xfd5d0000 0x0 0x4000>; 638 #address-cells = <1>; 639 #size-cells = <1>; 640 641 u2phy0: usb2phy@0 { 642 compatible = "rockchip,rk3588-usb2phy"; 643 reg = <0x0 0x10>; 644 #clock-cells = <0>; 645 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 646 clock-names = "phyclk"; 647 clock-output-names = "usb480m_phy0"; 648 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; 649 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 650 reset-names = "phy", "apb"; 651 status = "disabled"; 652 653 u2phy0_otg: otg-port { 654 #phy-cells = <0>; 655 status = "disabled"; 656 }; 657 }; 658 }; 659 660 usb2phy2_grf: syscon@fd5d8000 { 661 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 662 reg = <0x0 0xfd5d8000 0x0 0x4000>; 663 #address-cells = <1>; 664 #size-cells = <1>; 665 666 u2phy2: usb2phy@8000 { 667 compatible = "rockchip,rk3588-usb2phy"; 668 reg = <0x8000 0x10>; 669 #clock-cells = <0>; 670 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 671 clock-names = "phyclk"; 672 clock-output-names = "usb480m_phy2"; 673 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 674 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 675 reset-names = "phy", "apb"; 676 status = "disabled"; 677 678 u2phy2_host: host-port { 679 #phy-cells = <0>; 680 status = "disabled"; 681 }; 682 }; 683 }; 684 685 usb2phy3_grf: syscon@fd5dc000 { 686 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 687 reg = <0x0 0xfd5dc000 0x0 0x4000>; 688 #address-cells = <1>; 689 #size-cells = <1>; 690 691 u2phy3: usb2phy@c000 { 692 compatible = "rockchip,rk3588-usb2phy"; 693 reg = <0xc000 0x10>; 694 #clock-cells = <0>; 695 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 696 clock-names = "phyclk"; 697 clock-output-names = "usb480m_phy3"; 698 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 699 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 700 reset-names = "phy", "apb"; 701 status = "disabled"; 702 703 u2phy3_host: host-port { 704 #phy-cells = <0>; 705 status = "disabled"; 706 }; 707 }; 708 }; 709 710 hdptxphy0_grf: syscon@fd5e0000 { 711 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 712 reg = <0x0 0xfd5e0000 0x0 0x100>; 713 }; 714 715 ioc: syscon@fd5f0000 { 716 compatible = "rockchip,rk3588-ioc", "syscon"; 717 reg = <0x0 0xfd5f0000 0x0 0x10000>; 718 }; 719 720 system_sram1: sram@fd600000 { 721 compatible = "mmio-sram"; 722 reg = <0x0 0xfd600000 0x0 0x100000>; 723 ranges = <0x0 0x0 0xfd600000 0x100000>; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 }; 727 728 cru: clock-controller@fd7c0000 { 729 compatible = "rockchip,rk3588-cru"; 730 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 731 assigned-clocks = 732 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 733 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 734 <&cru ACLK_CENTER_ROOT>, 735 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 736 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 737 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 738 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, 739 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 740 <&cru CLK_GPU>; 741 assigned-clock-rates = 742 <1100000000>, <786432000>, 743 <850000000>, <1188000000>, 744 <702000000>, 745 <400000000>, <500000000>, 746 <800000000>, <100000000>, 747 <400000000>, <100000000>, 748 <200000000>, <500000000>, 749 <375000000>, <150000000>, 750 <200000000>; 751 rockchip,grf = <&php_grf>; 752 #clock-cells = <1>; 753 #reset-cells = <1>; 754 }; 755 756 i2c0: i2c@fd880000 { 757 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 758 reg = <0x0 0xfd880000 0x0 0x1000>; 759 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; 760 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 761 clock-names = "i2c", "pclk"; 762 pinctrl-0 = <&i2c0m0_xfer>; 763 pinctrl-names = "default"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 status = "disabled"; 767 }; 768 769 uart0: serial@fd890000 { 770 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 771 reg = <0x0 0xfd890000 0x0 0x100>; 772 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 773 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 774 clock-names = "baudclk", "apb_pclk"; 775 dmas = <&dmac0 6>, <&dmac0 7>; 776 dma-names = "tx", "rx"; 777 pinctrl-0 = <&uart0m1_xfer>; 778 pinctrl-names = "default"; 779 reg-shift = <2>; 780 reg-io-width = <4>; 781 status = "disabled"; 782 }; 783 784 pwm0: pwm@fd8b0000 { 785 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 786 reg = <0x0 0xfd8b0000 0x0 0x10>; 787 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 788 clock-names = "pwm", "pclk"; 789 pinctrl-0 = <&pwm0m0_pins>; 790 pinctrl-names = "default"; 791 #pwm-cells = <3>; 792 status = "disabled"; 793 }; 794 795 pwm1: pwm@fd8b0010 { 796 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 797 reg = <0x0 0xfd8b0010 0x0 0x10>; 798 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 799 clock-names = "pwm", "pclk"; 800 pinctrl-0 = <&pwm1m0_pins>; 801 pinctrl-names = "default"; 802 #pwm-cells = <3>; 803 status = "disabled"; 804 }; 805 806 pwm2: pwm@fd8b0020 { 807 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 808 reg = <0x0 0xfd8b0020 0x0 0x10>; 809 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 810 clock-names = "pwm", "pclk"; 811 pinctrl-0 = <&pwm2m0_pins>; 812 pinctrl-names = "default"; 813 #pwm-cells = <3>; 814 status = "disabled"; 815 }; 816 817 pwm3: pwm@fd8b0030 { 818 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 819 reg = <0x0 0xfd8b0030 0x0 0x10>; 820 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 821 clock-names = "pwm", "pclk"; 822 pinctrl-0 = <&pwm3m0_pins>; 823 pinctrl-names = "default"; 824 #pwm-cells = <3>; 825 status = "disabled"; 826 }; 827 828 pmu: power-management@fd8d8000 { 829 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 830 reg = <0x0 0xfd8d8000 0x0 0x400>; 831 832 power: power-controller { 833 compatible = "rockchip,rk3588-power-controller"; 834 #address-cells = <1>; 835 #power-domain-cells = <1>; 836 #size-cells = <0>; 837 status = "okay"; 838 839 /* These power domains are grouped by VD_NPU */ 840 power-domain@RK3588_PD_NPU { 841 reg = <RK3588_PD_NPU>; 842 #power-domain-cells = <0>; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 846 power-domain@RK3588_PD_NPUTOP { 847 reg = <RK3588_PD_NPUTOP>; 848 clocks = <&cru HCLK_NPU_ROOT>, 849 <&cru PCLK_NPU_ROOT>, 850 <&cru CLK_NPU_DSU0>, 851 <&cru HCLK_NPU_CM0_ROOT>; 852 pm_qos = <&qos_npu0_mwr>, 853 <&qos_npu0_mro>, 854 <&qos_mcu_npu>; 855 #power-domain-cells = <0>; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 859 power-domain@RK3588_PD_NPU1 { 860 reg = <RK3588_PD_NPU1>; 861 clocks = <&cru HCLK_NPU_ROOT>, 862 <&cru PCLK_NPU_ROOT>, 863 <&cru CLK_NPU_DSU0>; 864 pm_qos = <&qos_npu1>; 865 #power-domain-cells = <0>; 866 }; 867 power-domain@RK3588_PD_NPU2 { 868 reg = <RK3588_PD_NPU2>; 869 clocks = <&cru HCLK_NPU_ROOT>, 870 <&cru PCLK_NPU_ROOT>, 871 <&cru CLK_NPU_DSU0>; 872 pm_qos = <&qos_npu2>; 873 #power-domain-cells = <0>; 874 }; 875 }; 876 }; 877 /* These power domains are grouped by VD_GPU */ 878 pd_gpu: power-domain@RK3588_PD_GPU { 879 reg = <RK3588_PD_GPU>; 880 clocks = <&cru CLK_GPU>, 881 <&cru CLK_GPU_COREGROUP>, 882 <&cru CLK_GPU_STACKS>; 883 pm_qos = <&qos_gpu_m0>, 884 <&qos_gpu_m1>, 885 <&qos_gpu_m2>, 886 <&qos_gpu_m3>; 887 #power-domain-cells = <0>; 888 }; 889 /* These power domains are grouped by VD_VCODEC */ 890 power-domain@RK3588_PD_VCODEC { 891 reg = <RK3588_PD_VCODEC>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 #power-domain-cells = <0>; 895 896 power-domain@RK3588_PD_RKVDEC0 { 897 reg = <RK3588_PD_RKVDEC0>; 898 clocks = <&cru HCLK_RKVDEC0>, 899 <&cru HCLK_VDPU_ROOT>, 900 <&cru ACLK_VDPU_ROOT>, 901 <&cru ACLK_RKVDEC0>, 902 <&cru ACLK_RKVDEC_CCU>; 903 pm_qos = <&qos_rkvdec0>; 904 #power-domain-cells = <0>; 905 }; 906 power-domain@RK3588_PD_RKVDEC1 { 907 reg = <RK3588_PD_RKVDEC1>; 908 clocks = <&cru HCLK_RKVDEC1>, 909 <&cru HCLK_VDPU_ROOT>, 910 <&cru ACLK_VDPU_ROOT>, 911 <&cru ACLK_RKVDEC1>; 912 pm_qos = <&qos_rkvdec1>; 913 #power-domain-cells = <0>; 914 }; 915 power-domain@RK3588_PD_VENC0 { 916 reg = <RK3588_PD_VENC0>; 917 clocks = <&cru HCLK_RKVENC0>, 918 <&cru ACLK_RKVENC0>; 919 pm_qos = <&qos_rkvenc0_m0ro>, 920 <&qos_rkvenc0_m1ro>, 921 <&qos_rkvenc0_m2wo>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 #power-domain-cells = <0>; 925 926 power-domain@RK3588_PD_VENC1 { 927 reg = <RK3588_PD_VENC1>; 928 clocks = <&cru HCLK_RKVENC1>, 929 <&cru HCLK_RKVENC0>, 930 <&cru ACLK_RKVENC0>, 931 <&cru ACLK_RKVENC1>; 932 pm_qos = <&qos_rkvenc1_m0ro>, 933 <&qos_rkvenc1_m1ro>, 934 <&qos_rkvenc1_m2wo>; 935 #power-domain-cells = <0>; 936 }; 937 }; 938 }; 939 /* These power domains are grouped by VD_LOGIC */ 940 power-domain@RK3588_PD_VDPU { 941 reg = <RK3588_PD_VDPU>; 942 clocks = <&cru HCLK_VDPU_ROOT>, 943 <&cru ACLK_VDPU_LOW_ROOT>, 944 <&cru ACLK_VDPU_ROOT>, 945 <&cru ACLK_JPEG_DECODER_ROOT>, 946 <&cru ACLK_IEP2P0>, 947 <&cru HCLK_IEP2P0>, 948 <&cru ACLK_JPEG_ENCODER0>, 949 <&cru HCLK_JPEG_ENCODER0>, 950 <&cru ACLK_JPEG_ENCODER1>, 951 <&cru HCLK_JPEG_ENCODER1>, 952 <&cru ACLK_JPEG_ENCODER2>, 953 <&cru HCLK_JPEG_ENCODER2>, 954 <&cru ACLK_JPEG_ENCODER3>, 955 <&cru HCLK_JPEG_ENCODER3>, 956 <&cru ACLK_JPEG_DECODER>, 957 <&cru HCLK_JPEG_DECODER>, 958 <&cru ACLK_RGA2>, 959 <&cru HCLK_RGA2>; 960 pm_qos = <&qos_iep>, 961 <&qos_jpeg_dec>, 962 <&qos_jpeg_enc0>, 963 <&qos_jpeg_enc1>, 964 <&qos_jpeg_enc2>, 965 <&qos_jpeg_enc3>, 966 <&qos_rga2_mro>, 967 <&qos_rga2_mwo>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 #power-domain-cells = <0>; 971 972 973 power-domain@RK3588_PD_AV1 { 974 reg = <RK3588_PD_AV1>; 975 clocks = <&cru PCLK_AV1>, 976 <&cru ACLK_AV1>, 977 <&cru HCLK_VDPU_ROOT>; 978 pm_qos = <&qos_av1>; 979 #power-domain-cells = <0>; 980 }; 981 power-domain@RK3588_PD_RKVDEC0 { 982 reg = <RK3588_PD_RKVDEC0>; 983 clocks = <&cru HCLK_RKVDEC0>, 984 <&cru HCLK_VDPU_ROOT>, 985 <&cru ACLK_VDPU_ROOT>, 986 <&cru ACLK_RKVDEC0>; 987 pm_qos = <&qos_rkvdec0>; 988 #power-domain-cells = <0>; 989 }; 990 power-domain@RK3588_PD_RKVDEC1 { 991 reg = <RK3588_PD_RKVDEC1>; 992 clocks = <&cru HCLK_RKVDEC1>, 993 <&cru HCLK_VDPU_ROOT>, 994 <&cru ACLK_VDPU_ROOT>; 995 pm_qos = <&qos_rkvdec1>; 996 #power-domain-cells = <0>; 997 }; 998 power-domain@RK3588_PD_RGA30 { 999 reg = <RK3588_PD_RGA30>; 1000 clocks = <&cru ACLK_RGA3_0>, 1001 <&cru HCLK_RGA3_0>; 1002 pm_qos = <&qos_rga3_0>; 1003 #power-domain-cells = <0>; 1004 }; 1005 }; 1006 power-domain@RK3588_PD_VOP { 1007 reg = <RK3588_PD_VOP>; 1008 clocks = <&cru PCLK_VOP_ROOT>, 1009 <&cru HCLK_VOP_ROOT>, 1010 <&cru ACLK_VOP>; 1011 pm_qos = <&qos_vop_m0>, 1012 <&qos_vop_m1>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 #power-domain-cells = <0>; 1016 1017 power-domain@RK3588_PD_VO0 { 1018 reg = <RK3588_PD_VO0>; 1019 clocks = <&cru PCLK_VO0_ROOT>, 1020 <&cru PCLK_VO0_S_ROOT>, 1021 <&cru HCLK_VO0_S_ROOT>, 1022 <&cru ACLK_VO0_ROOT>, 1023 <&cru HCLK_HDCP0>, 1024 <&cru ACLK_HDCP0>, 1025 <&cru HCLK_VOP_ROOT>; 1026 pm_qos = <&qos_hdcp0>; 1027 #power-domain-cells = <0>; 1028 }; 1029 }; 1030 power-domain@RK3588_PD_VO1 { 1031 reg = <RK3588_PD_VO1>; 1032 clocks = <&cru PCLK_VO1_ROOT>, 1033 <&cru PCLK_VO1_S_ROOT>, 1034 <&cru HCLK_VO1_S_ROOT>, 1035 <&cru HCLK_HDCP1>, 1036 <&cru ACLK_HDCP1>, 1037 <&cru ACLK_HDMIRX_ROOT>, 1038 <&cru HCLK_VO1USB_TOP_ROOT>; 1039 pm_qos = <&qos_hdcp1>, 1040 <&qos_hdmirx>; 1041 #power-domain-cells = <0>; 1042 }; 1043 power-domain@RK3588_PD_VI { 1044 reg = <RK3588_PD_VI>; 1045 clocks = <&cru HCLK_VI_ROOT>, 1046 <&cru PCLK_VI_ROOT>, 1047 <&cru HCLK_ISP0>, 1048 <&cru ACLK_ISP0>, 1049 <&cru HCLK_VICAP>, 1050 <&cru ACLK_VICAP>; 1051 pm_qos = <&qos_isp0_mro>, 1052 <&qos_isp0_mwo>, 1053 <&qos_vicap_m0>, 1054 <&qos_vicap_m1>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 #power-domain-cells = <0>; 1058 1059 power-domain@RK3588_PD_ISP1 { 1060 reg = <RK3588_PD_ISP1>; 1061 clocks = <&cru HCLK_ISP1>, 1062 <&cru ACLK_ISP1>, 1063 <&cru HCLK_VI_ROOT>, 1064 <&cru PCLK_VI_ROOT>; 1065 pm_qos = <&qos_isp1_mwo>, 1066 <&qos_isp1_mro>; 1067 #power-domain-cells = <0>; 1068 }; 1069 power-domain@RK3588_PD_FEC { 1070 reg = <RK3588_PD_FEC>; 1071 clocks = <&cru HCLK_FISHEYE0>, 1072 <&cru ACLK_FISHEYE0>, 1073 <&cru HCLK_FISHEYE1>, 1074 <&cru ACLK_FISHEYE1>, 1075 <&cru PCLK_VI_ROOT>; 1076 pm_qos = <&qos_fisheye0>, 1077 <&qos_fisheye1>; 1078 #power-domain-cells = <0>; 1079 }; 1080 }; 1081 power-domain@RK3588_PD_RGA31 { 1082 reg = <RK3588_PD_RGA31>; 1083 clocks = <&cru HCLK_RGA3_1>, 1084 <&cru ACLK_RGA3_1>; 1085 pm_qos = <&qos_rga3_1>; 1086 #power-domain-cells = <0>; 1087 }; 1088 power-domain@RK3588_PD_USB { 1089 reg = <RK3588_PD_USB>; 1090 clocks = <&cru PCLK_PHP_ROOT>, 1091 <&cru ACLK_USB_ROOT>, 1092 <&cru ACLK_USB>, 1093 <&cru HCLK_USB_ROOT>, 1094 <&cru HCLK_HOST0>, 1095 <&cru HCLK_HOST_ARB0>, 1096 <&cru HCLK_HOST1>, 1097 <&cru HCLK_HOST_ARB1>; 1098 pm_qos = <&qos_usb3_0>, 1099 <&qos_usb3_1>, 1100 <&qos_usb2host_0>, 1101 <&qos_usb2host_1>; 1102 #power-domain-cells = <0>; 1103 }; 1104 power-domain@RK3588_PD_GMAC { 1105 reg = <RK3588_PD_GMAC>; 1106 clocks = <&cru PCLK_PHP_ROOT>, 1107 <&cru ACLK_PCIE_ROOT>, 1108 <&cru ACLK_PHP_ROOT>; 1109 #power-domain-cells = <0>; 1110 }; 1111 power-domain@RK3588_PD_PCIE { 1112 reg = <RK3588_PD_PCIE>; 1113 clocks = <&cru PCLK_PHP_ROOT>, 1114 <&cru ACLK_PCIE_ROOT>, 1115 <&cru ACLK_PHP_ROOT>; 1116 #power-domain-cells = <0>; 1117 }; 1118 power-domain@RK3588_PD_SDIO { 1119 reg = <RK3588_PD_SDIO>; 1120 clocks = <&cru HCLK_SDIO>, 1121 <&cru HCLK_NVM_ROOT>; 1122 pm_qos = <&qos_sdio>; 1123 #power-domain-cells = <0>; 1124 }; 1125 power-domain@RK3588_PD_AUDIO { 1126 reg = <RK3588_PD_AUDIO>; 1127 clocks = <&cru HCLK_AUDIO_ROOT>, 1128 <&cru PCLK_AUDIO_ROOT>; 1129 #power-domain-cells = <0>; 1130 }; 1131 power-domain@RK3588_PD_SDMMC { 1132 reg = <RK3588_PD_SDMMC>; 1133 pm_qos = <&qos_sdmmc>; 1134 #power-domain-cells = <0>; 1135 }; 1136 }; 1137 }; 1138 1139 vpu121: video-codec@fdb50000 { 1140 compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; 1141 reg = <0x0 0xfdb50000 0x0 0x800>; 1142 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1143 interrupt-names = "vdpu"; 1144 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1145 clock-names = "aclk", "hclk"; 1146 iommus = <&vpu121_mmu>; 1147 power-domains = <&power RK3588_PD_VDPU>; 1148 }; 1149 1150 vpu121_mmu: iommu@fdb50800 { 1151 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1152 reg = <0x0 0xfdb50800 0x0 0x40>; 1153 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1154 clock-names = "aclk", "iface"; 1155 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1156 power-domains = <&power RK3588_PD_VDPU>; 1157 #iommu-cells = <0>; 1158 }; 1159 1160 rga: rga@fdb80000 { 1161 compatible = "rockchip,rk3588-rga", "rockchip,rk3288-rga"; 1162 reg = <0x0 0xfdb80000 0x0 0x180>; 1163 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1164 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 1165 clock-names = "aclk", "hclk", "sclk"; 1166 resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; 1167 reset-names = "core", "axi", "ahb"; 1168 power-domains = <&power RK3588_PD_VDPU>; 1169 }; 1170 1171 vepu121_0: video-codec@fdba0000 { 1172 compatible = "rockchip,rk3588-vepu121"; 1173 reg = <0x0 0xfdba0000 0x0 0x800>; 1174 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>; 1175 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1176 clock-names = "aclk", "hclk"; 1177 iommus = <&vepu121_0_mmu>; 1178 power-domains = <&power RK3588_PD_VDPU>; 1179 }; 1180 1181 vepu121_0_mmu: iommu@fdba0800 { 1182 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1183 reg = <0x0 0xfdba0800 0x0 0x40>; 1184 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 1185 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 1186 clock-names = "aclk", "iface"; 1187 power-domains = <&power RK3588_PD_VDPU>; 1188 #iommu-cells = <0>; 1189 }; 1190 1191 vepu121_1: video-codec@fdba4000 { 1192 compatible = "rockchip,rk3588-vepu121"; 1193 reg = <0x0 0xfdba4000 0x0 0x800>; 1194 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>; 1195 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1196 clock-names = "aclk", "hclk"; 1197 iommus = <&vepu121_1_mmu>; 1198 power-domains = <&power RK3588_PD_VDPU>; 1199 }; 1200 1201 vepu121_1_mmu: iommu@fdba4800 { 1202 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1203 reg = <0x0 0xfdba4800 0x0 0x40>; 1204 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 1206 clock-names = "aclk", "iface"; 1207 power-domains = <&power RK3588_PD_VDPU>; 1208 #iommu-cells = <0>; 1209 }; 1210 1211 vepu121_2: video-codec@fdba8000 { 1212 compatible = "rockchip,rk3588-vepu121"; 1213 reg = <0x0 0xfdba8000 0x0 0x800>; 1214 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>; 1215 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1216 clock-names = "aclk", "hclk"; 1217 iommus = <&vepu121_2_mmu>; 1218 power-domains = <&power RK3588_PD_VDPU>; 1219 }; 1220 1221 vepu121_2_mmu: iommu@fdba8800 { 1222 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1223 reg = <0x0 0xfdba8800 0x0 0x40>; 1224 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1225 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 1226 clock-names = "aclk", "iface"; 1227 power-domains = <&power RK3588_PD_VDPU>; 1228 #iommu-cells = <0>; 1229 }; 1230 1231 vepu121_3: video-codec@fdbac000 { 1232 compatible = "rockchip,rk3588-vepu121"; 1233 reg = <0x0 0xfdbac000 0x0 0x800>; 1234 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1235 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1236 clock-names = "aclk", "hclk"; 1237 iommus = <&vepu121_3_mmu>; 1238 power-domains = <&power RK3588_PD_VDPU>; 1239 }; 1240 1241 vepu121_3_mmu: iommu@fdbac800 { 1242 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1243 reg = <0x0 0xfdbac800 0x0 0x40>; 1244 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; 1245 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 1246 clock-names = "aclk", "iface"; 1247 power-domains = <&power RK3588_PD_VDPU>; 1248 #iommu-cells = <0>; 1249 }; 1250 1251 av1d: video-codec@fdc70000 { 1252 compatible = "rockchip,rk3588-av1-vpu"; 1253 reg = <0x0 0xfdc70000 0x0 0x800>; 1254 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1255 interrupt-names = "vdpu"; 1256 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1257 assigned-clock-rates = <400000000>, <400000000>; 1258 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 1259 clock-names = "aclk", "hclk"; 1260 power-domains = <&power RK3588_PD_AV1>; 1261 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; 1262 }; 1263 1264 vop: vop@fdd90000 { 1265 compatible = "rockchip,rk3588-vop"; 1266 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 1267 reg-names = "vop", "gamma-lut"; 1268 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1269 clocks = <&cru ACLK_VOP>, 1270 <&cru HCLK_VOP>, 1271 <&cru DCLK_VOP0>, 1272 <&cru DCLK_VOP1>, 1273 <&cru DCLK_VOP2>, 1274 <&cru DCLK_VOP3>, 1275 <&cru PCLK_VOP_ROOT>, 1276 <&hdptxphy0>; 1277 clock-names = "aclk", 1278 "hclk", 1279 "dclk_vp0", 1280 "dclk_vp1", 1281 "dclk_vp2", 1282 "dclk_vp3", 1283 "pclk_vop", 1284 "pll_hdmiphy0"; 1285 iommus = <&vop_mmu>; 1286 power-domains = <&power RK3588_PD_VOP>; 1287 rockchip,grf = <&sys_grf>; 1288 rockchip,vop-grf = <&vop_grf>; 1289 rockchip,vo1-grf = <&vo1_grf>; 1290 rockchip,pmu = <&pmu>; 1291 status = "disabled"; 1292 1293 vop_out: ports { 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 1297 vp0: port@0 { 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 reg = <0>; 1301 }; 1302 1303 vp1: port@1 { 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 reg = <1>; 1307 }; 1308 1309 vp2: port@2 { 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 reg = <2>; 1313 }; 1314 1315 vp3: port@3 { 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 reg = <3>; 1319 }; 1320 }; 1321 }; 1322 1323 vop_mmu: iommu@fdd97e00 { 1324 compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; 1325 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1326 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1327 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1328 clock-names = "aclk", "iface"; 1329 #iommu-cells = <0>; 1330 power-domains = <&power RK3588_PD_VOP>; 1331 status = "disabled"; 1332 }; 1333 1334 spdif_tx2: spdif-tx@fddb0000 { 1335 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1336 reg = <0x0 0xfddb0000 0x0 0x1000>; 1337 assigned-clock-parents = <&cru PLL_AUPLL>; 1338 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; 1339 clock-names = "mclk", "hclk"; 1340 clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; 1341 dma-names = "tx"; 1342 dmas = <&dmac1 6>; 1343 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1344 power-domains = <&power RK3588_PD_VO0>; 1345 #sound-dai-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 i2s4_8ch: i2s@fddc0000 { 1350 compatible = "rockchip,rk3588-i2s-tdm"; 1351 reg = <0x0 0xfddc0000 0x0 0x1000>; 1352 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; 1353 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1354 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1355 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 1356 assigned-clock-parents = <&cru PLL_AUPLL>; 1357 dmas = <&dmac2 0>; 1358 dma-names = "tx"; 1359 power-domains = <&power RK3588_PD_VO0>; 1360 resets = <&cru SRST_M_I2S4_8CH_TX>; 1361 reset-names = "tx-m"; 1362 #sound-dai-cells = <0>; 1363 status = "disabled"; 1364 }; 1365 1366 spdif_tx3: spdif-tx@fdde0000 { 1367 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1368 reg = <0x0 0xfdde0000 0x0 0x1000>; 1369 assigned-clock-parents = <&cru PLL_AUPLL>; 1370 assigned-clocks = <&cru CLK_SPDIF3_SRC>; 1371 clock-names = "mclk", "hclk"; 1372 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1373 dma-names = "tx"; 1374 dmas = <&dmac1 7>; 1375 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1376 power-domains = <&power RK3588_PD_VO1>; 1377 #sound-dai-cells = <0>; 1378 status = "disabled"; 1379 }; 1380 1381 i2s5_8ch: i2s@fddf0000 { 1382 compatible = "rockchip,rk3588-i2s-tdm"; 1383 reg = <0x0 0xfddf0000 0x0 0x1000>; 1384 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; 1385 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1386 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1387 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 1388 assigned-clock-parents = <&cru PLL_AUPLL>; 1389 dmas = <&dmac2 2>; 1390 dma-names = "tx"; 1391 power-domains = <&power RK3588_PD_VO1>; 1392 resets = <&cru SRST_M_I2S5_8CH_TX>; 1393 reset-names = "tx-m"; 1394 #sound-dai-cells = <0>; 1395 status = "disabled"; 1396 }; 1397 1398 i2s9_8ch: i2s@fddfc000 { 1399 compatible = "rockchip,rk3588-i2s-tdm"; 1400 reg = <0x0 0xfddfc000 0x0 0x1000>; 1401 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; 1402 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1403 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1404 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 1405 assigned-clock-parents = <&cru PLL_AUPLL>; 1406 dmas = <&dmac2 23>; 1407 dma-names = "rx"; 1408 power-domains = <&power RK3588_PD_VO1>; 1409 resets = <&cru SRST_M_I2S9_8CH_RX>; 1410 reset-names = "rx-m"; 1411 #sound-dai-cells = <0>; 1412 status = "disabled"; 1413 }; 1414 1415 hdmi0: hdmi@fde80000 { 1416 compatible = "rockchip,rk3588-dw-hdmi-qp"; 1417 reg = <0x0 0xfde80000 0x0 0x20000>; 1418 clocks = <&cru PCLK_HDMITX0>, 1419 <&cru CLK_HDMITX0_EARC>, 1420 <&cru CLK_HDMITX0_REF>, 1421 <&cru MCLK_I2S5_8CH_TX>, 1422 <&cru CLK_HDMIHDP0>, 1423 <&cru HCLK_VO1>; 1424 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1425 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>, 1427 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>, 1428 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>, 1429 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>; 1430 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1431 phys = <&hdptxphy0>; 1432 pinctrl-names = "default"; 1433 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd 1434 &hdmim0_tx0_scl &hdmim0_tx0_sda>; 1435 power-domains = <&power RK3588_PD_VO1>; 1436 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 1437 reset-names = "ref", "hdp"; 1438 rockchip,grf = <&sys_grf>; 1439 rockchip,vo-grf = <&vo1_grf>; 1440 #sound-dai-cells = <0>; 1441 status = "disabled"; 1442 1443 ports { 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 1447 hdmi0_in: port@0 { 1448 reg = <0>; 1449 }; 1450 1451 hdmi0_out: port@1 { 1452 reg = <1>; 1453 }; 1454 }; 1455 }; 1456 1457 qos_gpu_m0: qos@fdf35000 { 1458 compatible = "rockchip,rk3588-qos", "syscon"; 1459 reg = <0x0 0xfdf35000 0x0 0x20>; 1460 }; 1461 1462 qos_gpu_m1: qos@fdf35200 { 1463 compatible = "rockchip,rk3588-qos", "syscon"; 1464 reg = <0x0 0xfdf35200 0x0 0x20>; 1465 }; 1466 1467 qos_gpu_m2: qos@fdf35400 { 1468 compatible = "rockchip,rk3588-qos", "syscon"; 1469 reg = <0x0 0xfdf35400 0x0 0x20>; 1470 }; 1471 1472 qos_gpu_m3: qos@fdf35600 { 1473 compatible = "rockchip,rk3588-qos", "syscon"; 1474 reg = <0x0 0xfdf35600 0x0 0x20>; 1475 }; 1476 1477 qos_rga3_1: qos@fdf36000 { 1478 compatible = "rockchip,rk3588-qos", "syscon"; 1479 reg = <0x0 0xfdf36000 0x0 0x20>; 1480 }; 1481 1482 qos_sdio: qos@fdf39000 { 1483 compatible = "rockchip,rk3588-qos", "syscon"; 1484 reg = <0x0 0xfdf39000 0x0 0x20>; 1485 }; 1486 1487 qos_sdmmc: qos@fdf3d800 { 1488 compatible = "rockchip,rk3588-qos", "syscon"; 1489 reg = <0x0 0xfdf3d800 0x0 0x20>; 1490 }; 1491 1492 qos_usb3_1: qos@fdf3e000 { 1493 compatible = "rockchip,rk3588-qos", "syscon"; 1494 reg = <0x0 0xfdf3e000 0x0 0x20>; 1495 }; 1496 1497 qos_usb3_0: qos@fdf3e200 { 1498 compatible = "rockchip,rk3588-qos", "syscon"; 1499 reg = <0x0 0xfdf3e200 0x0 0x20>; 1500 }; 1501 1502 qos_usb2host_0: qos@fdf3e400 { 1503 compatible = "rockchip,rk3588-qos", "syscon"; 1504 reg = <0x0 0xfdf3e400 0x0 0x20>; 1505 }; 1506 1507 qos_usb2host_1: qos@fdf3e600 { 1508 compatible = "rockchip,rk3588-qos", "syscon"; 1509 reg = <0x0 0xfdf3e600 0x0 0x20>; 1510 }; 1511 1512 qos_fisheye0: qos@fdf40000 { 1513 compatible = "rockchip,rk3588-qos", "syscon"; 1514 reg = <0x0 0xfdf40000 0x0 0x20>; 1515 }; 1516 1517 qos_fisheye1: qos@fdf40200 { 1518 compatible = "rockchip,rk3588-qos", "syscon"; 1519 reg = <0x0 0xfdf40200 0x0 0x20>; 1520 }; 1521 1522 qos_isp0_mro: qos@fdf40400 { 1523 compatible = "rockchip,rk3588-qos", "syscon"; 1524 reg = <0x0 0xfdf40400 0x0 0x20>; 1525 }; 1526 1527 qos_isp0_mwo: qos@fdf40500 { 1528 compatible = "rockchip,rk3588-qos", "syscon"; 1529 reg = <0x0 0xfdf40500 0x0 0x20>; 1530 }; 1531 1532 qos_vicap_m0: qos@fdf40600 { 1533 compatible = "rockchip,rk3588-qos", "syscon"; 1534 reg = <0x0 0xfdf40600 0x0 0x20>; 1535 }; 1536 1537 qos_vicap_m1: qos@fdf40800 { 1538 compatible = "rockchip,rk3588-qos", "syscon"; 1539 reg = <0x0 0xfdf40800 0x0 0x20>; 1540 }; 1541 1542 qos_isp1_mwo: qos@fdf41000 { 1543 compatible = "rockchip,rk3588-qos", "syscon"; 1544 reg = <0x0 0xfdf41000 0x0 0x20>; 1545 }; 1546 1547 qos_isp1_mro: qos@fdf41100 { 1548 compatible = "rockchip,rk3588-qos", "syscon"; 1549 reg = <0x0 0xfdf41100 0x0 0x20>; 1550 }; 1551 1552 qos_rkvenc0_m0ro: qos@fdf60000 { 1553 compatible = "rockchip,rk3588-qos", "syscon"; 1554 reg = <0x0 0xfdf60000 0x0 0x20>; 1555 }; 1556 1557 qos_rkvenc0_m1ro: qos@fdf60200 { 1558 compatible = "rockchip,rk3588-qos", "syscon"; 1559 reg = <0x0 0xfdf60200 0x0 0x20>; 1560 }; 1561 1562 qos_rkvenc0_m2wo: qos@fdf60400 { 1563 compatible = "rockchip,rk3588-qos", "syscon"; 1564 reg = <0x0 0xfdf60400 0x0 0x20>; 1565 }; 1566 1567 qos_rkvenc1_m0ro: qos@fdf61000 { 1568 compatible = "rockchip,rk3588-qos", "syscon"; 1569 reg = <0x0 0xfdf61000 0x0 0x20>; 1570 }; 1571 1572 qos_rkvenc1_m1ro: qos@fdf61200 { 1573 compatible = "rockchip,rk3588-qos", "syscon"; 1574 reg = <0x0 0xfdf61200 0x0 0x20>; 1575 }; 1576 1577 qos_rkvenc1_m2wo: qos@fdf61400 { 1578 compatible = "rockchip,rk3588-qos", "syscon"; 1579 reg = <0x0 0xfdf61400 0x0 0x20>; 1580 }; 1581 1582 qos_rkvdec0: qos@fdf62000 { 1583 compatible = "rockchip,rk3588-qos", "syscon"; 1584 reg = <0x0 0xfdf62000 0x0 0x20>; 1585 }; 1586 1587 qos_rkvdec1: qos@fdf63000 { 1588 compatible = "rockchip,rk3588-qos", "syscon"; 1589 reg = <0x0 0xfdf63000 0x0 0x20>; 1590 }; 1591 1592 qos_av1: qos@fdf64000 { 1593 compatible = "rockchip,rk3588-qos", "syscon"; 1594 reg = <0x0 0xfdf64000 0x0 0x20>; 1595 }; 1596 1597 qos_iep: qos@fdf66000 { 1598 compatible = "rockchip,rk3588-qos", "syscon"; 1599 reg = <0x0 0xfdf66000 0x0 0x20>; 1600 }; 1601 1602 qos_jpeg_dec: qos@fdf66200 { 1603 compatible = "rockchip,rk3588-qos", "syscon"; 1604 reg = <0x0 0xfdf66200 0x0 0x20>; 1605 }; 1606 1607 qos_jpeg_enc0: qos@fdf66400 { 1608 compatible = "rockchip,rk3588-qos", "syscon"; 1609 reg = <0x0 0xfdf66400 0x0 0x20>; 1610 }; 1611 1612 qos_jpeg_enc1: qos@fdf66600 { 1613 compatible = "rockchip,rk3588-qos", "syscon"; 1614 reg = <0x0 0xfdf66600 0x0 0x20>; 1615 }; 1616 1617 qos_jpeg_enc2: qos@fdf66800 { 1618 compatible = "rockchip,rk3588-qos", "syscon"; 1619 reg = <0x0 0xfdf66800 0x0 0x20>; 1620 }; 1621 1622 qos_jpeg_enc3: qos@fdf66a00 { 1623 compatible = "rockchip,rk3588-qos", "syscon"; 1624 reg = <0x0 0xfdf66a00 0x0 0x20>; 1625 }; 1626 1627 qos_rga2_mro: qos@fdf66c00 { 1628 compatible = "rockchip,rk3588-qos", "syscon"; 1629 reg = <0x0 0xfdf66c00 0x0 0x20>; 1630 }; 1631 1632 qos_rga2_mwo: qos@fdf66e00 { 1633 compatible = "rockchip,rk3588-qos", "syscon"; 1634 reg = <0x0 0xfdf66e00 0x0 0x20>; 1635 }; 1636 1637 qos_rga3_0: qos@fdf67000 { 1638 compatible = "rockchip,rk3588-qos", "syscon"; 1639 reg = <0x0 0xfdf67000 0x0 0x20>; 1640 }; 1641 1642 qos_vdpu: qos@fdf67200 { 1643 compatible = "rockchip,rk3588-qos", "syscon"; 1644 reg = <0x0 0xfdf67200 0x0 0x20>; 1645 }; 1646 1647 qos_npu1: qos@fdf70000 { 1648 compatible = "rockchip,rk3588-qos", "syscon"; 1649 reg = <0x0 0xfdf70000 0x0 0x20>; 1650 }; 1651 1652 qos_npu2: qos@fdf71000 { 1653 compatible = "rockchip,rk3588-qos", "syscon"; 1654 reg = <0x0 0xfdf71000 0x0 0x20>; 1655 }; 1656 1657 qos_npu0_mwr: qos@fdf72000 { 1658 compatible = "rockchip,rk3588-qos", "syscon"; 1659 reg = <0x0 0xfdf72000 0x0 0x20>; 1660 }; 1661 1662 qos_npu0_mro: qos@fdf72200 { 1663 compatible = "rockchip,rk3588-qos", "syscon"; 1664 reg = <0x0 0xfdf72200 0x0 0x20>; 1665 }; 1666 1667 qos_mcu_npu: qos@fdf72400 { 1668 compatible = "rockchip,rk3588-qos", "syscon"; 1669 reg = <0x0 0xfdf72400 0x0 0x20>; 1670 }; 1671 1672 qos_hdcp0: qos@fdf80000 { 1673 compatible = "rockchip,rk3588-qos", "syscon"; 1674 reg = <0x0 0xfdf80000 0x0 0x20>; 1675 }; 1676 1677 qos_hdcp1: qos@fdf81000 { 1678 compatible = "rockchip,rk3588-qos", "syscon"; 1679 reg = <0x0 0xfdf81000 0x0 0x20>; 1680 }; 1681 1682 qos_hdmirx: qos@fdf81200 { 1683 compatible = "rockchip,rk3588-qos", "syscon"; 1684 reg = <0x0 0xfdf81200 0x0 0x20>; 1685 }; 1686 1687 qos_vop_m0: qos@fdf82000 { 1688 compatible = "rockchip,rk3588-qos", "syscon"; 1689 reg = <0x0 0xfdf82000 0x0 0x20>; 1690 }; 1691 1692 qos_vop_m1: qos@fdf82200 { 1693 compatible = "rockchip,rk3588-qos", "syscon"; 1694 reg = <0x0 0xfdf82200 0x0 0x20>; 1695 }; 1696 1697 dfi: dfi@fe060000 { 1698 reg = <0x00 0xfe060000 0x00 0x10000>; 1699 compatible = "rockchip,rk3588-dfi"; 1700 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, 1701 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, 1702 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, 1703 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1704 rockchip,pmu = <&pmu1grf>; 1705 }; 1706 1707 pcie2x1l1: pcie@fe180000 { 1708 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1709 bus-range = <0x30 0x3f>; 1710 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1711 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1712 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 1713 clock-names = "aclk_mst", "aclk_slv", 1714 "aclk_dbi", "pclk", 1715 "aux", "pipe"; 1716 device_type = "pci"; 1717 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 1718 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 1719 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 1720 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 1721 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; 1722 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1723 #interrupt-cells = <1>; 1724 interrupt-map-mask = <0 0 0 7>; 1725 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1726 <0 0 0 2 &pcie2x1l1_intc 1>, 1727 <0 0 0 3 &pcie2x1l1_intc 2>, 1728 <0 0 0 4 &pcie2x1l1_intc 3>; 1729 linux,pci-domain = <3>; 1730 max-link-speed = <2>; 1731 msi-map = <0x3000 &its0 0x3000 0x1000>; 1732 iommu-map = <0x3000 &mmu600_pcie 0x3000 0x1000>; 1733 num-lanes = <1>; 1734 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1735 phy-names = "pcie-phy"; 1736 power-domains = <&power RK3588_PD_PCIE>; 1737 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, 1738 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, 1739 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; 1740 reg = <0xa 0x40c00000 0x0 0x00400000>, 1741 <0x0 0xfe180000 0x0 0x00010000>, 1742 <0x0 0xf3000000 0x0 0x00100000>; 1743 reg-names = "dbi", "apb", "config"; 1744 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 1745 reset-names = "pwr", "pipe"; 1746 #address-cells = <3>; 1747 #size-cells = <2>; 1748 status = "disabled"; 1749 1750 pcie2x1l1_intc: legacy-interrupt-controller { 1751 interrupt-controller; 1752 #address-cells = <0>; 1753 #interrupt-cells = <1>; 1754 interrupt-parent = <&gic>; 1755 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; 1756 }; 1757 }; 1758 1759 pcie2x1l2: pcie@fe190000 { 1760 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 1761 bus-range = <0x40 0x4f>; 1762 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1763 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1764 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 1765 clock-names = "aclk_mst", "aclk_slv", 1766 "aclk_dbi", "pclk", 1767 "aux", "pipe"; 1768 device_type = "pci"; 1769 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, 1770 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, 1771 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, 1772 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 1773 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; 1774 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1775 #interrupt-cells = <1>; 1776 interrupt-map-mask = <0 0 0 7>; 1777 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1778 <0 0 0 2 &pcie2x1l2_intc 1>, 1779 <0 0 0 3 &pcie2x1l2_intc 2>, 1780 <0 0 0 4 &pcie2x1l2_intc 3>; 1781 linux,pci-domain = <4>; 1782 max-link-speed = <2>; 1783 msi-map = <0x4000 &its0 0x4000 0x1000>; 1784 iommu-map = <0x4000 &mmu600_pcie 0x4000 0x1000>; 1785 num-lanes = <1>; 1786 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1787 phy-names = "pcie-phy"; 1788 power-domains = <&power RK3588_PD_PCIE>; 1789 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1790 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, 1791 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; 1792 reg = <0xa 0x41000000 0x0 0x00400000>, 1793 <0x0 0xfe190000 0x0 0x00010000>, 1794 <0x0 0xf4000000 0x0 0x00100000>; 1795 reg-names = "dbi", "apb", "config"; 1796 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 1797 reset-names = "pwr", "pipe"; 1798 #address-cells = <3>; 1799 #size-cells = <2>; 1800 status = "disabled"; 1801 1802 pcie2x1l2_intc: legacy-interrupt-controller { 1803 interrupt-controller; 1804 #address-cells = <0>; 1805 #interrupt-cells = <1>; 1806 interrupt-parent = <&gic>; 1807 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; 1808 }; 1809 }; 1810 1811 gmac1: ethernet@fe1c0000 { 1812 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1813 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1814 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, 1815 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 1816 interrupt-names = "macirq", "eth_wake_irq"; 1817 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 1818 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1819 <&cru CLK_GMAC1_PTP_REF>; 1820 clock-names = "stmmaceth", "clk_mac_ref", 1821 "pclk_mac", "aclk_mac", 1822 "ptp_ref"; 1823 power-domains = <&power RK3588_PD_GMAC>; 1824 resets = <&cru SRST_A_GMAC1>; 1825 reset-names = "stmmaceth"; 1826 rockchip,grf = <&sys_grf>; 1827 rockchip,php-grf = <&php_grf>; 1828 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1829 snps,mixed-burst; 1830 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1831 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1832 snps,tso; 1833 status = "disabled"; 1834 1835 mdio1: mdio { 1836 compatible = "snps,dwmac-mdio"; 1837 #address-cells = <0x1>; 1838 #size-cells = <0x0>; 1839 }; 1840 1841 gmac1_stmmac_axi_setup: stmmac-axi-config { 1842 snps,blen = <0 0 0 0 16 8 4>; 1843 snps,wr_osr_lmt = <4>; 1844 snps,rd_osr_lmt = <8>; 1845 }; 1846 1847 gmac1_mtl_rx_setup: rx-queues-config { 1848 snps,rx-queues-to-use = <2>; 1849 queue0 {}; 1850 queue1 {}; 1851 }; 1852 1853 gmac1_mtl_tx_setup: tx-queues-config { 1854 snps,tx-queues-to-use = <2>; 1855 queue0 {}; 1856 queue1 {}; 1857 }; 1858 }; 1859 1860 sata0: sata@fe210000 { 1861 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1862 reg = <0 0xfe210000 0 0x1000>; 1863 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; 1864 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1865 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 1866 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 1867 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1868 ports-implemented = <0x1>; 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 status = "disabled"; 1872 1873 sata-port@0 { 1874 reg = <0>; 1875 hba-port-cap = <HBA_PORT_FBSCP>; 1876 phys = <&combphy0_ps PHY_TYPE_SATA>; 1877 phy-names = "sata-phy"; 1878 snps,rx-ts-max = <32>; 1879 snps,tx-ts-max = <32>; 1880 }; 1881 }; 1882 1883 sata2: sata@fe230000 { 1884 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 1885 reg = <0 0xfe230000 0 0x1000>; 1886 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; 1887 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1888 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 1889 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 1890 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 1891 ports-implemented = <0x1>; 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 status = "disabled"; 1895 1896 sata-port@0 { 1897 reg = <0>; 1898 hba-port-cap = <HBA_PORT_FBSCP>; 1899 phys = <&combphy2_psu PHY_TYPE_SATA>; 1900 phy-names = "sata-phy"; 1901 snps,rx-ts-max = <32>; 1902 snps,tx-ts-max = <32>; 1903 }; 1904 }; 1905 1906 sfc: spi@fe2b0000 { 1907 compatible = "rockchip,sfc"; 1908 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1909 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; 1910 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1911 clock-names = "clk_sfc", "hclk_sfc"; 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 status = "disabled"; 1915 }; 1916 1917 sdmmc: mmc@fe2c0000 { 1918 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1919 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1920 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; 1921 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 1922 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1923 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1924 fifo-depth = <0x100>; 1925 max-frequency = <200000000>; 1926 pinctrl-names = "default"; 1927 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1928 power-domains = <&power RK3588_PD_SDMMC>; 1929 status = "disabled"; 1930 }; 1931 1932 sdio: mmc@fe2d0000 { 1933 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1934 reg = <0x00 0xfe2d0000 0x00 0x4000>; 1935 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; 1936 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1937 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1938 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1939 fifo-depth = <0x100>; 1940 max-frequency = <200000000>; 1941 pinctrl-names = "default"; 1942 pinctrl-0 = <&sdiom1_pins>; 1943 power-domains = <&power RK3588_PD_SDIO>; 1944 status = "disabled"; 1945 }; 1946 1947 sdhci: mmc@fe2e0000 { 1948 compatible = "rockchip,rk3588-dwcmshc"; 1949 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1950 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 1951 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 1952 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1953 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1954 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1955 <&cru TMCLK_EMMC>; 1956 clock-names = "core", "bus", "axi", "block", "timer"; 1957 max-frequency = <200000000>; 1958 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1959 <&emmc_cmd>, <&emmc_data_strobe>; 1960 pinctrl-names = "default"; 1961 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1962 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1963 <&cru SRST_T_EMMC>; 1964 reset-names = "core", "bus", "axi", "block", "timer"; 1965 status = "disabled"; 1966 }; 1967 1968 rng@fe378000 { 1969 compatible = "rockchip,rk3588-rng"; 1970 reg = <0x0 0xfe378000 0x0 0x200>; 1971 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>; 1972 clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; 1973 resets = <&scmi_reset 48>; 1974 }; 1975 1976 i2s0_8ch: i2s@fe470000 { 1977 compatible = "rockchip,rk3588-i2s-tdm"; 1978 reg = <0x0 0xfe470000 0x0 0x1000>; 1979 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; 1980 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1981 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1982 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1983 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 1984 dmas = <&dmac0 0>, <&dmac0 1>; 1985 dma-names = "tx", "rx"; 1986 power-domains = <&power RK3588_PD_AUDIO>; 1987 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1988 reset-names = "tx-m", "rx-m"; 1989 rockchip,trcm-sync-tx-only; 1990 pinctrl-names = "default"; 1991 pinctrl-0 = <&i2s0_lrck 1992 &i2s0_sclk 1993 &i2s0_sdi0 1994 &i2s0_sdi1 1995 &i2s0_sdi2 1996 &i2s0_sdi3 1997 &i2s0_sdo0 1998 &i2s0_sdo1 1999 &i2s0_sdo2 2000 &i2s0_sdo3>; 2001 #sound-dai-cells = <0>; 2002 status = "disabled"; 2003 }; 2004 2005 i2s1_8ch: i2s@fe480000 { 2006 compatible = "rockchip,rk3588-i2s-tdm"; 2007 reg = <0x0 0xfe480000 0x0 0x1000>; 2008 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; 2009 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 2010 clock-names = "mclk_tx", "mclk_rx", "hclk"; 2011 dmas = <&dmac0 2>, <&dmac0 3>; 2012 dma-names = "tx", "rx"; 2013 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 2014 reset-names = "tx-m", "rx-m"; 2015 rockchip,trcm-sync-tx-only; 2016 pinctrl-names = "default"; 2017 pinctrl-0 = <&i2s1m0_lrck 2018 &i2s1m0_sclk 2019 &i2s1m0_sdi0 2020 &i2s1m0_sdi1 2021 &i2s1m0_sdi2 2022 &i2s1m0_sdi3 2023 &i2s1m0_sdo0 2024 &i2s1m0_sdo1 2025 &i2s1m0_sdo2 2026 &i2s1m0_sdo3>; 2027 #sound-dai-cells = <0>; 2028 status = "disabled"; 2029 }; 2030 2031 i2s2_2ch: i2s@fe490000 { 2032 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2033 reg = <0x0 0xfe490000 0x0 0x1000>; 2034 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; 2035 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 2036 clock-names = "i2s_clk", "i2s_hclk"; 2037 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 2038 assigned-clock-parents = <&cru PLL_AUPLL>; 2039 dmas = <&dmac1 0>, <&dmac1 1>; 2040 dma-names = "tx", "rx"; 2041 power-domains = <&power RK3588_PD_AUDIO>; 2042 pinctrl-names = "default"; 2043 pinctrl-0 = <&i2s2m1_lrck 2044 &i2s2m1_sclk 2045 &i2s2m1_sdi 2046 &i2s2m1_sdo>; 2047 #sound-dai-cells = <0>; 2048 status = "disabled"; 2049 }; 2050 2051 i2s3_2ch: i2s@fe4a0000 { 2052 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 2053 reg = <0x0 0xfe4a0000 0x0 0x1000>; 2054 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; 2055 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 2056 clock-names = "i2s_clk", "i2s_hclk"; 2057 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 2058 assigned-clock-parents = <&cru PLL_AUPLL>; 2059 dmas = <&dmac1 2>, <&dmac1 3>; 2060 dma-names = "tx", "rx"; 2061 power-domains = <&power RK3588_PD_AUDIO>; 2062 pinctrl-names = "default"; 2063 pinctrl-0 = <&i2s3_lrck 2064 &i2s3_sclk 2065 &i2s3_sdi 2066 &i2s3_sdo>; 2067 #sound-dai-cells = <0>; 2068 status = "disabled"; 2069 }; 2070 2071 spdif_tx0: spdif-tx@fe4e0000 { 2072 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2073 reg = <0x0 0xfe4e0000 0x0 0x1000>; 2074 assigned-clock-parents = <&cru PLL_AUPLL>; 2075 assigned-clocks = <&cru CLK_SPDIF0_SRC>; 2076 clock-names = "mclk", "hclk"; 2077 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 2078 dma-names = "tx"; 2079 dmas = <&dmac0 5>; 2080 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 2081 pinctrl-0 = <&spdif0m0_tx>; 2082 pinctrl-names = "default"; 2083 power-domains = <&power RK3588_PD_AUDIO>; 2084 #sound-dai-cells = <0>; 2085 status = "disabled"; 2086 }; 2087 2088 spdif_tx1: spdif-tx@fe4f0000 { 2089 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 2090 reg = <0x0 0xfe4f0000 0x0 0x1000>; 2091 assigned-clock-parents = <&cru PLL_AUPLL>; 2092 assigned-clocks = <&cru CLK_SPDIF1_SRC>; 2093 clock-names = "mclk", "hclk"; 2094 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 2095 dma-names = "tx"; 2096 dmas = <&dmac1 5>; 2097 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 2098 pinctrl-0 = <&spdif1m0_tx>; 2099 pinctrl-names = "default"; 2100 power-domains = <&power RK3588_PD_AUDIO>; 2101 #sound-dai-cells = <0>; 2102 status = "disabled"; 2103 }; 2104 2105 gic: interrupt-controller@fe600000 { 2106 compatible = "arm,gic-v3"; 2107 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 2108 <0x0 0xfe680000 0 0x100000>; /* GICR */ 2109 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2110 interrupt-controller; 2111 dma-noncoherent; 2112 mbi-alias = <0x0 0xfe610000>; 2113 mbi-ranges = <424 56>; 2114 msi-controller; 2115 ranges; 2116 #address-cells = <2>; 2117 #interrupt-cells = <4>; 2118 #size-cells = <2>; 2119 2120 its0: msi-controller@fe640000 { 2121 compatible = "arm,gic-v3-its"; 2122 reg = <0x0 0xfe640000 0x0 0x20000>; 2123 dma-noncoherent; 2124 msi-controller; 2125 #msi-cells = <1>; 2126 }; 2127 2128 its1: msi-controller@fe660000 { 2129 compatible = "arm,gic-v3-its"; 2130 reg = <0x0 0xfe660000 0x0 0x20000>; 2131 dma-noncoherent; 2132 msi-controller; 2133 #msi-cells = <1>; 2134 }; 2135 2136 ppi-partitions { 2137 ppi_partition0: interrupt-partition-0 { 2138 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 2139 }; 2140 2141 ppi_partition1: interrupt-partition-1 { 2142 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; 2143 }; 2144 }; 2145 }; 2146 2147 dmac0: dma-controller@fea10000 { 2148 compatible = "arm,pl330", "arm,primecell"; 2149 reg = <0x0 0xfea10000 0x0 0x4000>; 2150 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, 2151 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; 2152 arm,pl330-periph-burst; 2153 clocks = <&cru ACLK_DMAC0>; 2154 clock-names = "apb_pclk"; 2155 #dma-cells = <1>; 2156 }; 2157 2158 dmac1: dma-controller@fea30000 { 2159 compatible = "arm,pl330", "arm,primecell"; 2160 reg = <0x0 0xfea30000 0x0 0x4000>; 2161 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, 2162 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; 2163 arm,pl330-periph-burst; 2164 clocks = <&cru ACLK_DMAC1>; 2165 clock-names = "apb_pclk"; 2166 #dma-cells = <1>; 2167 }; 2168 2169 i2c1: i2c@fea90000 { 2170 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2171 reg = <0x0 0xfea90000 0x0 0x1000>; 2172 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 2173 clock-names = "i2c", "pclk"; 2174 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; 2175 pinctrl-0 = <&i2c1m0_xfer>; 2176 pinctrl-names = "default"; 2177 #address-cells = <1>; 2178 #size-cells = <0>; 2179 status = "disabled"; 2180 }; 2181 2182 i2c2: i2c@feaa0000 { 2183 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2184 reg = <0x0 0xfeaa0000 0x0 0x1000>; 2185 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 2186 clock-names = "i2c", "pclk"; 2187 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; 2188 pinctrl-0 = <&i2c2m0_xfer>; 2189 pinctrl-names = "default"; 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 status = "disabled"; 2193 }; 2194 2195 i2c3: i2c@feab0000 { 2196 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2197 reg = <0x0 0xfeab0000 0x0 0x1000>; 2198 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 2199 clock-names = "i2c", "pclk"; 2200 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; 2201 pinctrl-0 = <&i2c3m0_xfer>; 2202 pinctrl-names = "default"; 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 status = "disabled"; 2206 }; 2207 2208 i2c4: i2c@feac0000 { 2209 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2210 reg = <0x0 0xfeac0000 0x0 0x1000>; 2211 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 2212 clock-names = "i2c", "pclk"; 2213 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; 2214 pinctrl-0 = <&i2c4m0_xfer>; 2215 pinctrl-names = "default"; 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 status = "disabled"; 2219 }; 2220 2221 i2c5: i2c@fead0000 { 2222 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2223 reg = <0x0 0xfead0000 0x0 0x1000>; 2224 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 2225 clock-names = "i2c", "pclk"; 2226 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; 2227 pinctrl-0 = <&i2c5m0_xfer>; 2228 pinctrl-names = "default"; 2229 #address-cells = <1>; 2230 #size-cells = <0>; 2231 status = "disabled"; 2232 }; 2233 2234 timer0: timer@feae0000 { 2235 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 2236 reg = <0x0 0xfeae0000 0x0 0x20>; 2237 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 2238 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 2239 clock-names = "pclk", "timer"; 2240 }; 2241 2242 wdt: watchdog@feaf0000 { 2243 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; 2244 reg = <0x0 0xfeaf0000 0x0 0x100>; 2245 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 2246 clock-names = "tclk", "pclk"; 2247 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; 2248 }; 2249 2250 spi0: spi@feb00000 { 2251 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2252 reg = <0x0 0xfeb00000 0x0 0x1000>; 2253 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; 2254 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 2255 clock-names = "spiclk", "apb_pclk"; 2256 dmas = <&dmac0 14>, <&dmac0 15>; 2257 dma-names = "tx", "rx"; 2258 num-cs = <2>; 2259 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 2260 pinctrl-names = "default"; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 status = "disabled"; 2264 }; 2265 2266 spi1: spi@feb10000 { 2267 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2268 reg = <0x0 0xfeb10000 0x0 0x1000>; 2269 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; 2270 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 2271 clock-names = "spiclk", "apb_pclk"; 2272 dmas = <&dmac0 16>, <&dmac0 17>; 2273 dma-names = "tx", "rx"; 2274 num-cs = <2>; 2275 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 2276 pinctrl-names = "default"; 2277 #address-cells = <1>; 2278 #size-cells = <0>; 2279 status = "disabled"; 2280 }; 2281 2282 spi2: spi@feb20000 { 2283 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2284 reg = <0x0 0xfeb20000 0x0 0x1000>; 2285 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; 2286 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 2287 clock-names = "spiclk", "apb_pclk"; 2288 dmas = <&dmac1 15>, <&dmac1 16>; 2289 dma-names = "tx", "rx"; 2290 num-cs = <2>; 2291 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 2292 pinctrl-names = "default"; 2293 #address-cells = <1>; 2294 #size-cells = <0>; 2295 status = "disabled"; 2296 }; 2297 2298 spi3: spi@feb30000 { 2299 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2300 reg = <0x0 0xfeb30000 0x0 0x1000>; 2301 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; 2302 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 2303 clock-names = "spiclk", "apb_pclk"; 2304 dmas = <&dmac1 17>, <&dmac1 18>; 2305 dma-names = "tx", "rx"; 2306 num-cs = <2>; 2307 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 2308 pinctrl-names = "default"; 2309 #address-cells = <1>; 2310 #size-cells = <0>; 2311 status = "disabled"; 2312 }; 2313 2314 uart1: serial@feb40000 { 2315 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2316 reg = <0x0 0xfeb40000 0x0 0x100>; 2317 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; 2318 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 2319 clock-names = "baudclk", "apb_pclk"; 2320 dmas = <&dmac0 8>, <&dmac0 9>; 2321 dma-names = "tx", "rx"; 2322 pinctrl-0 = <&uart1m1_xfer>; 2323 pinctrl-names = "default"; 2324 reg-io-width = <4>; 2325 reg-shift = <2>; 2326 status = "disabled"; 2327 }; 2328 2329 uart2: serial@feb50000 { 2330 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2331 reg = <0x0 0xfeb50000 0x0 0x100>; 2332 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; 2333 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 2334 clock-names = "baudclk", "apb_pclk"; 2335 dmas = <&dmac0 10>, <&dmac0 11>; 2336 dma-names = "tx", "rx"; 2337 pinctrl-0 = <&uart2m1_xfer>; 2338 pinctrl-names = "default"; 2339 reg-io-width = <4>; 2340 reg-shift = <2>; 2341 status = "disabled"; 2342 }; 2343 2344 uart3: serial@feb60000 { 2345 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2346 reg = <0x0 0xfeb60000 0x0 0x100>; 2347 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; 2348 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 2349 clock-names = "baudclk", "apb_pclk"; 2350 dmas = <&dmac0 12>, <&dmac0 13>; 2351 dma-names = "tx", "rx"; 2352 pinctrl-0 = <&uart3m1_xfer>; 2353 pinctrl-names = "default"; 2354 reg-io-width = <4>; 2355 reg-shift = <2>; 2356 status = "disabled"; 2357 }; 2358 2359 uart4: serial@feb70000 { 2360 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2361 reg = <0x0 0xfeb70000 0x0 0x100>; 2362 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; 2363 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 2364 clock-names = "baudclk", "apb_pclk"; 2365 dmas = <&dmac1 9>, <&dmac1 10>; 2366 dma-names = "tx", "rx"; 2367 pinctrl-0 = <&uart4m1_xfer>; 2368 pinctrl-names = "default"; 2369 reg-io-width = <4>; 2370 reg-shift = <2>; 2371 status = "disabled"; 2372 }; 2373 2374 uart5: serial@feb80000 { 2375 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2376 reg = <0x0 0xfeb80000 0x0 0x100>; 2377 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; 2378 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 2379 clock-names = "baudclk", "apb_pclk"; 2380 dmas = <&dmac1 11>, <&dmac1 12>; 2381 dma-names = "tx", "rx"; 2382 pinctrl-0 = <&uart5m1_xfer>; 2383 pinctrl-names = "default"; 2384 reg-io-width = <4>; 2385 reg-shift = <2>; 2386 status = "disabled"; 2387 }; 2388 2389 uart6: serial@feb90000 { 2390 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2391 reg = <0x0 0xfeb90000 0x0 0x100>; 2392 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; 2393 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 2394 clock-names = "baudclk", "apb_pclk"; 2395 dmas = <&dmac1 13>, <&dmac1 14>; 2396 dma-names = "tx", "rx"; 2397 pinctrl-0 = <&uart6m1_xfer>; 2398 pinctrl-names = "default"; 2399 reg-io-width = <4>; 2400 reg-shift = <2>; 2401 status = "disabled"; 2402 }; 2403 2404 uart7: serial@feba0000 { 2405 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2406 reg = <0x0 0xfeba0000 0x0 0x100>; 2407 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; 2408 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 2409 clock-names = "baudclk", "apb_pclk"; 2410 dmas = <&dmac2 7>, <&dmac2 8>; 2411 dma-names = "tx", "rx"; 2412 pinctrl-0 = <&uart7m1_xfer>; 2413 pinctrl-names = "default"; 2414 reg-io-width = <4>; 2415 reg-shift = <2>; 2416 status = "disabled"; 2417 }; 2418 2419 uart8: serial@febb0000 { 2420 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2421 reg = <0x0 0xfebb0000 0x0 0x100>; 2422 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; 2423 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 2424 clock-names = "baudclk", "apb_pclk"; 2425 dmas = <&dmac2 9>, <&dmac2 10>; 2426 dma-names = "tx", "rx"; 2427 pinctrl-0 = <&uart8m1_xfer>; 2428 pinctrl-names = "default"; 2429 reg-io-width = <4>; 2430 reg-shift = <2>; 2431 status = "disabled"; 2432 }; 2433 2434 uart9: serial@febc0000 { 2435 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2436 reg = <0x0 0xfebc0000 0x0 0x100>; 2437 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; 2438 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 2439 clock-names = "baudclk", "apb_pclk"; 2440 dmas = <&dmac2 11>, <&dmac2 12>; 2441 dma-names = "tx", "rx"; 2442 pinctrl-0 = <&uart9m1_xfer>; 2443 pinctrl-names = "default"; 2444 reg-io-width = <4>; 2445 reg-shift = <2>; 2446 status = "disabled"; 2447 }; 2448 2449 pwm4: pwm@febd0000 { 2450 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2451 reg = <0x0 0xfebd0000 0x0 0x10>; 2452 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2453 clock-names = "pwm", "pclk"; 2454 pinctrl-0 = <&pwm4m0_pins>; 2455 pinctrl-names = "default"; 2456 #pwm-cells = <3>; 2457 status = "disabled"; 2458 }; 2459 2460 pwm5: pwm@febd0010 { 2461 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2462 reg = <0x0 0xfebd0010 0x0 0x10>; 2463 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2464 clock-names = "pwm", "pclk"; 2465 pinctrl-0 = <&pwm5m0_pins>; 2466 pinctrl-names = "default"; 2467 #pwm-cells = <3>; 2468 status = "disabled"; 2469 }; 2470 2471 pwm6: pwm@febd0020 { 2472 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2473 reg = <0x0 0xfebd0020 0x0 0x10>; 2474 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2475 clock-names = "pwm", "pclk"; 2476 pinctrl-0 = <&pwm6m0_pins>; 2477 pinctrl-names = "default"; 2478 #pwm-cells = <3>; 2479 status = "disabled"; 2480 }; 2481 2482 pwm7: pwm@febd0030 { 2483 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2484 reg = <0x0 0xfebd0030 0x0 0x10>; 2485 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 2486 clock-names = "pwm", "pclk"; 2487 pinctrl-0 = <&pwm7m0_pins>; 2488 pinctrl-names = "default"; 2489 #pwm-cells = <3>; 2490 status = "disabled"; 2491 }; 2492 2493 pwm8: pwm@febe0000 { 2494 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2495 reg = <0x0 0xfebe0000 0x0 0x10>; 2496 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2497 clock-names = "pwm", "pclk"; 2498 pinctrl-0 = <&pwm8m0_pins>; 2499 pinctrl-names = "default"; 2500 #pwm-cells = <3>; 2501 status = "disabled"; 2502 }; 2503 2504 pwm9: pwm@febe0010 { 2505 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2506 reg = <0x0 0xfebe0010 0x0 0x10>; 2507 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2508 clock-names = "pwm", "pclk"; 2509 pinctrl-0 = <&pwm9m0_pins>; 2510 pinctrl-names = "default"; 2511 #pwm-cells = <3>; 2512 status = "disabled"; 2513 }; 2514 2515 pwm10: pwm@febe0020 { 2516 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2517 reg = <0x0 0xfebe0020 0x0 0x10>; 2518 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2519 clock-names = "pwm", "pclk"; 2520 pinctrl-0 = <&pwm10m0_pins>; 2521 pinctrl-names = "default"; 2522 #pwm-cells = <3>; 2523 status = "disabled"; 2524 }; 2525 2526 pwm11: pwm@febe0030 { 2527 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2528 reg = <0x0 0xfebe0030 0x0 0x10>; 2529 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2530 clock-names = "pwm", "pclk"; 2531 pinctrl-0 = <&pwm11m0_pins>; 2532 pinctrl-names = "default"; 2533 #pwm-cells = <3>; 2534 status = "disabled"; 2535 }; 2536 2537 pwm12: pwm@febf0000 { 2538 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2539 reg = <0x0 0xfebf0000 0x0 0x10>; 2540 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2541 clock-names = "pwm", "pclk"; 2542 pinctrl-0 = <&pwm12m0_pins>; 2543 pinctrl-names = "default"; 2544 #pwm-cells = <3>; 2545 status = "disabled"; 2546 }; 2547 2548 pwm13: pwm@febf0010 { 2549 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2550 reg = <0x0 0xfebf0010 0x0 0x10>; 2551 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2552 clock-names = "pwm", "pclk"; 2553 pinctrl-0 = <&pwm13m0_pins>; 2554 pinctrl-names = "default"; 2555 #pwm-cells = <3>; 2556 status = "disabled"; 2557 }; 2558 2559 pwm14: pwm@febf0020 { 2560 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2561 reg = <0x0 0xfebf0020 0x0 0x10>; 2562 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2563 clock-names = "pwm", "pclk"; 2564 pinctrl-0 = <&pwm14m0_pins>; 2565 pinctrl-names = "default"; 2566 #pwm-cells = <3>; 2567 status = "disabled"; 2568 }; 2569 2570 pwm15: pwm@febf0030 { 2571 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2572 reg = <0x0 0xfebf0030 0x0 0x10>; 2573 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2574 clock-names = "pwm", "pclk"; 2575 pinctrl-0 = <&pwm15m0_pins>; 2576 pinctrl-names = "default"; 2577 #pwm-cells = <3>; 2578 status = "disabled"; 2579 }; 2580 2581 thermal_zones: thermal-zones { 2582 /* sensor near the center of the SoC */ 2583 package_thermal: package-thermal { 2584 polling-delay-passive = <0>; 2585 polling-delay = <0>; 2586 thermal-sensors = <&tsadc 0>; 2587 2588 trips { 2589 package_crit: package-crit { 2590 temperature = <115000>; 2591 hysteresis = <0>; 2592 type = "critical"; 2593 }; 2594 }; 2595 }; 2596 2597 /* sensor between A76 cores 0 and 1 */ 2598 bigcore0_thermal: bigcore0-thermal { 2599 polling-delay-passive = <100>; 2600 polling-delay = <0>; 2601 thermal-sensors = <&tsadc 1>; 2602 2603 trips { 2604 bigcore0_alert: bigcore0-alert { 2605 temperature = <85000>; 2606 hysteresis = <2000>; 2607 type = "passive"; 2608 }; 2609 2610 bigcore0_crit: bigcore0-crit { 2611 temperature = <115000>; 2612 hysteresis = <0>; 2613 type = "critical"; 2614 }; 2615 }; 2616 2617 cooling-maps { 2618 map0 { 2619 trip = <&bigcore0_alert>; 2620 cooling-device = 2621 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2622 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2623 }; 2624 }; 2625 }; 2626 2627 /* sensor between A76 cores 2 and 3 */ 2628 bigcore2_thermal: bigcore2-thermal { 2629 polling-delay-passive = <100>; 2630 polling-delay = <0>; 2631 thermal-sensors = <&tsadc 2>; 2632 2633 trips { 2634 bigcore2_alert: bigcore2-alert { 2635 temperature = <85000>; 2636 hysteresis = <2000>; 2637 type = "passive"; 2638 }; 2639 2640 bigcore2_crit: bigcore2-crit { 2641 temperature = <115000>; 2642 hysteresis = <0>; 2643 type = "critical"; 2644 }; 2645 }; 2646 2647 cooling-maps { 2648 map0 { 2649 trip = <&bigcore2_alert>; 2650 cooling-device = 2651 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2652 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2653 }; 2654 }; 2655 }; 2656 2657 /* sensor between the four A55 cores */ 2658 little_core_thermal: littlecore-thermal { 2659 polling-delay-passive = <100>; 2660 polling-delay = <0>; 2661 thermal-sensors = <&tsadc 3>; 2662 2663 trips { 2664 littlecore_alert: littlecore-alert { 2665 temperature = <85000>; 2666 hysteresis = <2000>; 2667 type = "passive"; 2668 }; 2669 2670 littlecore_crit: littlecore-crit { 2671 temperature = <115000>; 2672 hysteresis = <0>; 2673 type = "critical"; 2674 }; 2675 }; 2676 2677 cooling-maps { 2678 map0 { 2679 trip = <&littlecore_alert>; 2680 cooling-device = 2681 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2682 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2683 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2684 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2685 }; 2686 }; 2687 }; 2688 2689 /* sensor near the PD_CENTER power domain */ 2690 center_thermal: center-thermal { 2691 polling-delay-passive = <0>; 2692 polling-delay = <0>; 2693 thermal-sensors = <&tsadc 4>; 2694 2695 trips { 2696 center_crit: center-crit { 2697 temperature = <115000>; 2698 hysteresis = <0>; 2699 type = "critical"; 2700 }; 2701 }; 2702 }; 2703 2704 gpu_thermal: gpu-thermal { 2705 polling-delay-passive = <100>; 2706 polling-delay = <0>; 2707 thermal-sensors = <&tsadc 5>; 2708 2709 trips { 2710 gpu_alert: gpu-alert { 2711 temperature = <85000>; 2712 hysteresis = <2000>; 2713 type = "passive"; 2714 }; 2715 2716 gpu_crit: gpu-crit { 2717 temperature = <115000>; 2718 hysteresis = <0>; 2719 type = "critical"; 2720 }; 2721 }; 2722 2723 cooling-maps { 2724 map0 { 2725 trip = <&gpu_alert>; 2726 cooling-device = 2727 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2728 }; 2729 }; 2730 }; 2731 2732 npu_thermal: npu-thermal { 2733 polling-delay-passive = <0>; 2734 polling-delay = <0>; 2735 thermal-sensors = <&tsadc 6>; 2736 2737 trips { 2738 npu_crit: npu-crit { 2739 temperature = <115000>; 2740 hysteresis = <0>; 2741 type = "critical"; 2742 }; 2743 }; 2744 }; 2745 }; 2746 2747 tsadc: tsadc@fec00000 { 2748 compatible = "rockchip,rk3588-tsadc"; 2749 reg = <0x0 0xfec00000 0x0 0x400>; 2750 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; 2751 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2752 clock-names = "tsadc", "apb_pclk"; 2753 assigned-clocks = <&cru CLK_TSADC>; 2754 assigned-clock-rates = <2000000>; 2755 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; 2756 reset-names = "tsadc-apb", "tsadc"; 2757 rockchip,hw-tshut-temp = <120000>; 2758 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 2759 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2760 pinctrl-0 = <&tsadc_shut_org>; 2761 pinctrl-1 = <&tsadc_gpio_func>; 2762 pinctrl-names = "default", "sleep"; 2763 #thermal-sensor-cells = <1>; 2764 status = "disabled"; 2765 }; 2766 2767 saradc: adc@fec10000 { 2768 compatible = "rockchip,rk3588-saradc"; 2769 reg = <0x0 0xfec10000 0x0 0x10000>; 2770 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; 2771 #io-channel-cells = <1>; 2772 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2773 clock-names = "saradc", "apb_pclk"; 2774 resets = <&cru SRST_P_SARADC>; 2775 reset-names = "saradc-apb"; 2776 status = "disabled"; 2777 }; 2778 2779 i2c6: i2c@fec80000 { 2780 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2781 reg = <0x0 0xfec80000 0x0 0x1000>; 2782 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2783 clock-names = "i2c", "pclk"; 2784 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; 2785 pinctrl-0 = <&i2c6m0_xfer>; 2786 pinctrl-names = "default"; 2787 #address-cells = <1>; 2788 #size-cells = <0>; 2789 status = "disabled"; 2790 }; 2791 2792 i2c7: i2c@fec90000 { 2793 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2794 reg = <0x0 0xfec90000 0x0 0x1000>; 2795 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2796 clock-names = "i2c", "pclk"; 2797 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 2798 pinctrl-0 = <&i2c7m0_xfer>; 2799 pinctrl-names = "default"; 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 status = "disabled"; 2803 }; 2804 2805 i2c8: i2c@feca0000 { 2806 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2807 reg = <0x0 0xfeca0000 0x0 0x1000>; 2808 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2809 clock-names = "i2c", "pclk"; 2810 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; 2811 pinctrl-0 = <&i2c8m0_xfer>; 2812 pinctrl-names = "default"; 2813 #address-cells = <1>; 2814 #size-cells = <0>; 2815 status = "disabled"; 2816 }; 2817 2818 spi4: spi@fecb0000 { 2819 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; 2820 reg = <0x0 0xfecb0000 0x0 0x1000>; 2821 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; 2822 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2823 clock-names = "spiclk", "apb_pclk"; 2824 dmas = <&dmac2 13>, <&dmac2 14>; 2825 dma-names = "tx", "rx"; 2826 num-cs = <2>; 2827 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2828 pinctrl-names = "default"; 2829 #address-cells = <1>; 2830 #size-cells = <0>; 2831 status = "disabled"; 2832 }; 2833 2834 otp: efuse@fecc0000 { 2835 compatible = "rockchip,rk3588-otp"; 2836 reg = <0x0 0xfecc0000 0x0 0x400>; 2837 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2838 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; 2839 clock-names = "otp", "apb_pclk", "phy", "arb"; 2840 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2841 <&cru SRST_OTPC_ARB>; 2842 reset-names = "otp", "apb", "arb"; 2843 #address-cells = <1>; 2844 #size-cells = <1>; 2845 2846 cpu_code: cpu-code@2 { 2847 reg = <0x02 0x2>; 2848 }; 2849 2850 otp_id: id@7 { 2851 reg = <0x07 0x10>; 2852 }; 2853 2854 cpub0_leakage: cpu-leakage@17 { 2855 reg = <0x17 0x1>; 2856 }; 2857 2858 cpub1_leakage: cpu-leakage@18 { 2859 reg = <0x18 0x1>; 2860 }; 2861 2862 cpul_leakage: cpu-leakage@19 { 2863 reg = <0x19 0x1>; 2864 }; 2865 2866 log_leakage: log-leakage@1a { 2867 reg = <0x1a 0x1>; 2868 }; 2869 2870 gpu_leakage: gpu-leakage@1b { 2871 reg = <0x1b 0x1>; 2872 }; 2873 2874 otp_cpu_version: cpu-version@1c { 2875 reg = <0x1c 0x1>; 2876 bits = <3 3>; 2877 }; 2878 2879 npu_leakage: npu-leakage@28 { 2880 reg = <0x28 0x1>; 2881 }; 2882 2883 codec_leakage: codec-leakage@29 { 2884 reg = <0x29 0x1>; 2885 }; 2886 }; 2887 2888 dmac2: dma-controller@fed10000 { 2889 compatible = "arm,pl330", "arm,primecell"; 2890 reg = <0x0 0xfed10000 0x0 0x4000>; 2891 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, 2892 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; 2893 arm,pl330-periph-burst; 2894 clocks = <&cru ACLK_DMAC2>; 2895 clock-names = "apb_pclk"; 2896 #dma-cells = <1>; 2897 }; 2898 2899 hdptxphy0: phy@fed60000 { 2900 compatible = "rockchip,rk3588-hdptx-phy"; 2901 reg = <0x0 0xfed60000 0x0 0x2000>; 2902 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2903 clock-names = "ref", "apb"; 2904 #clock-cells = <0>; 2905 #phy-cells = <0>; 2906 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2907 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2908 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2909 <&cru SRST_HDPTX0_LCPLL>; 2910 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2911 "lcpll"; 2912 rockchip,grf = <&hdptxphy0_grf>; 2913 status = "disabled"; 2914 }; 2915 2916 usbdp_phy0: phy@fed80000 { 2917 compatible = "rockchip,rk3588-usbdp-phy"; 2918 reg = <0x0 0xfed80000 0x0 0x10000>; 2919 #phy-cells = <1>; 2920 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2921 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2922 <&cru PCLK_USBDPPHY0>, 2923 <&u2phy0>; 2924 clock-names = "refclk", "immortal", "pclk", "utmi"; 2925 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2926 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2927 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2928 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2929 <&cru SRST_P_USBDPPHY0>; 2930 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2931 rockchip,u2phy-grf = <&usb2phy0_grf>; 2932 rockchip,usb-grf = <&usb_grf>; 2933 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2934 rockchip,vo-grf = <&vo0_grf>; 2935 status = "disabled"; 2936 }; 2937 2938 combphy0_ps: phy@fee00000 { 2939 compatible = "rockchip,rk3588-naneng-combphy"; 2940 reg = <0x0 0xfee00000 0x0 0x100>; 2941 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 2942 <&cru PCLK_PHP_ROOT>; 2943 clock-names = "ref", "apb", "pipe"; 2944 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2945 assigned-clock-rates = <100000000>; 2946 #phy-cells = <1>; 2947 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; 2948 reset-names = "phy", "apb"; 2949 rockchip,pipe-grf = <&php_grf>; 2950 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2951 status = "disabled"; 2952 }; 2953 2954 combphy2_psu: phy@fee20000 { 2955 compatible = "rockchip,rk3588-naneng-combphy"; 2956 reg = <0x0 0xfee20000 0x0 0x100>; 2957 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 2958 <&cru PCLK_PHP_ROOT>; 2959 clock-names = "ref", "apb", "pipe"; 2960 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2961 assigned-clock-rates = <100000000>; 2962 #phy-cells = <1>; 2963 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; 2964 reset-names = "phy", "apb"; 2965 rockchip,pipe-grf = <&php_grf>; 2966 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2967 status = "disabled"; 2968 }; 2969 2970 system_sram2: sram@ff001000 { 2971 compatible = "mmio-sram"; 2972 reg = <0x0 0xff001000 0x0 0xef000>; 2973 ranges = <0x0 0x0 0xff001000 0xef000>; 2974 #address-cells = <1>; 2975 #size-cells = <1>; 2976 }; 2977 2978 pinctrl: pinctrl { 2979 compatible = "rockchip,rk3588-pinctrl"; 2980 ranges; 2981 rockchip,grf = <&ioc>; 2982 #address-cells = <2>; 2983 #size-cells = <2>; 2984 2985 gpio0: gpio@fd8a0000 { 2986 compatible = "rockchip,gpio-bank"; 2987 reg = <0x0 0xfd8a0000 0x0 0x100>; 2988 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 2989 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2990 gpio-controller; 2991 gpio-ranges = <&pinctrl 0 0 32>; 2992 interrupt-controller; 2993 #gpio-cells = <2>; 2994 #interrupt-cells = <2>; 2995 }; 2996 2997 gpio1: gpio@fec20000 { 2998 compatible = "rockchip,gpio-bank"; 2999 reg = <0x0 0xfec20000 0x0 0x100>; 3000 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; 3001 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 3002 gpio-controller; 3003 gpio-ranges = <&pinctrl 0 32 32>; 3004 interrupt-controller; 3005 #gpio-cells = <2>; 3006 #interrupt-cells = <2>; 3007 }; 3008 3009 gpio2: gpio@fec30000 { 3010 compatible = "rockchip,gpio-bank"; 3011 reg = <0x0 0xfec30000 0x0 0x100>; 3012 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; 3013 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 3014 gpio-controller; 3015 gpio-ranges = <&pinctrl 0 64 32>; 3016 interrupt-controller; 3017 #gpio-cells = <2>; 3018 #interrupt-cells = <2>; 3019 }; 3020 3021 gpio3: gpio@fec40000 { 3022 compatible = "rockchip,gpio-bank"; 3023 reg = <0x0 0xfec40000 0x0 0x100>; 3024 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; 3025 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 3026 gpio-controller; 3027 gpio-ranges = <&pinctrl 0 96 32>; 3028 interrupt-controller; 3029 #gpio-cells = <2>; 3030 #interrupt-cells = <2>; 3031 }; 3032 3033 gpio4: gpio@fec50000 { 3034 compatible = "rockchip,gpio-bank"; 3035 reg = <0x0 0xfec50000 0x0 0x100>; 3036 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; 3037 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 3038 gpio-controller; 3039 gpio-ranges = <&pinctrl 0 128 32>; 3040 interrupt-controller; 3041 #gpio-cells = <2>; 3042 #interrupt-cells = <2>; 3043 }; 3044 }; 3045}; 3046 3047#include "rk3588-base-pinctrl.dtsi" 3048