1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rk3576-power.h> 12#include <dt-bindings/reset/rockchip,rk3576-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,rk3576"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 i2c9 = &i2c9; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 serial5 = &uart5; 39 serial6 = &uart6; 40 serial7 = &uart7; 41 serial8 = &uart8; 42 serial9 = &uart9; 43 serial10 = &uart10; 44 serial11 = &uart11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi2 = &spi2; 48 spi3 = &spi3; 49 spi4 = &spi4; 50 }; 51 52 xin32k: clock-xin32k { 53 compatible = "fixed-clock"; 54 clock-frequency = <32768>; 55 clock-output-names = "xin32k"; 56 #clock-cells = <0>; 57 }; 58 59 xin24m: clock-xin24m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <24000000>; 63 clock-output-names = "xin24m"; 64 }; 65 66 spll: clock-spll { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <702000000>; 70 clock-output-names = "spll"; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu-map { 78 cluster0 { 79 core0 { 80 cpu = <&cpu_l0>; 81 }; 82 core1 { 83 cpu = <&cpu_l1>; 84 }; 85 core2 { 86 cpu = <&cpu_l2>; 87 }; 88 core3 { 89 cpu = <&cpu_l3>; 90 }; 91 }; 92 cluster1 { 93 core0 { 94 cpu = <&cpu_b0>; 95 }; 96 core1 { 97 cpu = <&cpu_b1>; 98 }; 99 core2 { 100 cpu = <&cpu_b2>; 101 }; 102 core3 { 103 cpu = <&cpu_b3>; 104 }; 105 }; 106 }; 107 108 cpu_l0: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <485>; 114 clocks = <&scmi_clk SCMI_ARMCLK_L>; 115 operating-points-v2 = <&cluster0_opp_table>; 116 #cooling-cells = <2>; 117 dynamic-power-coefficient = <120>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 }; 120 121 cpu_l1: cpu@1 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53"; 124 reg = <0x1>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <485>; 127 clocks = <&scmi_clk SCMI_ARMCLK_L>; 128 operating-points-v2 = <&cluster0_opp_table>; 129 cpu-idle-states = <&CPU_SLEEP>; 130 }; 131 132 cpu_l2: cpu@2 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53"; 135 reg = <0x2>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <485>; 138 clocks = <&scmi_clk SCMI_ARMCLK_L>; 139 operating-points-v2 = <&cluster0_opp_table>; 140 cpu-idle-states = <&CPU_SLEEP>; 141 }; 142 143 cpu_l3: cpu@3 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x3>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <485>; 149 clocks = <&scmi_clk SCMI_ARMCLK_L>; 150 operating-points-v2 = <&cluster0_opp_table>; 151 cpu-idle-states = <&CPU_SLEEP>; 152 }; 153 154 cpu_b0: cpu@100 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a72"; 157 reg = <0x100>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 clocks = <&scmi_clk SCMI_ARMCLK_B>; 161 operating-points-v2 = <&cluster1_opp_table>; 162 #cooling-cells = <2>; 163 dynamic-power-coefficient = <320>; 164 cpu-idle-states = <&CPU_SLEEP>; 165 }; 166 167 cpu_b1: cpu@101 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a72"; 170 reg = <0x101>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <1024>; 173 clocks = <&scmi_clk SCMI_ARMCLK_B>; 174 operating-points-v2 = <&cluster1_opp_table>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 }; 177 178 cpu_b2: cpu@102 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a72"; 181 reg = <0x102>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 clocks = <&scmi_clk SCMI_ARMCLK_B>; 185 operating-points-v2 = <&cluster1_opp_table>; 186 cpu-idle-states = <&CPU_SLEEP>; 187 }; 188 189 cpu_b3: cpu@103 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a72"; 192 reg = <0x103>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 clocks = <&scmi_clk SCMI_ARMCLK_B>; 196 operating-points-v2 = <&cluster1_opp_table>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 CPU_SLEEP: cpu-sleep { 204 compatible = "arm,idle-state"; 205 arm,psci-suspend-param = <0x0010000>; 206 entry-latency-us = <120>; 207 exit-latency-us = <250>; 208 min-residency-us = <900>; 209 local-timer-stop; 210 }; 211 }; 212 }; 213 214 cluster0_opp_table: opp-table-cluster0 { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 218 opp-408000000 { 219 opp-hz = /bits/ 64 <408000000>; 220 opp-microvolt = <700000 700000 950000>; 221 clock-latency-ns = <40000>; 222 }; 223 224 opp-600000000 { 225 opp-hz = /bits/ 64 <600000000>; 226 opp-microvolt = <700000 700000 950000>; 227 clock-latency-ns = <40000>; 228 }; 229 230 opp-816000000 { 231 opp-hz = /bits/ 64 <816000000>; 232 opp-microvolt = <700000 700000 950000>; 233 clock-latency-ns = <40000>; 234 }; 235 236 opp-1008000000 { 237 opp-hz = /bits/ 64 <1008000000>; 238 opp-microvolt = <700000 700000 950000>; 239 clock-latency-ns = <40000>; 240 }; 241 242 opp-1200000000 { 243 opp-hz = /bits/ 64 <1200000000>; 244 opp-microvolt = <700000 700000 950000>; 245 clock-latency-ns = <40000>; 246 }; 247 248 opp-1416000000 { 249 opp-hz = /bits/ 64 <1416000000>; 250 opp-microvolt = <725000 725000 950000>; 251 clock-latency-ns = <40000>; 252 }; 253 254 opp-1608000000 { 255 opp-hz = /bits/ 64 <1608000000>; 256 opp-microvolt = <750000 750000 950000>; 257 clock-latency-ns = <40000>; 258 }; 259 260 opp-1800000000 { 261 opp-hz = /bits/ 64 <1800000000>; 262 opp-microvolt = <825000 825000 950000>; 263 clock-latency-ns = <40000>; 264 opp-suspend; 265 }; 266 267 opp-2016000000 { 268 opp-hz = /bits/ 64 <2016000000>; 269 opp-microvolt = <900000 900000 950000>; 270 clock-latency-ns = <40000>; 271 }; 272 273 opp-2208000000 { 274 opp-hz = /bits/ 64 <2208000000>; 275 opp-microvolt = <950000 950000 950000>; 276 clock-latency-ns = <40000>; 277 }; 278 }; 279 280 cluster1_opp_table: opp-table-cluster1 { 281 compatible = "operating-points-v2"; 282 opp-shared; 283 284 opp-408000000 { 285 opp-hz = /bits/ 64 <408000000>; 286 opp-microvolt = <700000 700000 950000>; 287 clock-latency-ns = <40000>; 288 opp-suspend; 289 }; 290 291 opp-600000000 { 292 opp-hz = /bits/ 64 <600000000>; 293 opp-microvolt = <700000 700000 950000>; 294 clock-latency-ns = <40000>; 295 }; 296 297 opp-816000000 { 298 opp-hz = /bits/ 64 <816000000>; 299 opp-microvolt = <700000 700000 950000>; 300 clock-latency-ns = <40000>; 301 }; 302 303 opp-1008000000 { 304 opp-hz = /bits/ 64 <1008000000>; 305 opp-microvolt = <700000 700000 950000>; 306 clock-latency-ns = <40000>; 307 }; 308 309 opp-1200000000 { 310 opp-hz = /bits/ 64 <1200000000>; 311 opp-microvolt = <700000 700000 950000>; 312 clock-latency-ns = <40000>; 313 }; 314 315 opp-1416000000 { 316 opp-hz = /bits/ 64 <1416000000>; 317 opp-microvolt = <712500 712500 950000>; 318 clock-latency-ns = <40000>; 319 }; 320 321 opp-1608000000 { 322 opp-hz = /bits/ 64 <1608000000>; 323 opp-microvolt = <737500 737500 950000>; 324 clock-latency-ns = <40000>; 325 }; 326 327 opp-1800000000 { 328 opp-hz = /bits/ 64 <1800000000>; 329 opp-microvolt = <800000 800000 950000>; 330 clock-latency-ns = <40000>; 331 }; 332 333 opp-2016000000 { 334 opp-hz = /bits/ 64 <2016000000>; 335 opp-microvolt = <862500 862500 950000>; 336 clock-latency-ns = <40000>; 337 }; 338 339 opp-2208000000 { 340 opp-hz = /bits/ 64 <2208000000>; 341 opp-microvolt = <925000 925000 950000>; 342 clock-latency-ns = <40000>; 343 }; 344 345 opp-2304000000 { 346 opp-hz = /bits/ 64 <2304000000>; 347 opp-microvolt = <950000 950000 950000>; 348 clock-latency-ns = <40000>; 349 }; 350 }; 351 352 gpu_opp_table: opp-table-gpu { 353 compatible = "operating-points-v2"; 354 355 opp-300000000 { 356 opp-hz = /bits/ 64 <300000000>; 357 opp-microvolt = <700000 700000 850000>; 358 }; 359 360 opp-400000000 { 361 opp-hz = /bits/ 64 <400000000>; 362 opp-microvolt = <700000 700000 850000>; 363 }; 364 365 opp-500000000 { 366 opp-hz = /bits/ 64 <500000000>; 367 opp-microvolt = <700000 700000 850000>; 368 }; 369 370 opp-600000000 { 371 opp-hz = /bits/ 64 <600000000>; 372 opp-microvolt = <700000 700000 850000>; 373 }; 374 375 opp-700000000 { 376 opp-hz = /bits/ 64 <700000000>; 377 opp-microvolt = <725000 725000 850000>; 378 }; 379 380 opp-800000000 { 381 opp-hz = /bits/ 64 <800000000>; 382 opp-microvolt = <775000 775000 850000>; 383 }; 384 385 opp-900000000 { 386 opp-hz = /bits/ 64 <900000000>; 387 opp-microvolt = <825000 825000 850000>; 388 }; 389 390 opp-950000000 { 391 opp-hz = /bits/ 64 <950000000>; 392 opp-microvolt = <850000 850000 850000>; 393 }; 394 }; 395 396 display_subsystem: display-subsystem { 397 compatible = "rockchip,display-subsystem"; 398 ports = <&vop_out>; 399 }; 400 401 firmware { 402 scmi: scmi { 403 compatible = "arm,scmi-smc"; 404 arm,smc-id = <0x82000010>; 405 shmem = <&scmi_shmem>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 409 scmi_clk: protocol@14 { 410 reg = <0x14>; 411 #clock-cells = <1>; 412 }; 413 }; 414 }; 415 416 pmu_a53: pmu-a53 { 417 compatible = "arm,cortex-a53-pmu"; 418 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 423 }; 424 425 pmu_a72: pmu-a72 { 426 compatible = "arm,cortex-a72-pmu"; 427 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 431 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 432 }; 433 434 psci { 435 compatible = "arm,psci-1.0"; 436 method = "smc"; 437 }; 438 439 timer { 440 compatible = "arm,armv8-timer"; 441 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 442 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 443 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 444 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 445 }; 446 447 soc { 448 compatible = "simple-bus"; 449 #address-cells = <2>; 450 #size-cells = <2>; 451 ranges; 452 453 usb_drd0_dwc3: usb@23000000 { 454 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 455 reg = <0x0 0x23000000 0x0 0x400000>; 456 clocks = <&cru CLK_REF_USB3OTG0>, 457 <&cru CLK_SUSPEND_USB3OTG0>, 458 <&cru ACLK_USB3OTG0>; 459 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 460 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 461 power-domains = <&power RK3576_PD_USB>; 462 resets = <&cru SRST_A_USB3OTG0>; 463 dr_mode = "otg"; 464 phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; 465 phy-names = "usb2-phy", "usb3-phy"; 466 phy_type = "utmi_wide"; 467 snps,dis_enblslpm_quirk; 468 snps,dis-u1-entry-quirk; 469 snps,dis-u2-entry-quirk; 470 snps,dis-u2-freeclk-exists-quirk; 471 snps,dis-del-phy-power-chg-quirk; 472 snps,dis-tx-ipgap-linecheck-quirk; 473 snps,parkmode-disable-hs-quirk; 474 snps,parkmode-disable-ss-quirk; 475 status = "disabled"; 476 }; 477 478 usb_drd1_dwc3: usb@23400000 { 479 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 480 reg = <0x0 0x23400000 0x0 0x400000>; 481 clocks = <&cru CLK_REF_USB3OTG1>, 482 <&cru CLK_SUSPEND_USB3OTG1>, 483 <&cru ACLK_USB3OTG1>; 484 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 485 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 486 power-domains = <&power RK3576_PD_PHP>; 487 resets = <&cru SRST_A_USB3OTG1>; 488 dr_mode = "otg"; 489 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 490 phy-names = "usb2-phy", "usb3-phy"; 491 phy_type = "utmi_wide"; 492 snps,dis_enblslpm_quirk; 493 snps,dis-u1-entry-quirk; 494 snps,dis-u2-entry-quirk; 495 snps,dis-u2-freeclk-exists-quirk; 496 snps,dis-del-phy-power-chg-quirk; 497 snps,dis-tx-ipgap-linecheck-quirk; 498 snps,dis_rxdet_inp3_quirk; 499 snps,parkmode-disable-hs-quirk; 500 snps,parkmode-disable-ss-quirk; 501 dma-coherent; 502 status = "disabled"; 503 }; 504 505 sys_grf: syscon@2600a000 { 506 compatible = "rockchip,rk3576-sys-grf", "syscon"; 507 reg = <0x0 0x2600a000 0x0 0x2000>; 508 }; 509 510 bigcore_grf: syscon@2600c000 { 511 compatible = "rockchip,rk3576-bigcore-grf", "syscon"; 512 reg = <0x0 0x2600c000 0x0 0x2000>; 513 }; 514 515 litcore_grf: syscon@2600e000 { 516 compatible = "rockchip,rk3576-litcore-grf", "syscon"; 517 reg = <0x0 0x2600e000 0x0 0x2000>; 518 }; 519 520 cci_grf: syscon@26010000 { 521 compatible = "rockchip,rk3576-cci-grf", "syscon"; 522 reg = <0x0 0x26010000 0x0 0x2000>; 523 }; 524 525 gpu_grf: syscon@26016000 { 526 compatible = "rockchip,rk3576-gpu-grf", "syscon"; 527 reg = <0x0 0x26016000 0x0 0x2000>; 528 }; 529 530 npu_grf: syscon@26018000 { 531 compatible = "rockchip,rk3576-npu-grf", "syscon"; 532 reg = <0x0 0x26018000 0x0 0x2000>; 533 }; 534 535 vo0_grf: syscon@2601a000 { 536 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 537 reg = <0x0 0x2601a000 0x0 0x2000>; 538 }; 539 540 usb_grf: syscon@2601e000 { 541 compatible = "rockchip,rk3576-usb-grf", "syscon"; 542 reg = <0x0 0x2601e000 0x0 0x1000>; 543 }; 544 545 php_grf: syscon@26020000 { 546 compatible = "rockchip,rk3576-php-grf", "syscon"; 547 reg = <0x0 0x26020000 0x0 0x2000>; 548 }; 549 550 pmu0_grf: syscon@26024000 { 551 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 552 reg = <0x0 0x26024000 0x0 0x1000>; 553 }; 554 555 pmu1_grf: syscon@26026000 { 556 compatible = "rockchip,rk3576-pmu1-grf", "syscon"; 557 reg = <0x0 0x26026000 0x0 0x1000>; 558 }; 559 560 pipe_phy0_grf: syscon@26028000 { 561 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 562 reg = <0x0 0x26028000 0x0 0x2000>; 563 }; 564 565 pipe_phy1_grf: syscon@2602a000 { 566 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 567 reg = <0x0 0x2602a000 0x0 0x2000>; 568 }; 569 570 usbdpphy_grf: syscon@2602c000 { 571 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 572 reg = <0x0 0x2602c000 0x0 0x2000>; 573 }; 574 575 usb2phy_grf: syscon@2602e000 { 576 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 577 reg = <0x0 0x2602e000 0x0 0x4000>; 578 #address-cells = <1>; 579 #size-cells = <1>; 580 581 u2phy0: usb2-phy@0 { 582 compatible = "rockchip,rk3576-usb2phy"; 583 reg = <0x0 0x10>; 584 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 585 reset-names = "phy", "apb"; 586 clocks = <&cru CLK_PHY_REF_SRC>, 587 <&cru ACLK_MMU2>, 588 <&cru ACLK_SLV_MMU2>; 589 clock-names = "phyclk", "aclk", "aclk_slv"; 590 clock-output-names = "usb480m_phy0"; 591 #clock-cells = <0>; 592 status = "disabled"; 593 594 u2phy0_otg: otg-port { 595 #phy-cells = <0>; 596 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 600 status = "disabled"; 601 }; 602 }; 603 604 u2phy1: usb2-phy@2000 { 605 compatible = "rockchip,rk3576-usb2phy"; 606 reg = <0x2000 0x10>; 607 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 608 reset-names = "phy", "apb"; 609 clocks = <&cru CLK_PHY_REF_SRC>, 610 <&cru ACLK_MMU1>, 611 <&cru ACLK_SLV_MMU1>; 612 clock-names = "phyclk", "aclk", "aclk_slv"; 613 clock-output-names = "usb480m_phy1"; 614 #clock-cells = <0>; 615 status = "disabled"; 616 617 u2phy1_otg: otg-port { 618 #phy-cells = <0>; 619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 622 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 623 status = "disabled"; 624 }; 625 }; 626 }; 627 628 hdptxphy_grf: syscon@26032000 { 629 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; 630 reg = <0x0 0x26032000 0x0 0x100>; 631 }; 632 633 vo1_grf: syscon@26036000 { 634 compatible = "rockchip,rk3576-vo1-grf", "syscon"; 635 reg = <0x0 0x26036000 0x0 0x100>; 636 clocks = <&cru PCLK_VO1_ROOT>; 637 }; 638 639 sdgmac_grf: syscon@26038000 { 640 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 641 reg = <0x0 0x26038000 0x0 0x1000>; 642 }; 643 644 ioc_grf: syscon@26040000 { 645 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 646 reg = <0x0 0x26040000 0x0 0xc000>; 647 }; 648 649 cru: clock-controller@27200000 { 650 compatible = "rockchip,rk3576-cru"; 651 reg = <0x0 0x27200000 0x0 0x50000>; 652 #clock-cells = <1>; 653 #reset-cells = <1>; 654 655 assigned-clocks = 656 <&cru CLK_AUDIO_FRAC_1_SRC>, 657 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 658 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 659 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, 660 <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, 661 <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, 662 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, 663 <&cru ACLK_PHP_ROOT>; 664 assigned-clock-parents = <&cru PLL_AUPLL>; 665 assigned-clock-rates = 666 <0>, 667 <1188000000>, <1000000000>, 668 <786432000>, <18432000>, 669 <96000000>, <128000000>, 670 <45158400>, <49152000>, 671 <500000000>, <250000000>, 672 <100000000>, <500000000>, 673 <250000000>; 674 }; 675 676 i2c0: i2c@27300000 { 677 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 678 reg = <0x0 0x27300000 0x0 0x1000>; 679 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 680 clock-names = "i2c", "pclk"; 681 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&i2c0m0_xfer>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 uart1: serial@27310000 { 690 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 691 reg = <0x0 0x27310000 0x0 0x100>; 692 reg-shift = <2>; 693 reg-io-width = <4>; 694 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 695 clock-names = "baudclk", "apb_pclk"; 696 dmas = <&dmac0 8>, <&dmac0 9>; 697 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&uart1m0_xfer>; 700 status = "disabled"; 701 }; 702 703 pmu: power-management@27380000 { 704 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 705 reg = <0x0 0x27380000 0x0 0x800>; 706 707 power: power-controller { 708 compatible = "rockchip,rk3576-power-controller"; 709 #power-domain-cells = <1>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 713 power-domain@RK3576_PD_NPU { 714 reg = <RK3576_PD_NPU>; 715 #power-domain-cells = <1>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 719 power-domain@RK3576_PD_NPUTOP { 720 reg = <RK3576_PD_NPUTOP>; 721 clocks = <&cru ACLK_RKNN0>, 722 <&cru ACLK_RKNN1>, 723 <&cru ACLK_RKNN_CBUF>, 724 <&cru CLK_RKNN_DSU0>, 725 <&cru HCLK_RKNN_CBUF>, 726 <&cru HCLK_RKNN_ROOT>, 727 <&cru HCLK_NPU_CM0_ROOT>, 728 <&cru PCLK_NPUTOP_ROOT>; 729 pm_qos = <&qos_npu_mcu>, 730 <&qos_npu_nsp0>, 731 <&qos_npu_nsp1>, 732 <&qos_npu_m0ro>, 733 <&qos_npu_m1ro>; 734 #power-domain-cells = <1>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 power-domain@RK3576_PD_NPU0 { 739 reg = <RK3576_PD_NPU0>; 740 clocks = <&cru HCLK_RKNN_ROOT>, 741 <&cru ACLK_RKNN0>; 742 pm_qos = <&qos_npu_m0>; 743 #power-domain-cells = <0>; 744 }; 745 power-domain@RK3576_PD_NPU1 { 746 reg = <RK3576_PD_NPU1>; 747 clocks = <&cru HCLK_RKNN_ROOT>, 748 <&cru ACLK_RKNN1>; 749 pm_qos = <&qos_npu_m1>; 750 #power-domain-cells = <0>; 751 }; 752 }; 753 }; 754 755 power-domain@RK3576_PD_GPU { 756 reg = <RK3576_PD_GPU>; 757 clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; 758 pm_qos = <&qos_gpu>; 759 #power-domain-cells = <0>; 760 }; 761 762 power-domain@RK3576_PD_NVM { 763 reg = <RK3576_PD_NVM>; 764 clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; 765 pm_qos = <&qos_emmc>, 766 <&qos_fspi0>; 767 #power-domain-cells = <1>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 771 power-domain@RK3576_PD_SDGMAC { 772 reg = <RK3576_PD_SDGMAC>; 773 clocks = <&cru ACLK_HSGPIO>, 774 <&cru ACLK_GMAC0>, 775 <&cru ACLK_GMAC1>, 776 <&cru CCLK_SRC_SDIO>, 777 <&cru CCLK_SRC_SDMMC0>, 778 <&cru HCLK_HSGPIO>, 779 <&cru HCLK_SDIO>, 780 <&cru HCLK_SDMMC0>, 781 <&cru PCLK_SDGMAC_ROOT>; 782 pm_qos = <&qos_fspi1>, 783 <&qos_gmac0>, 784 <&qos_gmac1>, 785 <&qos_sdio>, 786 <&qos_sdmmc>, 787 <&qos_flexbus>; 788 #power-domain-cells = <0>; 789 }; 790 }; 791 792 power-domain@RK3576_PD_PHP { 793 reg = <RK3576_PD_PHP>; 794 clocks = <&cru ACLK_PHP_ROOT>, 795 <&cru PCLK_PHP_ROOT>, 796 <&cru ACLK_MMU0>, 797 <&cru ACLK_MMU1>; 798 pm_qos = <&qos_mmu0>, 799 <&qos_mmu1>; 800 #power-domain-cells = <1>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 804 power-domain@RK3576_PD_SUBPHP { 805 reg = <RK3576_PD_SUBPHP>; 806 #power-domain-cells = <0>; 807 }; 808 }; 809 810 power-domain@RK3576_PD_AUDIO { 811 reg = <RK3576_PD_AUDIO>; 812 #power-domain-cells = <0>; 813 }; 814 815 power-domain@RK3576_PD_VEPU1 { 816 reg = <RK3576_PD_VEPU1>; 817 clocks = <&cru ACLK_VEPU1>, 818 <&cru HCLK_VEPU1>; 819 pm_qos = <&qos_vepu1>; 820 #power-domain-cells = <0>; 821 }; 822 823 power-domain@RK3576_PD_VPU { 824 reg = <RK3576_PD_VPU>; 825 clocks = <&cru ACLK_EBC>, 826 <&cru HCLK_EBC>, 827 <&cru ACLK_JPEG>, 828 <&cru HCLK_JPEG>, 829 <&cru ACLK_RGA2E_0>, 830 <&cru HCLK_RGA2E_0>, 831 <&cru ACLK_RGA2E_1>, 832 <&cru HCLK_RGA2E_1>, 833 <&cru ACLK_VDPP>, 834 <&cru HCLK_VDPP>; 835 pm_qos = <&qos_ebc>, 836 <&qos_jpeg>, 837 <&qos_rga0>, 838 <&qos_rga1>, 839 <&qos_vdpp>; 840 #power-domain-cells = <0>; 841 }; 842 843 power-domain@RK3576_PD_VDEC { 844 reg = <RK3576_PD_VDEC>; 845 clocks = <&cru ACLK_RKVDEC_ROOT>, 846 <&cru HCLK_RKVDEC>; 847 pm_qos = <&qos_rkvdec>; 848 #power-domain-cells = <0>; 849 }; 850 851 power-domain@RK3576_PD_VI { 852 reg = <RK3576_PD_VI>; 853 clocks = <&cru ACLK_VICAP>, 854 <&cru HCLK_VICAP>, 855 <&cru DCLK_VICAP>, 856 <&cru ACLK_VI_ROOT>, 857 <&cru HCLK_VI_ROOT>, 858 <&cru PCLK_VI_ROOT>, 859 <&cru CLK_ISP_CORE>, 860 <&cru ACLK_ISP>, 861 <&cru HCLK_ISP>, 862 <&cru CLK_CORE_VPSS>, 863 <&cru ACLK_VPSS>, 864 <&cru HCLK_VPSS>; 865 pm_qos = <&qos_isp_mro>, 866 <&qos_isp_mwo>, 867 <&qos_vicap_m0>, 868 <&qos_vpss_mro>, 869 <&qos_vpss_mwo>; 870 #power-domain-cells = <1>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 874 power-domain@RK3576_PD_VEPU0 { 875 reg = <RK3576_PD_VEPU0>; 876 clocks = <&cru ACLK_VEPU0>, 877 <&cru HCLK_VEPU0>; 878 pm_qos = <&qos_vepu0>; 879 #power-domain-cells = <0>; 880 }; 881 }; 882 883 power-domain@RK3576_PD_VOP { 884 reg = <RK3576_PD_VOP>; 885 clocks = <&cru ACLK_VOP>, 886 <&cru HCLK_VOP>, 887 <&cru HCLK_VOP_ROOT>, 888 <&cru PCLK_VOP_ROOT>; 889 pm_qos = <&qos_vop_m0>, 890 <&qos_vop_m1ro>; 891 #power-domain-cells = <1>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 895 power-domain@RK3576_PD_USB { 896 reg = <RK3576_PD_USB>; 897 clocks = <&cru PCLK_PHP_ROOT>, 898 <&cru ACLK_USB_ROOT>, 899 <&cru ACLK_MMU2>, 900 <&cru ACLK_SLV_MMU2>, 901 <&cru ACLK_UFS_SYS>; 902 pm_qos = <&qos_mmu2>, 903 <&qos_ufshc>; 904 #power-domain-cells = <0>; 905 }; 906 907 power-domain@RK3576_PD_VO0 { 908 reg = <RK3576_PD_VO0>; 909 clocks = <&cru ACLK_HDCP0>, 910 <&cru HCLK_HDCP0>, 911 <&cru ACLK_VO0_ROOT>, 912 <&cru PCLK_VO0_ROOT>, 913 <&cru HCLK_VOP_ROOT>; 914 pm_qos = <&qos_hdcp0>; 915 #power-domain-cells = <0>; 916 }; 917 918 power-domain@RK3576_PD_VO1 { 919 reg = <RK3576_PD_VO1>; 920 clocks = <&cru ACLK_HDCP1>, 921 <&cru HCLK_HDCP1>, 922 <&cru ACLK_VO1_ROOT>, 923 <&cru PCLK_VO1_ROOT>, 924 <&cru HCLK_VOP_ROOT>; 925 pm_qos = <&qos_hdcp1>; 926 #power-domain-cells = <0>; 927 }; 928 }; 929 }; 930 }; 931 932 gpu: gpu@27800000 { 933 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; 934 reg = <0x0 0x27800000 0x0 0x200000>; 935 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 936 assigned-clock-rates = <198000000>; 937 clocks = <&cru CLK_GPU>; 938 clock-names = "core"; 939 dynamic-power-coefficient = <1625>; 940 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "job", "mmu", "gpu"; 944 operating-points-v2 = <&gpu_opp_table>; 945 power-domains = <&power RK3576_PD_GPU>; 946 #cooling-cells = <2>; 947 status = "disabled"; 948 }; 949 950 vop: vop@27d00000 { 951 compatible = "rockchip,rk3576-vop"; 952 reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; 953 reg-names = "vop", "gamma-lut"; 954 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "sys", 959 "vp0", 960 "vp1", 961 "vp2"; 962 clocks = <&cru ACLK_VOP>, 963 <&cru HCLK_VOP>, 964 <&cru DCLK_VP0>, 965 <&cru DCLK_VP1>, 966 <&cru DCLK_VP2>; 967 clock-names = "aclk", 968 "hclk", 969 "dclk_vp0", 970 "dclk_vp1", 971 "dclk_vp2"; 972 iommus = <&vop_mmu>; 973 power-domains = <&power RK3576_PD_VOP>; 974 rockchip,grf = <&sys_grf>; 975 rockchip,pmu = <&pmu>; 976 status = "disabled"; 977 978 vop_out: ports { 979 #address-cells = <1>; 980 #size-cells = <0>; 981 982 vp0: port@0 { 983 #address-cells = <1>; 984 #size-cells = <0>; 985 reg = <0>; 986 }; 987 988 vp1: port@1 { 989 #address-cells = <1>; 990 #size-cells = <0>; 991 reg = <1>; 992 }; 993 994 vp2: port@2 { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 reg = <2>; 998 }; 999 }; 1000 }; 1001 1002 vop_mmu: iommu@27d07e00 { 1003 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; 1004 reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; 1005 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1007 clock-names = "aclk", "iface"; 1008 #iommu-cells = <0>; 1009 power-domains = <&power RK3576_PD_VOP>; 1010 status = "disabled"; 1011 }; 1012 1013 hdmi: hdmi@27da0000 { 1014 compatible = "rockchip,rk3576-dw-hdmi-qp"; 1015 reg = <0x0 0x27da0000 0x0 0x20000>; 1016 clocks = <&cru PCLK_HDMITX0>, 1017 <&cru CLK_HDMITX0_EARC>, 1018 <&cru CLK_HDMITX0_REF>, 1019 <&cru MCLK_SAI6_8CH>, 1020 <&cru CLK_HDMITXHDP>, 1021 <&cru HCLK_VO0_ROOT>; 1022 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 1023 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1028 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 1029 phys = <&hdptxphy>; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; 1032 power-domains = <&power RK3576_PD_VO0>; 1033 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; 1034 reset-names = "ref", "hdp"; 1035 rockchip,grf = <&ioc_grf>; 1036 rockchip,vo-grf = <&vo0_grf>; 1037 status = "disabled"; 1038 1039 ports { 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 hdmi_in: port@0 { 1044 reg = <0>; 1045 }; 1046 1047 hdmi_out: port@1 { 1048 reg = <1>; 1049 }; 1050 }; 1051 }; 1052 1053 qos_hdcp1: qos@27f02000 { 1054 compatible = "rockchip,rk3576-qos", "syscon"; 1055 reg = <0x0 0x27f02000 0x0 0x20>; 1056 }; 1057 1058 qos_fspi1: qos@27f04000 { 1059 compatible = "rockchip,rk3576-qos", "syscon"; 1060 reg = <0x0 0x27f04000 0x0 0x20>; 1061 }; 1062 1063 qos_gmac0: qos@27f04080 { 1064 compatible = "rockchip,rk3576-qos", "syscon"; 1065 reg = <0x0 0x27f04080 0x0 0x20>; 1066 }; 1067 1068 qos_gmac1: qos@27f04100 { 1069 compatible = "rockchip,rk3576-qos", "syscon"; 1070 reg = <0x0 0x27f04100 0x0 0x20>; 1071 }; 1072 1073 qos_sdio: qos@27f04180 { 1074 compatible = "rockchip,rk3576-qos", "syscon"; 1075 reg = <0x0 0x27f04180 0x0 0x20>; 1076 }; 1077 1078 qos_sdmmc: qos@27f04200 { 1079 compatible = "rockchip,rk3576-qos", "syscon"; 1080 reg = <0x0 0x27f04200 0x0 0x20>; 1081 }; 1082 1083 qos_flexbus: qos@27f04280 { 1084 compatible = "rockchip,rk3576-qos", "syscon"; 1085 reg = <0x0 0x27f04280 0x0 0x20>; 1086 }; 1087 1088 qos_gpu: qos@27f05000 { 1089 compatible = "rockchip,rk3576-qos", "syscon"; 1090 reg = <0x0 0x27f05000 0x0 0x20>; 1091 }; 1092 1093 qos_vepu1: qos@27f06000 { 1094 compatible = "rockchip,rk3576-qos", "syscon"; 1095 reg = <0x0 0x27f06000 0x0 0x20>; 1096 }; 1097 1098 qos_npu_mcu: qos@27f08000 { 1099 compatible = "rockchip,rk3576-qos", "syscon"; 1100 reg = <0x0 0x27f08000 0x0 0x20>; 1101 }; 1102 1103 qos_npu_nsp0: qos@27f08080 { 1104 compatible = "rockchip,rk3576-qos", "syscon"; 1105 reg = <0x0 0x27f08080 0x0 0x20>; 1106 }; 1107 1108 qos_npu_nsp1: qos@27f08100 { 1109 compatible = "rockchip,rk3576-qos", "syscon"; 1110 reg = <0x0 0x27f08100 0x0 0x20>; 1111 }; 1112 1113 qos_emmc: qos@27f09000 { 1114 compatible = "rockchip,rk3576-qos", "syscon"; 1115 reg = <0x0 0x27f09000 0x0 0x20>; 1116 }; 1117 1118 qos_fspi0: qos@27f09080 { 1119 compatible = "rockchip,rk3576-qos", "syscon"; 1120 reg = <0x0 0x27f09080 0x0 0x20>; 1121 }; 1122 1123 qos_mmu0: qos@27f0a000 { 1124 compatible = "rockchip,rk3576-qos", "syscon"; 1125 reg = <0x0 0x27f0a000 0x0 0x20>; 1126 }; 1127 1128 qos_mmu1: qos@27f0a080 { 1129 compatible = "rockchip,rk3576-qos", "syscon"; 1130 reg = <0x0 0x27f0a080 0x0 0x20>; 1131 }; 1132 1133 qos_rkvdec: qos@27f0c000 { 1134 compatible = "rockchip,rk3576-qos", "syscon"; 1135 reg = <0x0 0x27f0c000 0x0 0x20>; 1136 }; 1137 1138 qos_crypto: qos@27f0d000 { 1139 compatible = "rockchip,rk3576-qos", "syscon"; 1140 reg = <0x0 0x27f0d000 0x0 0x20>; 1141 }; 1142 1143 qos_mmu2: qos@27f0e000 { 1144 compatible = "rockchip,rk3576-qos", "syscon"; 1145 reg = <0x0 0x27f0e000 0x0 0x20>; 1146 }; 1147 1148 qos_ufshc: qos@27f0e080 { 1149 compatible = "rockchip,rk3576-qos", "syscon"; 1150 reg = <0x0 0x27f0e080 0x0 0x20>; 1151 }; 1152 1153 qos_vepu0: qos@27f0f000 { 1154 compatible = "rockchip,rk3576-qos", "syscon"; 1155 reg = <0x0 0x27f0f000 0x0 0x20>; 1156 }; 1157 1158 qos_isp_mro: qos@27f10000 { 1159 compatible = "rockchip,rk3576-qos", "syscon"; 1160 reg = <0x0 0x27f10000 0x0 0x20>; 1161 }; 1162 1163 qos_isp_mwo: qos@27f10080 { 1164 compatible = "rockchip,rk3576-qos", "syscon"; 1165 reg = <0x0 0x27f10080 0x0 0x20>; 1166 }; 1167 1168 qos_vicap_m0: qos@27f10100 { 1169 compatible = "rockchip,rk3576-qos", "syscon"; 1170 reg = <0x0 0x27f10100 0x0 0x20>; 1171 }; 1172 1173 qos_vpss_mro: qos@27f10180 { 1174 compatible = "rockchip,rk3576-qos", "syscon"; 1175 reg = <0x0 0x27f10180 0x0 0x20>; 1176 }; 1177 1178 qos_vpss_mwo: qos@27f10200 { 1179 compatible = "rockchip,rk3576-qos", "syscon"; 1180 reg = <0x0 0x27f10200 0x0 0x20>; 1181 }; 1182 1183 qos_hdcp0: qos@27f11000 { 1184 compatible = "rockchip,rk3576-qos", "syscon"; 1185 reg = <0x0 0x27f11000 0x0 0x20>; 1186 }; 1187 1188 qos_vop_m0: qos@27f12800 { 1189 compatible = "rockchip,rk3576-qos", "syscon"; 1190 reg = <0x0 0x27f12800 0x0 0x20>; 1191 }; 1192 1193 qos_vop_m1ro: qos@27f12880 { 1194 compatible = "rockchip,rk3576-qos", "syscon"; 1195 reg = <0x0 0x27f12880 0x0 0x20>; 1196 }; 1197 1198 qos_ebc: qos@27f13000 { 1199 compatible = "rockchip,rk3576-qos", "syscon"; 1200 reg = <0x0 0x27f13000 0x0 0x20>; 1201 }; 1202 1203 qos_rga0: qos@27f13080 { 1204 compatible = "rockchip,rk3576-qos", "syscon"; 1205 reg = <0x0 0x27f13080 0x0 0x20>; 1206 }; 1207 1208 qos_rga1: qos@27f13100 { 1209 compatible = "rockchip,rk3576-qos", "syscon"; 1210 reg = <0x0 0x27f13100 0x0 0x20>; 1211 }; 1212 1213 qos_jpeg: qos@27f13180 { 1214 compatible = "rockchip,rk3576-qos", "syscon"; 1215 reg = <0x0 0x27f13180 0x0 0x20>; 1216 }; 1217 1218 qos_vdpp: qos@27f13200 { 1219 compatible = "rockchip,rk3576-qos", "syscon"; 1220 reg = <0x0 0x27f13200 0x0 0x20>; 1221 }; 1222 1223 qos_npu_m0: qos@27f20000 { 1224 compatible = "rockchip,rk3576-qos", "syscon"; 1225 reg = <0x0 0x27f20000 0x0 0x20>; 1226 }; 1227 1228 qos_npu_m1: qos@27f21000 { 1229 compatible = "rockchip,rk3576-qos", "syscon"; 1230 reg = <0x0 0x27f21000 0x0 0x20>; 1231 }; 1232 1233 qos_npu_m0ro: qos@27f22080 { 1234 compatible = "rockchip,rk3576-qos", "syscon"; 1235 reg = <0x0 0x27f22080 0x0 0x20>; 1236 }; 1237 1238 qos_npu_m1ro: qos@27f22100 { 1239 compatible = "rockchip,rk3576-qos", "syscon"; 1240 reg = <0x0 0x27f22100 0x0 0x20>; 1241 }; 1242 1243 gmac0: ethernet@2a220000 { 1244 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1245 reg = <0x0 0x2a220000 0x0 0x10000>; 1246 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 1247 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 1248 <&cru CLK_GMAC0_PTP_REF>; 1249 clock-names = "stmmaceth", "clk_mac_ref", 1250 "pclk_mac", "aclk_mac", 1251 "ptp_ref"; 1252 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1254 interrupt-names = "macirq", "eth_wake_irq"; 1255 power-domains = <&power RK3576_PD_SDGMAC>; 1256 resets = <&cru SRST_A_GMAC0>; 1257 reset-names = "stmmaceth"; 1258 rockchip,grf = <&sdgmac_grf>; 1259 rockchip,php-grf = <&ioc_grf>; 1260 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1261 snps,mixed-burst; 1262 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1263 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1264 snps,tso; 1265 status = "disabled"; 1266 1267 mdio0: mdio { 1268 compatible = "snps,dwmac-mdio"; 1269 #address-cells = <0x1>; 1270 #size-cells = <0x0>; 1271 }; 1272 1273 gmac0_stmmac_axi_setup: stmmac-axi-config { 1274 snps,blen = <0 0 0 0 16 8 4>; 1275 snps,rd_osr_lmt = <8>; 1276 snps,wr_osr_lmt = <4>; 1277 }; 1278 1279 gmac0_mtl_rx_setup: rx-queues-config { 1280 snps,rx-queues-to-use = <1>; 1281 queue0 {}; 1282 }; 1283 1284 gmac0_mtl_tx_setup: tx-queues-config { 1285 snps,tx-queues-to-use = <1>; 1286 queue0 {}; 1287 }; 1288 }; 1289 1290 gmac1: ethernet@2a230000 { 1291 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1292 reg = <0x0 0x2a230000 0x0 0x10000>; 1293 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 1294 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1295 <&cru CLK_GMAC1_PTP_REF>; 1296 clock-names = "stmmaceth", "clk_mac_ref", 1297 "pclk_mac", "aclk_mac", 1298 "ptp_ref"; 1299 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1301 interrupt-names = "macirq", "eth_wake_irq"; 1302 power-domains = <&power RK3576_PD_SDGMAC>; 1303 resets = <&cru SRST_A_GMAC1>; 1304 reset-names = "stmmaceth"; 1305 rockchip,grf = <&sdgmac_grf>; 1306 rockchip,php-grf = <&ioc_grf>; 1307 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1308 snps,mixed-burst; 1309 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1310 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1311 snps,tso; 1312 status = "disabled"; 1313 1314 mdio1: mdio { 1315 compatible = "snps,dwmac-mdio"; 1316 #address-cells = <0x1>; 1317 #size-cells = <0x0>; 1318 }; 1319 1320 gmac1_stmmac_axi_setup: stmmac-axi-config { 1321 snps,blen = <0 0 0 0 16 8 4>; 1322 snps,rd_osr_lmt = <8>; 1323 snps,wr_osr_lmt = <4>; 1324 }; 1325 1326 gmac1_mtl_rx_setup: rx-queues-config { 1327 snps,rx-queues-to-use = <1>; 1328 queue0 {}; 1329 }; 1330 1331 gmac1_mtl_tx_setup: tx-queues-config { 1332 snps,tx-queues-to-use = <1>; 1333 queue0 {}; 1334 }; 1335 }; 1336 1337 ufshc: ufshc@2a2d0000 { 1338 compatible = "rockchip,rk3576-ufshc"; 1339 reg = <0x0 0x2a2d0000 0x0 0x10000>, 1340 <0x0 0x2b040000 0x0 0x10000>, 1341 <0x0 0x2601f000 0x0 0x1000>, 1342 <0x0 0x2603c000 0x0 0x1000>, 1343 <0x0 0x2a2e0000 0x0 0x10000>; 1344 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; 1345 clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, 1346 <&cru CLK_REF_UFS_CLKOUT>; 1347 clock-names = "core", "pclk", "pclk_mphy", "ref_out"; 1348 assigned-clocks = <&cru CLK_REF_OSC_MPHY>; 1349 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; 1350 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1351 power-domains = <&power RK3576_PD_USB>; 1352 pinctrl-0 = <&ufs_refclk>; 1353 pinctrl-names = "default"; 1354 resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, 1355 <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; 1356 reset-names = "biu", "sys", "ufs", "grf"; 1357 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; 1358 status = "disabled"; 1359 }; 1360 1361 sfc1: spi@2a300000 { 1362 compatible = "rockchip,sfc"; 1363 reg = <0x0 0x2a300000 0x0 0x4000>; 1364 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; 1366 clock-names = "clk_sfc", "hclk_sfc"; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 status = "disabled"; 1370 }; 1371 1372 sdmmc: mmc@2a310000 { 1373 compatible = "rockchip,rk3576-dw-mshc"; 1374 reg = <0x0 0x2a310000 0x0 0x4000>; 1375 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 1376 clock-names = "biu", "ciu"; 1377 fifo-depth = <0x100>; 1378 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1379 max-frequency = <200000000>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 1382 power-domains = <&power RK3576_PD_SDGMAC>; 1383 resets = <&cru SRST_H_SDMMC0>; 1384 reset-names = "reset"; 1385 status = "disabled"; 1386 }; 1387 1388 sdhci: mmc@2a330000 { 1389 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 1390 reg = <0x0 0x2a330000 0x0 0x10000>; 1391 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1392 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1393 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1394 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1395 <&cru TCLK_EMMC>; 1396 clock-names = "core", "bus", "axi", "block", "timer"; 1397 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1398 max-frequency = <200000000>; 1399 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1400 <&emmc_cmd>, <&emmc_strb>; 1401 pinctrl-names = "default"; 1402 power-domains = <&power RK3576_PD_NVM>; 1403 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1404 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1405 <&cru SRST_T_EMMC>; 1406 reset-names = "core", "bus", "axi", "block", "timer"; 1407 supports-cqe; 1408 status = "disabled"; 1409 }; 1410 1411 sfc0: spi@2a340000 { 1412 compatible = "rockchip,sfc"; 1413 reg = <0x0 0x2a340000 0x0 0x4000>; 1414 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1415 clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; 1416 clock-names = "clk_sfc", "hclk_sfc"; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 otp: otp@2a580000 { 1423 compatible = "rockchip,rk3576-otp"; 1424 reg = <0x0 0x2a580000 0x0 0x400>; 1425 #address-cells = <1>; 1426 #size-cells = <1>; 1427 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 1428 <&cru CLK_OTP_PHY_G>; 1429 clock-names = "otp", "apb_pclk", "phy"; 1430 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; 1431 reset-names = "otp", "apb"; 1432 1433 /* Data cells */ 1434 cpu_code: cpu-code@2 { 1435 reg = <0x02 0x2>; 1436 }; 1437 otp_cpu_version: cpu-version@5 { 1438 reg = <0x05 0x1>; 1439 bits = <3 3>; 1440 }; 1441 otp_id: id@a { 1442 reg = <0x0a 0x10>; 1443 }; 1444 cpub_leakage: cpub-leakage@1e { 1445 reg = <0x1e 0x1>; 1446 }; 1447 cpul_leakage: cpul-leakage@1f { 1448 reg = <0x1f 0x1>; 1449 }; 1450 npu_leakage: npu-leakage@20 { 1451 reg = <0x20 0x1>; 1452 }; 1453 gpu_leakage: gpu-leakage@21 { 1454 reg = <0x21 0x1>; 1455 }; 1456 log_leakage: log-leakage@22 { 1457 reg = <0x22 0x1>; 1458 }; 1459 }; 1460 1461 gic: interrupt-controller@2a701000 { 1462 compatible = "arm,gic-400"; 1463 reg = <0x0 0x2a701000 0 0x10000>, 1464 <0x0 0x2a702000 0 0x10000>, 1465 <0x0 0x2a704000 0 0x10000>, 1466 <0x0 0x2a706000 0 0x10000>; 1467 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1468 interrupt-controller; 1469 #interrupt-cells = <3>; 1470 #address-cells = <2>; 1471 #size-cells = <2>; 1472 }; 1473 1474 dmac0: dma-controller@2ab90000 { 1475 compatible = "arm,pl330", "arm,primecell"; 1476 reg = <0x0 0x2ab90000 0x0 0x4000>; 1477 arm,pl330-periph-burst; 1478 clocks = <&cru ACLK_DMAC0>; 1479 clock-names = "apb_pclk"; 1480 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1482 #dma-cells = <1>; 1483 }; 1484 1485 dmac1: dma-controller@2abb0000 { 1486 compatible = "arm,pl330", "arm,primecell"; 1487 reg = <0x0 0x2abb0000 0x0 0x4000>; 1488 arm,pl330-periph-burst; 1489 clocks = <&cru ACLK_DMAC1>; 1490 clock-names = "apb_pclk"; 1491 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1493 #dma-cells = <1>; 1494 }; 1495 1496 dmac2: dma-controller@2abd0000 { 1497 compatible = "arm,pl330", "arm,primecell"; 1498 reg = <0x0 0x2abd0000 0x0 0x4000>; 1499 arm,pl330-periph-burst; 1500 clocks = <&cru ACLK_DMAC2>; 1501 clock-names = "apb_pclk"; 1502 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1504 #dma-cells = <1>; 1505 }; 1506 1507 i2c1: i2c@2ac40000 { 1508 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1509 reg = <0x0 0x2ac40000 0x0 0x1000>; 1510 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1511 clock-names = "i2c", "pclk"; 1512 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1513 pinctrl-names = "default"; 1514 pinctrl-0 = <&i2c1m0_xfer>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 status = "disabled"; 1518 }; 1519 1520 i2c2: i2c@2ac50000 { 1521 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1522 reg = <0x0 0x2ac50000 0x0 0x1000>; 1523 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1524 clock-names = "i2c", "pclk"; 1525 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1526 pinctrl-names = "default"; 1527 pinctrl-0 = <&i2c2m0_xfer>; 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 status = "disabled"; 1531 }; 1532 1533 i2c3: i2c@2ac60000 { 1534 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1535 reg = <0x0 0x2ac60000 0x0 0x1000>; 1536 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1537 clock-names = "i2c", "pclk"; 1538 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1539 pinctrl-names = "default"; 1540 pinctrl-0 = <&i2c3m0_xfer>; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 i2c4: i2c@2ac70000 { 1547 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1548 reg = <0x0 0x2ac70000 0x0 0x1000>; 1549 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1550 clock-names = "i2c", "pclk"; 1551 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1552 pinctrl-names = "default"; 1553 pinctrl-0 = <&i2c4m0_xfer>; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 i2c5: i2c@2ac80000 { 1560 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1561 reg = <0x0 0x2ac80000 0x0 0x1000>; 1562 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1563 clock-names = "i2c", "pclk"; 1564 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&i2c5m0_xfer>; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 1572 1573 i2c6: i2c@2ac90000 { 1574 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1575 reg = <0x0 0x2ac90000 0x0 0x1000>; 1576 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1577 clock-names = "i2c", "pclk"; 1578 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1579 pinctrl-names = "default"; 1580 pinctrl-0 = <&i2c6m0_xfer>; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 status = "disabled"; 1584 }; 1585 1586 i2c7: i2c@2aca0000 { 1587 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1588 reg = <0x0 0x2aca0000 0x0 0x1000>; 1589 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1590 clock-names = "i2c", "pclk"; 1591 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1592 pinctrl-names = "default"; 1593 pinctrl-0 = <&i2c7m0_xfer>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 status = "disabled"; 1597 }; 1598 1599 i2c8: i2c@2acb0000 { 1600 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1601 reg = <0x0 0x2acb0000 0x0 0x1000>; 1602 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 1603 clock-names = "i2c", "pclk"; 1604 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&i2c8m0_xfer>; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 status = "disabled"; 1610 }; 1611 1612 timer0: timer@2acc0000 { 1613 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 1614 reg = <0x0 0x2acc0000 0x0 0x20>; 1615 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 1616 clock-names = "pclk", "timer"; 1617 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1618 }; 1619 1620 wdt: watchdog@2ace0000 { 1621 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; 1622 reg = <0x0 0x2ace0000 0x0 0x100>; 1623 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1624 clock-names = "tclk", "pclk"; 1625 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1626 status = "disabled"; 1627 }; 1628 1629 spi0: spi@2acf0000 { 1630 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1631 reg = <0x0 0x2acf0000 0x0 0x1000>; 1632 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1633 clock-names = "spiclk", "apb_pclk"; 1634 dmas = <&dmac0 14>, <&dmac0 15>; 1635 dma-names = "tx", "rx"; 1636 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1637 num-cs = <2>; 1638 pinctrl-names = "default"; 1639 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 spi1: spi@2ad00000 { 1646 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1647 reg = <0x0 0x2ad00000 0x0 0x1000>; 1648 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1649 clock-names = "spiclk", "apb_pclk"; 1650 dmas = <&dmac0 16>, <&dmac0 17>; 1651 dma-names = "tx", "rx"; 1652 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1653 num-cs = <2>; 1654 pinctrl-names = "default"; 1655 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 1656 #address-cells = <1>; 1657 #size-cells = <0>; 1658 status = "disabled"; 1659 }; 1660 1661 spi2: spi@2ad10000 { 1662 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1663 reg = <0x0 0x2ad10000 0x0 0x1000>; 1664 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1665 clock-names = "spiclk", "apb_pclk"; 1666 dmas = <&dmac1 15>, <&dmac1 16>; 1667 dma-names = "tx", "rx"; 1668 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1669 num-cs = <2>; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 status = "disabled"; 1675 }; 1676 1677 spi3: spi@2ad20000 { 1678 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1679 reg = <0x0 0x2ad20000 0x0 0x1000>; 1680 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1681 clock-names = "spiclk", "apb_pclk"; 1682 dmas = <&dmac1 17>, <&dmac1 18>; 1683 dma-names = "tx", "rx"; 1684 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1685 num-cs = <2>; 1686 pinctrl-names = "default"; 1687 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 status = "disabled"; 1691 }; 1692 1693 spi4: spi@2ad30000 { 1694 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1695 reg = <0x0 0x2ad30000 0x0 0x1000>; 1696 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 1697 clock-names = "spiclk", "apb_pclk"; 1698 dmas = <&dmac2 12>, <&dmac2 13>; 1699 dma-names = "tx", "rx"; 1700 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1701 num-cs = <2>; 1702 pinctrl-names = "default"; 1703 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 status = "disabled"; 1707 }; 1708 1709 uart0: serial@2ad40000 { 1710 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1711 reg = <0x0 0x2ad40000 0x0 0x100>; 1712 reg-shift = <2>; 1713 reg-io-width = <4>; 1714 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1715 clock-names = "baudclk", "apb_pclk"; 1716 dmas = <&dmac0 6>, <&dmac0 7>; 1717 dma-names = "tx", "rx"; 1718 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1719 pinctrl-0 = <&uart0m0_xfer>; 1720 pinctrl-names = "default"; 1721 status = "disabled"; 1722 }; 1723 1724 uart2: serial@2ad50000 { 1725 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1726 reg = <0x0 0x2ad50000 0x0 0x100>; 1727 reg-shift = <2>; 1728 reg-io-width = <4>; 1729 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1730 clock-names = "baudclk", "apb_pclk"; 1731 dmas = <&dmac0 10>, <&dmac0 11>; 1732 dma-names = "tx", "rx"; 1733 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1734 pinctrl-names = "default"; 1735 pinctrl-0 = <&uart2m0_xfer>; 1736 status = "disabled"; 1737 }; 1738 1739 uart3: serial@2ad60000 { 1740 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1741 reg = <0x0 0x2ad60000 0x0 0x100>; 1742 reg-shift = <2>; 1743 reg-io-width = <4>; 1744 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1745 clock-names = "baudclk", "apb_pclk"; 1746 dmas = <&dmac0 12>, <&dmac0 13>; 1747 dma-names = "tx", "rx"; 1748 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1749 pinctrl-0 = <&uart3m0_xfer>; 1750 pinctrl-names = "default"; 1751 status = "disabled"; 1752 }; 1753 1754 uart4: serial@2ad70000 { 1755 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1756 reg = <0x0 0x2ad70000 0x0 0x100>; 1757 reg-shift = <2>; 1758 reg-io-width = <4>; 1759 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1760 clock-names = "baudclk", "apb_pclk"; 1761 dmas = <&dmac1 9>, <&dmac1 10>; 1762 dma-names = "tx", "rx"; 1763 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1764 pinctrl-0 = <&uart4m0_xfer>; 1765 pinctrl-names = "default"; 1766 status = "disabled"; 1767 }; 1768 1769 uart5: serial@2ad80000 { 1770 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1771 reg = <0x0 0x2ad80000 0x0 0x100>; 1772 reg-shift = <2>; 1773 reg-io-width = <4>; 1774 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1775 clock-names = "baudclk", "apb_pclk"; 1776 dmas = <&dmac1 11>, <&dmac1 12>; 1777 dma-names = "tx", "rx"; 1778 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1779 pinctrl-0 = <&uart5m0_xfer>; 1780 pinctrl-names = "default"; 1781 status = "disabled"; 1782 }; 1783 1784 uart6: serial@2ad90000 { 1785 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1786 reg = <0x0 0x2ad90000 0x0 0x100>; 1787 reg-shift = <2>; 1788 reg-io-width = <4>; 1789 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1790 clock-names = "baudclk", "apb_pclk"; 1791 dmas = <&dmac1 13>, <&dmac1 14>; 1792 dma-names = "tx", "rx"; 1793 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1794 pinctrl-0 = <&uart6m0_xfer>; 1795 pinctrl-names = "default"; 1796 status = "disabled"; 1797 }; 1798 1799 uart7: serial@2ada0000 { 1800 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1801 reg = <0x0 0x2ada0000 0x0 0x100>; 1802 reg-shift = <2>; 1803 reg-io-width = <4>; 1804 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1805 clock-names = "baudclk", "apb_pclk"; 1806 dmas = <&dmac2 6>, <&dmac2 7>; 1807 dma-names = "tx", "rx"; 1808 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1809 pinctrl-0 = <&uart7m0_xfer>; 1810 pinctrl-names = "default"; 1811 status = "disabled"; 1812 }; 1813 1814 uart8: serial@2adb0000 { 1815 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1816 reg = <0x0 0x2adb0000 0x0 0x100>; 1817 reg-shift = <2>; 1818 reg-io-width = <4>; 1819 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1820 clock-names = "baudclk", "apb_pclk"; 1821 dmas = <&dmac2 8>, <&dmac2 9>; 1822 dma-names = "tx", "rx"; 1823 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1824 pinctrl-0 = <&uart8m0_xfer>; 1825 pinctrl-names = "default"; 1826 status = "disabled"; 1827 }; 1828 1829 uart9: serial@2adc0000 { 1830 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1831 reg = <0x0 0x2adc0000 0x0 0x100>; 1832 reg-shift = <2>; 1833 reg-io-width = <4>; 1834 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1835 clock-names = "baudclk", "apb_pclk"; 1836 dmas = <&dmac2 10>, <&dmac2 11>; 1837 dma-names = "tx", "rx"; 1838 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1839 pinctrl-0 = <&uart9m0_xfer>; 1840 pinctrl-names = "default"; 1841 status = "disabled"; 1842 }; 1843 1844 saradc: adc@2ae00000 { 1845 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 1846 reg = <0x0 0x2ae00000 0x0 0x10000>; 1847 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1848 clock-names = "saradc", "apb_pclk"; 1849 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1850 resets = <&cru SRST_P_SARADC>; 1851 reset-names = "saradc-apb"; 1852 #io-channel-cells = <1>; 1853 status = "disabled"; 1854 }; 1855 1856 i2c9: i2c@2ae80000 { 1857 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1858 reg = <0x0 0x2ae80000 0x0 0x1000>; 1859 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 1860 clock-names = "i2c", "pclk"; 1861 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1862 pinctrl-names = "default"; 1863 pinctrl-0 = <&i2c9m0_xfer>; 1864 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; 1865 reset-names = "i2c", "apb"; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 status = "disabled"; 1869 }; 1870 1871 uart10: serial@2afc0000 { 1872 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1873 reg = <0x0 0x2afc0000 0x0 0x100>; 1874 reg-shift = <2>; 1875 reg-io-width = <4>; 1876 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 1877 clock-names = "baudclk", "apb_pclk"; 1878 dmas = <&dmac2 21>, <&dmac2 22>; 1879 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1880 pinctrl-names = "default"; 1881 pinctrl-0 = <&uart10m0_xfer>; 1882 status = "disabled"; 1883 }; 1884 1885 uart11: serial@2afd0000 { 1886 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1887 reg = <0x0 0x2afd0000 0x0 0x100>; 1888 reg-shift = <2>; 1889 reg-io-width = <4>; 1890 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 1891 clock-names = "baudclk", "apb_pclk"; 1892 dmas = <&dmac2 23>, <&dmac2 24>; 1893 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1894 pinctrl-names = "default"; 1895 pinctrl-0 = <&uart11m0_xfer>; 1896 status = "disabled"; 1897 }; 1898 1899 combphy0_ps: phy@2b050000 { 1900 compatible = "rockchip,rk3576-naneng-combphy"; 1901 reg = <0x0 0x2b050000 0x0 0x100>; 1902 #phy-cells = <1>; 1903 clocks = <&cru CLK_REF_PCIE0_PHY>, 1904 <&cru PCLK_PCIE2_COMBOPHY0>, 1905 <&cru PCLK_PCIE0>; 1906 clock-names = "ref", "apb", "pipe"; 1907 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 1908 assigned-clock-rates = <100000000>; 1909 resets = <&cru SRST_PCIE0_PIPE_PHY>, 1910 <&cru SRST_P_PCIE2_COMBOPHY0>; 1911 reset-names = "phy", "apb"; 1912 rockchip,pipe-grf = <&php_grf>; 1913 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 1914 status = "disabled"; 1915 }; 1916 1917 combphy1_psu: phy@2b060000 { 1918 compatible = "rockchip,rk3576-naneng-combphy"; 1919 reg = <0x0 0x2b060000 0x0 0x100>; 1920 #phy-cells = <1>; 1921 clocks = <&cru CLK_REF_PCIE1_PHY>, 1922 <&cru PCLK_PCIE2_COMBOPHY1>, 1923 <&cru PCLK_PCIE1>; 1924 clock-names = "ref", "apb", "pipe"; 1925 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 1926 assigned-clock-rates = <100000000>; 1927 resets = <&cru SRST_PCIE1_PIPE_PHY>, 1928 <&cru SRST_P_PCIE2_COMBOPHY1>; 1929 reset-names = "phy", "apb"; 1930 rockchip,pipe-grf = <&php_grf>; 1931 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 1932 status = "disabled"; 1933 }; 1934 1935 usbdp_phy: phy@2b010000 { 1936 compatible = "rockchip,rk3576-usbdp-phy"; 1937 reg = <0x0 0x2b010000 0x0 0x10000>; 1938 #phy-cells = <1>; 1939 clocks = <&cru CLK_PHY_REF_SRC >, 1940 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 1941 <&cru PCLK_USBDPPHY>, 1942 <&u2phy0>; 1943 clock-names = "refclk", "immortal", "pclk", "utmi"; 1944 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 1945 <&cru SRST_USBDP_COMBO_PHY_CMN>, 1946 <&cru SRST_USBDP_COMBO_PHY_LANE>, 1947 <&cru SRST_USBDP_COMBO_PHY_PCS>, 1948 <&cru SRST_P_USBDPPHY>; 1949 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 1950 rockchip,u2phy-grf = <&usb2phy_grf>; 1951 rockchip,usb-grf = <&usb_grf>; 1952 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 1953 rockchip,vo-grf = <&vo1_grf>; 1954 status = "disabled"; 1955 }; 1956 1957 hdptxphy: hdmiphy@2b000000 { 1958 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; 1959 reg = <0x0 0x2b000000 0x0 0x2000>; 1960 clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; 1961 clock-names = "ref", "apb"; 1962 resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, 1963 <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; 1964 reset-names = "apb", "init", "cmn", "lane"; 1965 rockchip,grf = <&hdptxphy_grf>; 1966 #phy-cells = <0>; 1967 status = "disabled"; 1968 }; 1969 1970 sram: sram@3ff88000 { 1971 compatible = "mmio-sram"; 1972 reg = <0x0 0x3ff88000 0x0 0x78000>; 1973 ranges = <0x0 0x0 0x3ff88000 0x78000>; 1974 #address-cells = <1>; 1975 #size-cells = <1>; 1976 1977 /* start address and size should be 4k align */ 1978 rkvdec_sram: rkvdec-sram@0 { 1979 reg = <0x0 0x78000>; 1980 }; 1981 }; 1982 1983 scmi_shmem: scmi-shmem@4010f000 { 1984 compatible = "arm,scmi-shmem"; 1985 reg = <0x0 0x4010f000 0x0 0x100>; 1986 }; 1987 1988 pinctrl: pinctrl { 1989 compatible = "rockchip,rk3576-pinctrl"; 1990 rockchip,grf = <&ioc_grf>; 1991 #address-cells = <2>; 1992 #size-cells = <2>; 1993 ranges; 1994 1995 gpio0: gpio@27320000 { 1996 compatible = "rockchip,gpio-bank"; 1997 reg = <0x0 0x27320000 0x0 0x200>; 1998 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1999 gpio-controller; 2000 gpio-ranges = <&pinctrl 0 0 32>; 2001 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2002 interrupt-controller; 2003 #gpio-cells = <2>; 2004 #interrupt-cells = <2>; 2005 }; 2006 2007 gpio1: gpio@2ae10000 { 2008 compatible = "rockchip,gpio-bank"; 2009 reg = <0x0 0x2ae10000 0x0 0x200>; 2010 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2011 gpio-controller; 2012 gpio-ranges = <&pinctrl 0 32 32>; 2013 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2014 interrupt-controller; 2015 #gpio-cells = <2>; 2016 #interrupt-cells = <2>; 2017 }; 2018 2019 gpio2: gpio@2ae20000 { 2020 compatible = "rockchip,gpio-bank"; 2021 reg = <0x0 0x2ae20000 0x0 0x200>; 2022 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2023 gpio-controller; 2024 gpio-ranges = <&pinctrl 0 64 32>; 2025 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 2026 interrupt-controller; 2027 #gpio-cells = <2>; 2028 #interrupt-cells = <2>; 2029 }; 2030 2031 gpio3: gpio@2ae30000 { 2032 compatible = "rockchip,gpio-bank"; 2033 reg = <0x0 0x2ae30000 0x0 0x200>; 2034 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2035 gpio-controller; 2036 gpio-ranges = <&pinctrl 0 96 32>; 2037 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-controller; 2039 #gpio-cells = <2>; 2040 #interrupt-cells = <2>; 2041 }; 2042 2043 gpio4: gpio@2ae40000 { 2044 compatible = "rockchip,gpio-bank"; 2045 reg = <0x0 0x2ae40000 0x0 0x200>; 2046 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2047 gpio-controller; 2048 gpio-ranges = <&pinctrl 0 128 32>; 2049 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 2050 interrupt-controller; 2051 #gpio-cells = <2>; 2052 #interrupt-cells = <2>; 2053 }; 2054 }; 2055 }; 2056}; 2057 2058#include "rk3576-pinctrl.dtsi" 2059