1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include "rockchip-pinconf.dtsi"
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	arm {
15		/omit-if-no-ref/
16		arm_pins: arm-pins {
17			rockchip,pins =
18				/* arm_avs */
19				<4 RK_PC4 3 &pcfg_pull_none>;
20		};
21	};
22
23	clk {
24		/omit-if-no-ref/
25		clkm0_32k_out: clkm0-32k-out {
26			rockchip,pins =
27				/* clkm0_32k_out */
28				<3 RK_PC3 3 &pcfg_pull_none>;
29		};
30
31		/omit-if-no-ref/
32		clkm1_32k_out: clkm1-32k-out {
33			rockchip,pins =
34				/* clkm1_32k_out */
35				<1 RK_PC3 1 &pcfg_pull_none>;
36		};
37	};
38
39	emmc {
40		/omit-if-no-ref/
41		emmc_rstnout: emmc-rstnout {
42			rockchip,pins =
43				/* emmc_rstn */
44				<1 RK_PD6 1 &pcfg_pull_none>;
45		};
46
47		/omit-if-no-ref/
48		emmc_bus8: emmc-bus8 {
49			rockchip,pins =
50				/* emmc_d0 */
51				<1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
52				/* emmc_d1 */
53				<1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
54				/* emmc_d2 */
55				<1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
56				/* emmc_d3 */
57				<1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
58				/* emmc_d4 */
59				<1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
60				/* emmc_d5 */
61				<1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
62				/* emmc_d6 */
63				<1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
64				/* emmc_d7 */
65				<1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
66		};
67
68		/omit-if-no-ref/
69		emmc_clk: emmc-clk {
70			rockchip,pins =
71				/* emmc_clk */
72				<1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
73		};
74
75		/omit-if-no-ref/
76		emmc_cmd: emmc-cmd {
77			rockchip,pins =
78				/* emmc_cmd */
79				<1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
80		};
81
82		/omit-if-no-ref/
83		emmc_strb: emmc-strb {
84			rockchip,pins =
85				/* emmc_strb */
86				<1 RK_PD7 1 &pcfg_pull_none>;
87		};
88	};
89
90	eth {
91		/omit-if-no-ref/
92		eth_pins: eth-pins {
93			rockchip,pins =
94				/* eth_clk_25m_out */
95				<3 RK_PB5 2 &pcfg_pull_none_drv_level_2>;
96		};
97	};
98
99	fephy {
100		/omit-if-no-ref/
101		fephym0_led_dpx: fephym0-led_dpx {
102			rockchip,pins =
103				/* fephy_led_dpx_m0 */
104				<4 RK_PB5 2 &pcfg_pull_none>;
105		};
106
107		/omit-if-no-ref/
108		fephym0_led_link: fephym0-led_link {
109			rockchip,pins =
110				/* fephy_led_link_m0 */
111				<4 RK_PC0 2 &pcfg_pull_none>;
112		};
113
114		/omit-if-no-ref/
115		fephym0_led_spd: fephym0-led_spd {
116			rockchip,pins =
117				/* fephy_led_spd_m0 */
118				<4 RK_PB7 2 &pcfg_pull_none>;
119		};
120
121		/omit-if-no-ref/
122		fephym1_led_dpx: fephym1-led_dpx {
123			rockchip,pins =
124				/* fephy_led_dpx_m1 */
125				<2 RK_PA4 5 &pcfg_pull_none>;
126		};
127
128		/omit-if-no-ref/
129		fephym1_led_link: fephym1-led_link {
130			rockchip,pins =
131				/* fephy_led_link_m1 */
132				<2 RK_PA6 5 &pcfg_pull_none>;
133		};
134
135		/omit-if-no-ref/
136		fephym1_led_spd: fephym1-led_spd {
137			rockchip,pins =
138				/* fephy_led_spd_m1 */
139				<2 RK_PA5 5 &pcfg_pull_none>;
140		};
141	};
142
143	fspi {
144		/omit-if-no-ref/
145		fspi_pins: fspi-pins {
146			rockchip,pins =
147				/* fspi_clk */
148				<1 RK_PD5 2 &pcfg_pull_none>,
149				/* fspi_d0 */
150				<1 RK_PC4 2 &pcfg_pull_none>,
151				/* fspi_d1 */
152				<1 RK_PC5 2 &pcfg_pull_none>,
153				/* fspi_d2 */
154				<1 RK_PC6 2 &pcfg_pull_none>,
155				/* fspi_d3 */
156				<1 RK_PC7 2 &pcfg_pull_none>;
157		};
158
159		/omit-if-no-ref/
160		fspi_csn0: fspi-csn0 {
161			rockchip,pins =
162				/* fspi_csn0 */
163				<1 RK_PD0 2 &pcfg_pull_none>;
164		};
165		/omit-if-no-ref/
166		fspi_csn1: fspi-csn1 {
167			rockchip,pins =
168				/* fspi_csn1 */
169				<1 RK_PD1 2 &pcfg_pull_none>;
170		};
171	};
172
173	gpu {
174		/omit-if-no-ref/
175		gpu_pins: gpu-pins {
176			rockchip,pins =
177				/* gpu_avs */
178				<4 RK_PC3 3 &pcfg_pull_none>;
179		};
180	};
181
182	hdmi {
183		/omit-if-no-ref/
184		hdmi_pins: hdmi-pins {
185			rockchip,pins =
186				/* hdmi_tx_cec */
187				<0 RK_PA3 1 &pcfg_pull_none>,
188				/* hdmi_tx_hpd */
189				<0 RK_PA2 1 &pcfg_pull_none>,
190				/* hdmi_tx_scl */
191				<0 RK_PA4 1 &pcfg_pull_none>,
192				/* hdmi_tx_sda */
193				<0 RK_PA5 1 &pcfg_pull_none>;
194		};
195	};
196
197	hsm {
198		/omit-if-no-ref/
199		hsmm0_pins: hsmm0-pins {
200			rockchip,pins =
201				/* hsm_clk_out_m0 */
202				<2 RK_PA2 4 &pcfg_pull_none>;
203		};
204
205		/omit-if-no-ref/
206		hsmm1_pins: hsmm1-pins {
207			rockchip,pins =
208				/* hsm_clk_out_m1 */
209				<1 RK_PA4 3 &pcfg_pull_none>;
210		};
211	};
212
213	i2c0 {
214		/omit-if-no-ref/
215		i2c0m0_xfer: i2c0m0-xfer {
216			rockchip,pins =
217				/* i2c0_scl_m0 */
218				<4 RK_PC4 2 &pcfg_pull_none_smt>,
219				/* i2c0_sda_m0 */
220				<4 RK_PC3 2 &pcfg_pull_none_smt>;
221		};
222
223		/omit-if-no-ref/
224		i2c0m1_xfer: i2c0m1-xfer {
225			rockchip,pins =
226				/* i2c0_scl_m1 */
227				<4 RK_PA1 2 &pcfg_pull_none_smt>,
228				/* i2c0_sda_m1 */
229				<4 RK_PA0 2 &pcfg_pull_none_smt>;
230		};
231	};
232
233	i2c1 {
234		/omit-if-no-ref/
235		i2c1m0_xfer: i2c1m0-xfer {
236			rockchip,pins =
237				/* i2c1_scl_m0 */
238				<4 RK_PA3 2 &pcfg_pull_none_smt>,
239				/* i2c1_sda_m0 */
240				<4 RK_PA2 2 &pcfg_pull_none_smt>;
241		};
242
243		/omit-if-no-ref/
244		i2c1m1_xfer: i2c1m1-xfer {
245			rockchip,pins =
246				/* i2c1_scl_m1 */
247				<4 RK_PC5 4 &pcfg_pull_none_smt>,
248				/* i2c1_sda_m1 */
249				<4 RK_PC6 4 &pcfg_pull_none_smt>;
250		};
251	};
252
253	i2c2 {
254		/omit-if-no-ref/
255		i2c2m0_xfer: i2c2m0-xfer {
256			rockchip,pins =
257				/* i2c2_scl_m0 */
258				<0 RK_PA4 2 &pcfg_pull_none_smt>,
259				/* i2c2_sda_m0 */
260				<0 RK_PA5 2 &pcfg_pull_none_smt>;
261		};
262
263		/omit-if-no-ref/
264		i2c2m1_xfer: i2c2m1-xfer {
265			rockchip,pins =
266				/* i2c2_scl_m1 */
267				<1 RK_PA5 3 &pcfg_pull_none_smt>,
268				/* i2c2_sda_m1 */
269				<1 RK_PA6 3 &pcfg_pull_none_smt>;
270		};
271	};
272
273	i2c3 {
274		/omit-if-no-ref/
275		i2c3m0_xfer: i2c3m0-xfer {
276			rockchip,pins =
277				/* i2c3_scl_m0 */
278				<1 RK_PA0 2 &pcfg_pull_none_smt>,
279				/* i2c3_sda_m0 */
280				<1 RK_PA1 2 &pcfg_pull_none_smt>;
281		};
282
283		/omit-if-no-ref/
284		i2c3m1_xfer: i2c3m1-xfer {
285			rockchip,pins =
286				/* i2c3_scl_m1 */
287				<3 RK_PC1 5 &pcfg_pull_none_smt>,
288				/* i2c3_sda_m1 */
289				<3 RK_PC3 5 &pcfg_pull_none_smt>;
290		};
291	};
292
293	i2c4 {
294		/omit-if-no-ref/
295		i2c4_xfer: i2c4-xfer {
296			rockchip,pins =
297				/* i2c4_scl */
298				<2 RK_PA0 4 &pcfg_pull_none_smt>,
299				/* i2c4_sda */
300				<2 RK_PA1 4 &pcfg_pull_none_smt>;
301		};
302	};
303
304	i2c5 {
305		/omit-if-no-ref/
306		i2c5m0_xfer: i2c5m0-xfer {
307			rockchip,pins =
308				/* i2c5_scl_m0 */
309				<1 RK_PB2 3 &pcfg_pull_none_smt>,
310				/* i2c5_sda_m0 */
311				<1 RK_PB3 3 &pcfg_pull_none_smt>;
312		};
313
314		/omit-if-no-ref/
315		i2c5m1_xfer: i2c5m1-xfer {
316			rockchip,pins =
317				/* i2c5_scl_m1 */
318				<1 RK_PD2 3 &pcfg_pull_none_smt>,
319				/* i2c5_sda_m1 */
320				<1 RK_PD3 3 &pcfg_pull_none_smt>;
321		};
322	};
323
324	i2c6 {
325		/omit-if-no-ref/
326		i2c6m0_xfer: i2c6m0-xfer {
327			rockchip,pins =
328				/* i2c6_scl_m0 */
329				<3 RK_PB2 5 &pcfg_pull_none_smt>,
330				/* i2c6_sda_m0 */
331				<3 RK_PB3 5 &pcfg_pull_none_smt>;
332		};
333
334		/omit-if-no-ref/
335		i2c6m1_xfer: i2c6m1-xfer {
336			rockchip,pins =
337				/* i2c6_scl_m1 */
338				<1 RK_PD4 3 &pcfg_pull_none_smt>,
339				/* i2c6_sda_m1 */
340				<1 RK_PD7 3 &pcfg_pull_none_smt>;
341		};
342	};
343
344	i2c7 {
345		/omit-if-no-ref/
346		i2c7_xfer: i2c7-xfer {
347			rockchip,pins =
348				/* i2c7_scl */
349				<2 RK_PA5 4 &pcfg_pull_none_smt>,
350				/* i2c7_sda */
351				<2 RK_PA6 4 &pcfg_pull_none_smt>;
352		};
353	};
354
355	i2s0 {
356		/omit-if-no-ref/
357		i2s0m0_lrck: i2s0m0-lrck {
358			rockchip,pins =
359				/* i2s0_lrck_m0 */
360				<3 RK_PB6 1 &pcfg_pull_none_smt>;
361		};
362
363		/omit-if-no-ref/
364		i2s0m0_mclk: i2s0m0-mclk {
365			rockchip,pins =
366				/* i2s0_mclk_m0 */
367				<3 RK_PB4 1 &pcfg_pull_none_smt>;
368		};
369
370		/omit-if-no-ref/
371		i2s0m0_sclk: i2s0m0-sclk {
372			rockchip,pins =
373				/* i2s0_sclk_m0 */
374				<3 RK_PB5 1 &pcfg_pull_none_smt>;
375		};
376
377		/omit-if-no-ref/
378		i2s0m0_sdi: i2s0m0-sdi {
379			rockchip,pins =
380				/* i2s0m0_sdi */
381				<3 RK_PB7 1 &pcfg_pull_none>;
382		};
383		/omit-if-no-ref/
384		i2s0m0_sdo: i2s0m0-sdo {
385			rockchip,pins =
386				/* i2s0m0_sdo */
387				<3 RK_PC0 1 &pcfg_pull_none>;
388		};
389
390		/omit-if-no-ref/
391		i2s0m1_lrck: i2s0m1-lrck {
392			rockchip,pins =
393				/* i2s0_lrck_m1 */
394				<1 RK_PB6 1 &pcfg_pull_none_smt>;
395		};
396
397		/omit-if-no-ref/
398		i2s0m1_mclk: i2s0m1-mclk {
399			rockchip,pins =
400				/* i2s0_mclk_m1 */
401				<1 RK_PB4 1 &pcfg_pull_none_smt>;
402		};
403
404		/omit-if-no-ref/
405		i2s0m1_sclk: i2s0m1-sclk {
406			rockchip,pins =
407				/* i2s0_sclk_m1 */
408				<1 RK_PB5 1 &pcfg_pull_none_smt>;
409		};
410
411		/omit-if-no-ref/
412		i2s0m1_sdi: i2s0m1-sdi {
413			rockchip,pins =
414				/* i2s0m1_sdi */
415				<1 RK_PB7 1 &pcfg_pull_none>;
416		};
417		/omit-if-no-ref/
418		i2s0m1_sdo: i2s0m1-sdo {
419			rockchip,pins =
420				/* i2s0m1_sdo */
421				<1 RK_PC0 1 &pcfg_pull_none>;
422		};
423	};
424
425	i2s1 {
426		/omit-if-no-ref/
427		i2s1_lrck: i2s1-lrck {
428			rockchip,pins =
429				/* i2s1_lrck */
430				<4 RK_PA6 1 &pcfg_pull_none_smt>;
431		};
432
433		/omit-if-no-ref/
434		i2s1_mclk: i2s1-mclk {
435			rockchip,pins =
436				/* i2s1_mclk */
437				<4 RK_PA4 1 &pcfg_pull_none_smt>;
438		};
439
440		/omit-if-no-ref/
441		i2s1_sclk: i2s1-sclk {
442			rockchip,pins =
443				/* i2s1_sclk */
444				<4 RK_PA5 1 &pcfg_pull_none_smt>;
445		};
446
447		/omit-if-no-ref/
448		i2s1_sdi0: i2s1-sdi0 {
449			rockchip,pins =
450				/* i2s1_sdi0 */
451				<4 RK_PB4 1 &pcfg_pull_none>;
452		};
453
454		/omit-if-no-ref/
455		i2s1_sdi1: i2s1-sdi1 {
456			rockchip,pins =
457				/* i2s1_sdi1 */
458				<4 RK_PB3 1 &pcfg_pull_none>;
459		};
460
461		/omit-if-no-ref/
462		i2s1_sdi2: i2s1-sdi2 {
463			rockchip,pins =
464				/* i2s1_sdi2 */
465				<4 RK_PA3 1 &pcfg_pull_none>;
466		};
467
468		/omit-if-no-ref/
469		i2s1_sdi3: i2s1-sdi3 {
470			rockchip,pins =
471				/* i2s1_sdi3 */
472				<4 RK_PA2 1 &pcfg_pull_none>;
473		};
474
475		/omit-if-no-ref/
476		i2s1_sdo0: i2s1-sdo0 {
477			rockchip,pins =
478				/* i2s1_sdo0 */
479				<4 RK_PA7 1 &pcfg_pull_none>;
480		};
481
482		/omit-if-no-ref/
483		i2s1_sdo1: i2s1-sdo1 {
484			rockchip,pins =
485				/* i2s1_sdo1 */
486				<4 RK_PB0 1 &pcfg_pull_none>;
487		};
488
489		/omit-if-no-ref/
490		i2s1_sdo2: i2s1-sdo2 {
491			rockchip,pins =
492				/* i2s1_sdo2 */
493				<4 RK_PB1 1 &pcfg_pull_none>;
494		};
495
496		/omit-if-no-ref/
497		i2s1_sdo3: i2s1-sdo3 {
498			rockchip,pins =
499				/* i2s1_sdo3 */
500				<4 RK_PB2 1 &pcfg_pull_none>;
501		};
502	};
503
504	jtag {
505		/omit-if-no-ref/
506		jtagm0_pins: jtagm0-pins {
507			rockchip,pins =
508				/* jtag_cpu_tck_m0 */
509				<2 RK_PA2 2 &pcfg_pull_none>,
510				/* jtag_cpu_tms_m0 */
511				<2 RK_PA3 2 &pcfg_pull_none>,
512				/* jtag_mcu_tck_m0 */
513				<2 RK_PA4 2 &pcfg_pull_none>,
514				/* jtag_mcu_tms_m0 */
515				<2 RK_PA5 2 &pcfg_pull_none>;
516		};
517
518		/omit-if-no-ref/
519		jtagm1_pins: jtagm1-pins {
520			rockchip,pins =
521				/* jtag_cpu_tck_m1 */
522				<4 RK_PD0 2 &pcfg_pull_none>,
523				/* jtag_cpu_tms_m1 */
524				<4 RK_PC7 2 &pcfg_pull_none>,
525				/* jtag_mcu_tck_m1 */
526				<4 RK_PD0 3 &pcfg_pull_none>,
527				/* jtag_mcu_tms_m1 */
528				<4 RK_PC7 3 &pcfg_pull_none>;
529		};
530	};
531
532	pcie {
533		/omit-if-no-ref/
534		pciem0_pins: pciem0-pins {
535			rockchip,pins =
536				/* pcie_clkreqn_m0 */
537				<3 RK_PA6 5 &pcfg_pull_none>,
538				/* pcie_perstn_m0 */
539				<3 RK_PB0 5 &pcfg_pull_none>,
540				/* pcie_waken_m0 */
541				<3 RK_PA7 5 &pcfg_pull_none>;
542		};
543
544		/omit-if-no-ref/
545		pciem1_pins: pciem1-pins {
546			rockchip,pins =
547				/* pcie_clkreqn_m1 */
548				<1 RK_PA0 4 &pcfg_pull_none>,
549				/* pcie_perstn_m1 */
550				<1 RK_PA2 4 &pcfg_pull_none>,
551				/* pcie_waken_m1 */
552				<1 RK_PA1 4 &pcfg_pull_none>;
553		};
554	};
555
556	pdm {
557		/omit-if-no-ref/
558		pdm_clk0: pdm-clk0 {
559			rockchip,pins =
560				/* pdm_clk0 */
561				<4 RK_PB5 3 &pcfg_pull_none>;
562		};
563
564		/omit-if-no-ref/
565		pdm_clk1: pdm-clk1 {
566			rockchip,pins =
567				/* pdm_clk1 */
568				<4 RK_PA4 3 &pcfg_pull_none>;
569		};
570
571		/omit-if-no-ref/
572		pdm_sdi0: pdm-sdi0 {
573			rockchip,pins =
574				/* pdm_sdi0 */
575				<4 RK_PB2 3 &pcfg_pull_none>;
576		};
577
578		/omit-if-no-ref/
579		pdm_sdi1: pdm-sdi1 {
580			rockchip,pins =
581				/* pdm_sdi1 */
582				<4 RK_PB1 3 &pcfg_pull_none>;
583		};
584
585		/omit-if-no-ref/
586		pdm_sdi2: pdm-sdi2 {
587			rockchip,pins =
588				/* pdm_sdi2 */
589				<4 RK_PB3 3 &pcfg_pull_none>;
590		};
591
592		/omit-if-no-ref/
593		pdm_sdi3: pdm-sdi3 {
594			rockchip,pins =
595				/* pdm_sdi3 */
596				<4 RK_PC1 3 &pcfg_pull_none>;
597		};
598	};
599
600	pmu {
601		/omit-if-no-ref/
602		pmu_pins: pmu-pins {
603			rockchip,pins =
604				/* pmu_debug */
605				<4 RK_PA0 4 &pcfg_pull_none>;
606		};
607	};
608
609	pwm0 {
610		/omit-if-no-ref/
611		pwm0m0_pins: pwm0m0-pins {
612			rockchip,pins =
613				/* pwm0_m0 */
614				<4 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
615		};
616
617		/omit-if-no-ref/
618		pwm0m1_pins: pwm0m1-pins {
619			rockchip,pins =
620				/* pwm0_m1 */
621				<1 RK_PA2 5 &pcfg_pull_none_drv_level_0>;
622		};
623	};
624
625	pwm1 {
626		/omit-if-no-ref/
627		pwm1m0_pins: pwm1m0-pins {
628			rockchip,pins =
629				/* pwm1_m0 */
630				<4 RK_PC4 1 &pcfg_pull_none_drv_level_0>;
631		};
632
633		/omit-if-no-ref/
634		pwm1m1_pins: pwm1m1-pins {
635			rockchip,pins =
636				/* pwm1_m1 */
637				<1 RK_PA3 4 &pcfg_pull_none_drv_level_0>;
638		};
639	};
640
641	pwm2 {
642		/omit-if-no-ref/
643		pwm2m0_pins: pwm2m0-pins {
644			rockchip,pins =
645				/* pwm2_m0 */
646				<4 RK_PC5 1 &pcfg_pull_none_drv_level_0>;
647		};
648
649		/omit-if-no-ref/
650		pwm2m1_pins: pwm2m1-pins {
651			rockchip,pins =
652				/* pwm2_m1 */
653				<1 RK_PA7 2 &pcfg_pull_none_drv_level_0>;
654		};
655	};
656
657	pwm3 {
658		/omit-if-no-ref/
659		pwm3m0_pins: pwm3m0-pins {
660			rockchip,pins =
661				/* pwm3_m0 */
662				<4 RK_PC6 1 &pcfg_pull_none_drv_level_0>;
663		};
664
665		/omit-if-no-ref/
666		pwm3m1_pins: pwm3m1-pins {
667			rockchip,pins =
668				/* pwm3_m1 */
669				<2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
670		};
671	};
672
673	pwm4 {
674		/omit-if-no-ref/
675		pwm4m0_pins: pwm4m0-pins {
676			rockchip,pins =
677				/* pwm4_m0 */
678				<4 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
679		};
680
681		/omit-if-no-ref/
682		pwm4m1_pins: pwm4m1-pins {
683			rockchip,pins =
684				/* pwm4_m1 */
685				<1 RK_PA4 2 &pcfg_pull_none_drv_level_0>;
686		};
687	};
688
689	pwm5 {
690		/omit-if-no-ref/
691		pwm5m0_pins: pwm5m0-pins {
692			rockchip,pins =
693				/* pwm5_m0 */
694				<4 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
695		};
696
697		/omit-if-no-ref/
698		pwm5m1_pins: pwm5m1-pins {
699			rockchip,pins =
700				/* pwm5_m1 */
701				<3 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
702		};
703	};
704
705	pwm6 {
706		/omit-if-no-ref/
707		pwm6m0_pins: pwm6m0-pins {
708			rockchip,pins =
709				/* pwm6_m0 */
710				<4 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
711		};
712
713		/omit-if-no-ref/
714		pwm6m1_pins: pwm6m1-pins {
715			rockchip,pins =
716				/* pwm6_m1 */
717				<1 RK_PC3 3 &pcfg_pull_none_drv_level_0>;
718		};
719
720		/omit-if-no-ref/
721		pwm6m2_pins: pwm6m2-pins {
722			rockchip,pins =
723				/* pwm6_m2 */
724				<3 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
725		};
726	};
727
728	pwm7 {
729		/omit-if-no-ref/
730		pwm7m0_pins: pwm7m0-pins {
731			rockchip,pins =
732				/* pwm7_m0 */
733				<4 RK_PC2 1 &pcfg_pull_none_drv_level_0>;
734		};
735
736		/omit-if-no-ref/
737		pwm7m1_pins: pwm7m1-pins {
738			rockchip,pins =
739				/* pwm7_m1 */
740				<1 RK_PC2 2 &pcfg_pull_none_drv_level_0>;
741		};
742	};
743
744	pwr {
745		/omit-if-no-ref/
746		pwr_pins: pwr-pins {
747			rockchip,pins =
748				/* pwr_ctrl0 */
749				<4 RK_PC2 2 &pcfg_pull_none>,
750				/* pwr_ctrl1 */
751				<4 RK_PB6 1 &pcfg_pull_none>;
752		};
753	};
754
755	ref {
756		/omit-if-no-ref/
757		refm0_pins: refm0-pins {
758			rockchip,pins =
759				/* ref_clk_out_m0 */
760				<0 RK_PA1 1 &pcfg_pull_none>;
761		};
762
763		/omit-if-no-ref/
764		refm1_pins: refm1-pins {
765			rockchip,pins =
766				/* ref_clk_out_m1 */
767				<3 RK_PC3 6 &pcfg_pull_none>;
768		};
769	};
770
771	rgmii {
772		/omit-if-no-ref/
773		rgmii_miim: rgmii-miim {
774			rockchip,pins =
775				/* rgmii_mdc */
776				<3 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
777				/* rgmii_mdio */
778				<3 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
779		};
780
781		/omit-if-no-ref/
782		rgmii_rx_bus2: rgmii-rx_bus2 {
783			rockchip,pins =
784				/* rgmii_rxd0 */
785				<3 RK_PA3 2 &pcfg_pull_none>,
786				/* rgmii_rxd1 */
787				<3 RK_PA2 2 &pcfg_pull_none>,
788				/* rgmii_rxdv_crs */
789				<3 RK_PC2 2 &pcfg_pull_none>;
790		};
791
792		/omit-if-no-ref/
793		rgmii_tx_bus2: rgmii-tx_bus2 {
794			rockchip,pins =
795				/* rgmii_txd0 */
796				<3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
797				/* rgmii_txd1 */
798				<3 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
799				/* rgmii_txen */
800				<3 RK_PC0 2 &pcfg_pull_none>;
801		};
802
803		/omit-if-no-ref/
804		rgmii_rgmii_clk: rgmii-rgmii_clk {
805			rockchip,pins =
806				/* rgmii_rxclk */
807				<3 RK_PA5 2 &pcfg_pull_none>,
808				/* rgmii_txclk */
809				<3 RK_PA4 2 &pcfg_pull_none_drv_level_2>;
810		};
811
812		/omit-if-no-ref/
813		rgmii_rgmii_bus: rgmii-rgmii_bus {
814			rockchip,pins =
815				/* rgmii_rxd2 */
816				<3 RK_PA7 2 &pcfg_pull_none>,
817				/* rgmii_rxd3 */
818				<3 RK_PA6 2 &pcfg_pull_none>,
819				/* rgmii_txd2 */
820				<3 RK_PB1 2 &pcfg_pull_none_drv_level_2>,
821				/* rgmii_txd3 */
822				<3 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
823		};
824
825		/omit-if-no-ref/
826		rgmii_clk: rgmii-clk {
827			rockchip,pins =
828				/* rgmii_clk */
829				<3 RK_PB4 2 &pcfg_pull_none>;
830		};
831		/omit-if-no-ref/
832		rgmii_txer: rgmii-txer {
833			rockchip,pins =
834				/* rgmii_txer */
835				<3 RK_PC1 2 &pcfg_pull_none>;
836		};
837	};
838
839	scr {
840		/omit-if-no-ref/
841		scrm0_pins: scrm0-pins {
842			rockchip,pins =
843				/* scr_clk_m0 */
844				<1 RK_PA2 3 &pcfg_pull_none>,
845				/* scr_data_m0 */
846				<1 RK_PA1 3 &pcfg_pull_none>,
847				/* scr_detn_m0 */
848				<1 RK_PA0 3 &pcfg_pull_none>,
849				/* scr_rstn_m0 */
850				<1 RK_PA3 3 &pcfg_pull_none>;
851		};
852
853		/omit-if-no-ref/
854		scrm1_pins: scrm1-pins {
855			rockchip,pins =
856				/* scr_clk_m1 */
857				<2 RK_PA5 3 &pcfg_pull_none>,
858				/* scr_data_m1 */
859				<2 RK_PA3 4 &pcfg_pull_none>,
860				/* scr_detn_m1 */
861				<2 RK_PA6 3 &pcfg_pull_none>,
862				/* scr_rstn_m1 */
863				<2 RK_PA4 4 &pcfg_pull_none>;
864		};
865	};
866
867	sdio0 {
868		/omit-if-no-ref/
869		sdio0_bus4: sdio0-bus4 {
870			rockchip,pins =
871				/* sdio0_d0 */
872				<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
873				/* sdio0_d1 */
874				<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
875				/* sdio0_d2 */
876				<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
877				/* sdio0_d3 */
878				<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
879		};
880
881		/omit-if-no-ref/
882		sdio0_clk: sdio0-clk {
883			rockchip,pins =
884				/* sdio0_clk */
885				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
886		};
887
888		/omit-if-no-ref/
889		sdio0_cmd: sdio0-cmd {
890			rockchip,pins =
891				/* sdio0_cmd */
892				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
893		};
894
895		/omit-if-no-ref/
896		sdio0_det: sdio0-det {
897			rockchip,pins =
898				/* sdio0_det */
899				<1 RK_PA6 1 &pcfg_pull_up>;
900		};
901
902		/omit-if-no-ref/
903		sdio0_pwren: sdio0-pwren {
904			rockchip,pins =
905				/* sdio0_pwren */
906				<1 RK_PA7 1 &pcfg_pull_none>;
907		};
908	};
909
910	sdio1 {
911		/omit-if-no-ref/
912		sdio1_bus4: sdio1-bus4 {
913			rockchip,pins =
914				/* sdio1_d0 */
915				<3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
916				/* sdio1_d1 */
917				<3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
918				/* sdio1_d2 */
919				<3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
920				/* sdio1_d3 */
921				<3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
922		};
923
924		/omit-if-no-ref/
925		sdio1_clk: sdio1-clk {
926			rockchip,pins =
927				/* sdio1_clk */
928				<3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
929		};
930
931		/omit-if-no-ref/
932		sdio1_cmd: sdio1-cmd {
933			rockchip,pins =
934				/* sdio1_cmd */
935				<3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
936		};
937
938		/omit-if-no-ref/
939		sdio1_det: sdio1-det {
940			rockchip,pins =
941				/* sdio1_det */
942				<3 RK_PB3 1 &pcfg_pull_up>;
943		};
944
945		/omit-if-no-ref/
946		sdio1_pwren: sdio1-pwren {
947			rockchip,pins =
948				/* sdio1_pwren */
949				<3 RK_PB2 1 &pcfg_pull_none>;
950		};
951	};
952
953	sdmmc {
954		/omit-if-no-ref/
955		sdmmc_bus4: sdmmc-bus4 {
956			rockchip,pins =
957				/* sdmmc_d0 */
958				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
959				/* sdmmc_d1 */
960				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
961				/* sdmmc_d2 */
962				<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
963				/* sdmmc_d3 */
964				<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
965		};
966
967		/omit-if-no-ref/
968		sdmmc_clk: sdmmc-clk {
969			rockchip,pins =
970				/* sdmmc_clk */
971				<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
972		};
973
974		/omit-if-no-ref/
975		sdmmc_cmd: sdmmc-cmd {
976			rockchip,pins =
977				/* sdmmc_cmd */
978				<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
979		};
980
981		/omit-if-no-ref/
982		sdmmc_det: sdmmc-det {
983			rockchip,pins =
984				/* sdmmc_detn */
985				<2 RK_PA6 1 &pcfg_pull_up>;
986		};
987
988		/omit-if-no-ref/
989		sdmmc_pwren: sdmmc-pwren {
990			rockchip,pins =
991				/* sdmmc_pwren */
992				<4 RK_PA1 1 &pcfg_pull_none>;
993		};
994	};
995
996	spdif {
997		/omit-if-no-ref/
998		spdifm0_pins: spdifm0-pins {
999			rockchip,pins =
1000				/* spdif_tx_m0 */
1001				<4 RK_PA0 1 &pcfg_pull_none>;
1002		};
1003
1004		/omit-if-no-ref/
1005		spdifm1_pins: spdifm1-pins {
1006			rockchip,pins =
1007				/* spdif_tx_m1 */
1008				<1 RK_PC3 2 &pcfg_pull_none>;
1009		};
1010
1011		/omit-if-no-ref/
1012		spdifm2_pins: spdifm2-pins {
1013			rockchip,pins =
1014				/* spdif_tx_m2 */
1015				<3 RK_PC3 2 &pcfg_pull_none>;
1016		};
1017	};
1018
1019	spi0 {
1020		/omit-if-no-ref/
1021		spi0_pins: spi0-pins {
1022			rockchip,pins =
1023				/* spi0_clk */
1024				<4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
1025				/* spi0_miso */
1026				<4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
1027				/* spi0_mosi */
1028				<4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
1029		};
1030
1031		/omit-if-no-ref/
1032		spi0_csn0: spi0-csn0 {
1033			rockchip,pins =
1034				/* spi0_csn0 */
1035				<4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
1036		};
1037		/omit-if-no-ref/
1038		spi0_csn1: spi0-csn1 {
1039			rockchip,pins =
1040				/* spi0_csn1 */
1041				<4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
1042		};
1043	};
1044
1045	spi1 {
1046		/omit-if-no-ref/
1047		spi1_pins: spi1-pins {
1048			rockchip,pins =
1049				/* spi1_clk */
1050				<1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
1051				/* spi1_miso */
1052				<1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
1053				/* spi1_mosi */
1054				<1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
1055		};
1056
1057		/omit-if-no-ref/
1058		spi1_csn0: spi1-csn0 {
1059			rockchip,pins =
1060				/* spi1_csn0 */
1061				<1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
1062		};
1063		/omit-if-no-ref/
1064		spi1_csn1: spi1-csn1 {
1065			rockchip,pins =
1066				/* spi1_csn1 */
1067				<1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
1068		};
1069	};
1070
1071	tsi0 {
1072		/omit-if-no-ref/
1073		tsi0_pins: tsi0-pins {
1074			rockchip,pins =
1075				/* tsi0_clkin */
1076				<3 RK_PB2 3 &pcfg_pull_none>,
1077				/* tsi0_d0 */
1078				<3 RK_PB1 3 &pcfg_pull_none>,
1079				/* tsi0_d1 */
1080				<3 RK_PB5 3 &pcfg_pull_none>,
1081				/* tsi0_d2 */
1082				<3 RK_PB6 3 &pcfg_pull_none>,
1083				/* tsi0_d3 */
1084				<3 RK_PB7 3 &pcfg_pull_none>,
1085				/* tsi0_d4 */
1086				<3 RK_PA3 3 &pcfg_pull_none>,
1087				/* tsi0_d5 */
1088				<3 RK_PA2 3 &pcfg_pull_none>,
1089				/* tsi0_d6 */
1090				<3 RK_PA1 3 &pcfg_pull_none>,
1091				/* tsi0_d7 */
1092				<3 RK_PA0 3 &pcfg_pull_none>,
1093				/* tsi0_fail */
1094				<3 RK_PC0 3 &pcfg_pull_none>,
1095				/* tsi0_sync */
1096				<3 RK_PB4 3 &pcfg_pull_none>,
1097				/* tsi0_valid */
1098				<3 RK_PB3 3 &pcfg_pull_none>;
1099		};
1100	};
1101
1102	tsi1 {
1103		/omit-if-no-ref/
1104		tsi1_pins: tsi1-pins {
1105			rockchip,pins =
1106				/* tsi1_clkin */
1107				<3 RK_PA5 3 &pcfg_pull_none>,
1108				/* tsi1_d0 */
1109				<3 RK_PA4 3 &pcfg_pull_none>,
1110				/* tsi1_sync */
1111				<3 RK_PA7 3 &pcfg_pull_none>,
1112				/* tsi1_valid */
1113				<3 RK_PA6 3 &pcfg_pull_none>;
1114		};
1115	};
1116
1117	uart0 {
1118		/omit-if-no-ref/
1119		uart0m0_xfer: uart0m0-xfer {
1120			rockchip,pins =
1121				/* uart0_rx_m0 */
1122				<4 RK_PC7 1 &pcfg_pull_up>,
1123				/* uart0_tx_m0 */
1124				<4 RK_PD0 1 &pcfg_pull_up>;
1125		};
1126
1127		/omit-if-no-ref/
1128		uart0m1_xfer: uart0m1-xfer {
1129			rockchip,pins =
1130				/* uart0_rx_m1 */
1131				<2 RK_PA0 2 &pcfg_pull_up>,
1132				/* uart0_tx_m1 */
1133				<2 RK_PA1 2 &pcfg_pull_up>;
1134		};
1135	};
1136
1137	uart1 {
1138		/omit-if-no-ref/
1139		uart1m0_xfer: uart1m0-xfer {
1140			rockchip,pins =
1141				/* uart1_rx_m0 */
1142				<4 RK_PA7 2 &pcfg_pull_up>,
1143				/* uart1_tx_m0 */
1144				<4 RK_PA6 2 &pcfg_pull_up>;
1145		};
1146
1147		/omit-if-no-ref/
1148		uart1m1_xfer: uart1m1-xfer {
1149			rockchip,pins =
1150				/* uart1_rx_m1 */
1151				<4 RK_PC6 2 &pcfg_pull_up>,
1152				/* uart1_tx_m1 */
1153				<4 RK_PC5 2 &pcfg_pull_up>;
1154		};
1155
1156		/omit-if-no-ref/
1157		uart1_ctsn: uart1-ctsn {
1158			rockchip,pins =
1159				/* uart1_ctsn */
1160				<4 RK_PA4 2 &pcfg_pull_none>;
1161		};
1162		/omit-if-no-ref/
1163		uart1_rtsn: uart1-rtsn {
1164			rockchip,pins =
1165				/* uart1_rtsn */
1166				<4 RK_PA5 2 &pcfg_pull_none>;
1167		};
1168	};
1169
1170	uart2 {
1171		/omit-if-no-ref/
1172		uart2m0_xfer: uart2m0-xfer {
1173			rockchip,pins =
1174				/* uart2_rx_m0 */
1175				<3 RK_PA0 1 &pcfg_pull_up>,
1176				/* uart2_tx_m0 */
1177				<3 RK_PA1 1 &pcfg_pull_up>;
1178		};
1179
1180		/omit-if-no-ref/
1181		uart2m0_ctsn: uart2m0-ctsn {
1182			rockchip,pins =
1183				/* uart2m0_ctsn */
1184				<3 RK_PA3 1 &pcfg_pull_none>;
1185		};
1186		/omit-if-no-ref/
1187		uart2m0_rtsn: uart2m0-rtsn {
1188			rockchip,pins =
1189				/* uart2m0_rtsn */
1190				<3 RK_PA2 1 &pcfg_pull_none>;
1191		};
1192
1193		/omit-if-no-ref/
1194		uart2m1_xfer: uart2m1-xfer {
1195			rockchip,pins =
1196				/* uart2_rx_m1 */
1197				<1 RK_PB0 1 &pcfg_pull_up>,
1198				/* uart2_tx_m1 */
1199				<1 RK_PB1 1 &pcfg_pull_up>;
1200		};
1201
1202		/omit-if-no-ref/
1203		uart2m1_ctsn: uart2m1-ctsn {
1204			rockchip,pins =
1205				/* uart2m1_ctsn */
1206				<1 RK_PB3 1 &pcfg_pull_none>;
1207		};
1208		/omit-if-no-ref/
1209		uart2m1_rtsn: uart2m1-rtsn {
1210			rockchip,pins =
1211				/* uart2m1_rtsn */
1212				<1 RK_PB2 1 &pcfg_pull_none>;
1213		};
1214	};
1215
1216	uart3 {
1217		/omit-if-no-ref/
1218		uart3m0_xfer: uart3m0-xfer {
1219			rockchip,pins =
1220				/* uart3_rx_m0 */
1221				<4 RK_PB0 2 &pcfg_pull_up>,
1222				/* uart3_tx_m0 */
1223				<4 RK_PB1 2 &pcfg_pull_up>;
1224		};
1225
1226		/omit-if-no-ref/
1227		uart3m1_xfer: uart3m1-xfer {
1228			rockchip,pins =
1229				/* uart3_rx_m1 */
1230				<4 RK_PB7 3 &pcfg_pull_up>,
1231				/* uart3_tx_m1 */
1232				<4 RK_PC0 3 &pcfg_pull_up>;
1233		};
1234
1235		/omit-if-no-ref/
1236		uart3_ctsn: uart3-ctsn {
1237			rockchip,pins =
1238				/* uart3_ctsn */
1239				<4 RK_PA3 3 &pcfg_pull_none>;
1240		};
1241		/omit-if-no-ref/
1242		uart3_rtsn: uart3-rtsn {
1243			rockchip,pins =
1244				/* uart3_rtsn */
1245				<4 RK_PA2 3 &pcfg_pull_none>;
1246		};
1247	};
1248
1249	uart4 {
1250		/omit-if-no-ref/
1251		uart4_xfer: uart4-xfer {
1252			rockchip,pins =
1253				/* uart4_rx */
1254				<2 RK_PA2 3 &pcfg_pull_up>,
1255				/* uart4_tx */
1256				<2 RK_PA3 3 &pcfg_pull_up>;
1257		};
1258
1259		/omit-if-no-ref/
1260		uart4_ctsn: uart4-ctsn {
1261			rockchip,pins =
1262				/* uart4_ctsn */
1263				<2 RK_PA1 3 &pcfg_pull_none>;
1264		};
1265		/omit-if-no-ref/
1266		uart4_rtsn: uart4-rtsn {
1267			rockchip,pins =
1268				/* uart4_rtsn */
1269				<2 RK_PA0 3 &pcfg_pull_none>;
1270		};
1271	};
1272
1273	uart5 {
1274		/omit-if-no-ref/
1275		uart5m0_xfer: uart5m0-xfer {
1276			rockchip,pins =
1277				/* uart5_rx_m0 */
1278				<1 RK_PA2 2 &pcfg_pull_up>,
1279				/* uart5_tx_m0 */
1280				<1 RK_PA3 2 &pcfg_pull_up>;
1281		};
1282
1283		/omit-if-no-ref/
1284		uart5m0_ctsn: uart5m0-ctsn {
1285			rockchip,pins =
1286				/* uart5m0_ctsn */
1287				<1 RK_PA6 2 &pcfg_pull_none>;
1288		};
1289		/omit-if-no-ref/
1290		uart5m0_rtsn: uart5m0-rtsn {
1291			rockchip,pins =
1292				/* uart5m0_rtsn */
1293				<1 RK_PA5 2 &pcfg_pull_none>;
1294		};
1295
1296		/omit-if-no-ref/
1297		uart5m1_xfer: uart5m1-xfer {
1298			rockchip,pins =
1299				/* uart5_rx_m1 */
1300				<1 RK_PD4 2 &pcfg_pull_up>,
1301				/* uart5_tx_m1 */
1302				<1 RK_PD7 2 &pcfg_pull_up>;
1303		};
1304
1305		/omit-if-no-ref/
1306		uart5m1_ctsn: uart5m1-ctsn {
1307			rockchip,pins =
1308				/* uart5m1_ctsn */
1309				<1 RK_PD3 2 &pcfg_pull_none>;
1310		};
1311		/omit-if-no-ref/
1312		uart5m1_rtsn: uart5m1-rtsn {
1313			rockchip,pins =
1314				/* uart5m1_rtsn */
1315				<1 RK_PD2 2 &pcfg_pull_none>;
1316		};
1317	};
1318
1319	uart6 {
1320		/omit-if-no-ref/
1321		uart6m0_xfer: uart6m0-xfer {
1322			rockchip,pins =
1323				/* uart6_rx_m0 */
1324				<3 RK_PA7 4 &pcfg_pull_up>,
1325				/* uart6_tx_m0 */
1326				<3 RK_PA6 4 &pcfg_pull_up>;
1327		};
1328
1329		/omit-if-no-ref/
1330		uart6m1_xfer: uart6m1-xfer {
1331			rockchip,pins =
1332				/* uart6_rx_m1 */
1333				<3 RK_PC3 4 &pcfg_pull_up>,
1334				/* uart6_tx_m1 */
1335				<3 RK_PC1 4 &pcfg_pull_up>;
1336		};
1337
1338		/omit-if-no-ref/
1339		uart6_ctsn: uart6-ctsn {
1340			rockchip,pins =
1341				/* uart6_ctsn */
1342				<3 RK_PA4 4 &pcfg_pull_none>;
1343		};
1344		/omit-if-no-ref/
1345		uart6_rtsn: uart6-rtsn {
1346			rockchip,pins =
1347				/* uart6_rtsn */
1348				<3 RK_PA5 4 &pcfg_pull_none>;
1349		};
1350	};
1351
1352	uart7 {
1353		/omit-if-no-ref/
1354		uart7m0_xfer: uart7m0-xfer {
1355			rockchip,pins =
1356				/* uart7_rx_m0 */
1357				<3 RK_PB3 4 &pcfg_pull_up>,
1358				/* uart7_tx_m0 */
1359				<3 RK_PB2 4 &pcfg_pull_up>;
1360		};
1361
1362		/omit-if-no-ref/
1363		uart7m0_ctsn: uart7m0-ctsn {
1364			rockchip,pins =
1365				/* uart7m0_ctsn */
1366				<3 RK_PB0 4 &pcfg_pull_none>;
1367		};
1368		/omit-if-no-ref/
1369		uart7m0_rtsn: uart7m0-rtsn {
1370			rockchip,pins =
1371				/* uart7m0_rtsn */
1372				<3 RK_PB1 4 &pcfg_pull_none>;
1373		};
1374
1375		/omit-if-no-ref/
1376		uart7m1_xfer: uart7m1-xfer {
1377			rockchip,pins =
1378				/* uart7_rx_m1 */
1379				<1 RK_PB3 4 &pcfg_pull_up>,
1380				/* uart7_tx_m1 */
1381				<1 RK_PB2 4 &pcfg_pull_up>;
1382		};
1383
1384		/omit-if-no-ref/
1385		uart7m1_ctsn: uart7m1-ctsn {
1386			rockchip,pins =
1387				/* uart7m1_ctsn */
1388				<1 RK_PB0 4 &pcfg_pull_none>;
1389		};
1390		/omit-if-no-ref/
1391		uart7m1_rtsn: uart7m1-rtsn {
1392			rockchip,pins =
1393				/* uart7m1_rtsn */
1394				<1 RK_PB1 4 &pcfg_pull_none>;
1395		};
1396	};
1397};
1398