1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for Marvell Armada AP806.
6 */
7
8#include "armada-ap806.dtsi"
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-a72";
18			reg = <0x000>;
19			enable-method = "psci";
20			#cooling-cells = <2>;
21			clocks = <&cpu_clk 0>;
22			i-cache-size = <0xc000>;
23			i-cache-line-size = <64>;
24			i-cache-sets = <256>;
25			d-cache-size = <0x8000>;
26			d-cache-line-size = <64>;
27			d-cache-sets = <256>;
28			next-level-cache = <&l2>;
29		};
30		cpu1: cpu@1 {
31			device_type = "cpu";
32			compatible = "arm,cortex-a72";
33			reg = <0x001>;
34			enable-method = "psci";
35			#cooling-cells = <2>;
36			clocks = <&cpu_clk 0>;
37			i-cache-size = <0xc000>;
38			i-cache-line-size = <64>;
39			i-cache-sets = <256>;
40			d-cache-size = <0x8000>;
41			d-cache-line-size = <64>;
42			d-cache-sets = <256>;
43			next-level-cache = <&l2>;
44		};
45
46		l2: l2-cache {
47			compatible = "cache";
48			cache-size = <0x80000>;
49			cache-line-size = <64>;
50			cache-sets = <512>;
51			cache-level = <2>;
52			cache-unified;
53		};
54	};
55
56	thermal-zones {
57		/delete-node/ ap-thermal-cpu2;
58		/delete-node/ ap-thermal-cpu3;
59	};
60};
61