1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * dtsi for Hisilicon Hi3660 Coresight
5 *
6 * Copyright (C) 2016-2018 HiSilicon Ltd.
7 *
8 * Author: Wanglai Shi <shiwanglai@hisilicon.com>
9 *
10 */
11/ {
12	soc {
13		/* A53 cluster internals */
14		etm@ecc40000 {
15			compatible = "arm,coresight-etm4x", "arm,primecell";
16			reg = <0 0xecc40000 0 0x1000>;
17			clocks = <&crg_ctrl HI3660_PCLK>;
18			clock-names = "apb_pclk";
19			cpu = <&cpu0>;
20			arm,coresight-loses-context-with-cpu;
21
22			out-ports {
23				port {
24					etm0_out: endpoint {
25						remote-endpoint =
26							<&cluster0_funnel_in0>;
27					};
28				};
29			};
30		};
31
32		etm@ecd40000 {
33			compatible = "arm,coresight-etm4x", "arm,primecell";
34			reg = <0 0xecd40000 0 0x1000>;
35			clocks = <&crg_ctrl HI3660_PCLK>;
36			clock-names = "apb_pclk";
37			cpu = <&cpu1>;
38			arm,coresight-loses-context-with-cpu;
39
40			out-ports {
41				port {
42					etm1_out: endpoint {
43						remote-endpoint =
44							<&cluster0_funnel_in1>;
45					};
46				};
47			};
48		};
49
50		etm@ece40000 {
51			compatible = "arm,coresight-etm4x", "arm,primecell";
52			reg = <0 0xece40000 0 0x1000>;
53			clocks = <&crg_ctrl HI3660_PCLK>;
54			clock-names = "apb_pclk";
55			cpu = <&cpu2>;
56			arm,coresight-loses-context-with-cpu;
57
58			out-ports {
59				port {
60					etm2_out: endpoint {
61						remote-endpoint =
62							<&cluster0_funnel_in2>;
63					};
64				};
65			};
66		};
67
68		etm@ecf40000 {
69			compatible = "arm,coresight-etm4x", "arm,primecell";
70			reg = <0 0xecf40000 0 0x1000>;
71			clocks = <&crg_ctrl HI3660_PCLK>;
72			clock-names = "apb_pclk";
73			cpu = <&cpu3>;
74			arm,coresight-loses-context-with-cpu;
75
76			out-ports {
77				port {
78					etm3_out: endpoint {
79						remote-endpoint =
80							<&cluster0_funnel_in3>;
81					};
82				};
83			};
84		};
85
86		funnel@ec801000 {
87			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
88			reg = <0 0xec801000 0 0x1000>;
89			clocks = <&crg_ctrl HI3660_PCLK>;
90			clock-names = "apb_pclk";
91
92			out-ports {
93				port {
94					cluster0_funnel_out: endpoint {
95						remote-endpoint =
96							<&cluster0_etf_in>;
97					};
98				};
99			};
100
101			in-ports {
102				#address-cells = <1>;
103				#size-cells = <0>;
104
105				port@0 {
106					reg = <0>;
107					cluster0_funnel_in0: endpoint {
108						remote-endpoint = <&etm0_out>;
109					};
110				};
111
112				port@1 {
113					reg = <1>;
114					cluster0_funnel_in1: endpoint {
115						remote-endpoint = <&etm1_out>;
116					};
117				};
118
119				port@2 {
120					reg = <2>;
121					cluster0_funnel_in2: endpoint {
122						remote-endpoint = <&etm2_out>;
123					};
124				};
125
126				port@3 {
127					reg = <3>;
128					cluster0_funnel_in3: endpoint {
129						remote-endpoint = <&etm3_out>;
130					};
131				};
132			};
133		};
134
135		etf@ec802000 {
136			compatible = "arm,coresight-tmc", "arm,primecell";
137			reg = <0 0xec802000 0 0x1000>;
138			clocks = <&crg_ctrl HI3660_PCLK>;
139			clock-names = "apb_pclk";
140
141			in-ports {
142				port {
143					cluster0_etf_in: endpoint {
144						remote-endpoint =
145							<&cluster0_funnel_out>;
146					};
147				};
148			};
149
150			out-ports {
151				port {
152					cluster0_etf_out: endpoint {
153						remote-endpoint =
154							<&combo_funnel_in0>;
155					};
156				};
157			};
158		};
159
160		/* A73 cluster internals */
161		etm@ed440000 {
162			compatible = "arm,coresight-etm4x", "arm,primecell";
163			reg = <0 0xed440000 0 0x1000>;
164			clocks = <&crg_ctrl HI3660_PCLK>;
165			clock-names = "apb_pclk";
166			cpu = <&cpu4>;
167			arm,coresight-loses-context-with-cpu;
168
169			out-ports {
170				port {
171					etm4_out: endpoint {
172						remote-endpoint =
173							<&cluster1_funnel_in0>;
174					};
175				};
176			};
177		};
178
179		etm@ed540000 {
180			compatible = "arm,coresight-etm4x", "arm,primecell";
181			reg = <0 0xed540000 0 0x1000>;
182			clocks = <&crg_ctrl HI3660_PCLK>;
183			clock-names = "apb_pclk";
184			cpu = <&cpu5>;
185			arm,coresight-loses-context-with-cpu;
186
187			out-ports {
188				port {
189					etm5_out: endpoint {
190						remote-endpoint =
191							<&cluster1_funnel_in1>;
192					};
193				};
194			};
195		};
196
197		etm@ed640000 {
198			compatible = "arm,coresight-etm4x", "arm,primecell";
199			reg = <0 0xed640000 0 0x1000>;
200			clocks = <&crg_ctrl HI3660_PCLK>;
201			clock-names = "apb_pclk";
202			cpu = <&cpu6>;
203			arm,coresight-loses-context-with-cpu;
204
205			out-ports {
206				port {
207					etm6_out: endpoint {
208						remote-endpoint =
209							<&cluster1_funnel_in2>;
210					};
211				};
212			};
213		};
214
215		etm@ed740000 {
216			compatible = "arm,coresight-etm4x", "arm,primecell";
217			reg = <0 0xed740000 0 0x1000>;
218			clocks = <&crg_ctrl HI3660_PCLK>;
219			clock-names = "apb_pclk";
220			cpu = <&cpu7>;
221			arm,coresight-loses-context-with-cpu;
222
223			out-ports {
224				port {
225					etm7_out: endpoint {
226						remote-endpoint =
227							<&cluster1_funnel_in3>;
228					};
229				};
230			};
231		};
232
233		funnel@ed001000 {
234			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
235			reg = <0 0xed001000 0 0x1000>;
236			clocks = <&crg_ctrl HI3660_PCLK>;
237			clock-names = "apb_pclk";
238			out-ports {
239				port {
240					cluster1_funnel_out: endpoint {
241						remote-endpoint =
242							<&cluster1_etf_in>;
243					};
244				};
245			};
246
247			in-ports {
248				#address-cells = <1>;
249				#size-cells = <0>;
250
251				port@0 {
252					reg = <0>;
253					cluster1_funnel_in0: endpoint {
254						remote-endpoint = <&etm4_out>;
255					};
256				};
257
258				port@1 {
259					reg = <1>;
260					cluster1_funnel_in1: endpoint {
261						remote-endpoint = <&etm5_out>;
262					};
263				};
264
265				port@2 {
266					reg = <2>;
267					cluster1_funnel_in2: endpoint {
268						remote-endpoint = <&etm6_out>;
269					};
270				};
271
272				port@3 {
273					reg = <3>;
274					cluster1_funnel_in3: endpoint {
275						remote-endpoint = <&etm7_out>;
276					};
277				};
278			};
279		};
280
281		etf@ed002000 {
282			compatible = "arm,coresight-tmc", "arm,primecell";
283			reg = <0 0xed002000 0 0x1000>;
284			clocks = <&crg_ctrl HI3660_PCLK>;
285			clock-names = "apb_pclk";
286
287			in-ports {
288				port {
289					cluster1_etf_in: endpoint {
290						remote-endpoint =
291							<&cluster1_funnel_out>;
292					};
293				};
294			};
295
296			out-ports {
297				port {
298					cluster1_etf_out: endpoint {
299						remote-endpoint =
300							<&combo_funnel_in1>;
301					};
302				};
303			};
304		};
305
306		/* An invisible combo funnel between clusters and top funnel */
307		funnel {
308			compatible = "arm,coresight-static-funnel";
309			clocks = <&crg_ctrl HI3660_PCLK>;
310			clock-names = "apb_pclk";
311
312			out-ports {
313				port {
314					combo_funnel_out: endpoint {
315						remote-endpoint =
316							<&top_funnel_in>;
317					};
318				};
319			};
320
321			in-ports {
322				#address-cells = <1>;
323				#size-cells = <0>;
324
325				port@0 {
326					reg = <0>;
327					combo_funnel_in0: endpoint {
328						remote-endpoint =
329							<&cluster0_etf_out>;
330					};
331				};
332
333				port@1 {
334					reg = <1>;
335					combo_funnel_in1: endpoint {
336						remote-endpoint =
337							<&cluster1_etf_out>;
338					};
339				};
340			};
341		};
342
343		/* Top internals */
344		funnel@ec031000 {
345			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
346			reg = <0 0xec031000 0 0x1000>;
347			clocks = <&crg_ctrl HI3660_PCLK>;
348			clock-names = "apb_pclk";
349
350			out-ports {
351				port {
352					top_funnel_out: endpoint {
353						remote-endpoint =
354							<&top_etf_in>;
355					};
356				};
357			};
358
359			in-ports {
360				#address-cells = <1>;
361				#size-cells = <0>;
362
363				port@0 {
364					reg = <0>;
365					top_funnel_in: endpoint {
366						remote-endpoint =
367							<&combo_funnel_out>;
368					};
369				};
370			};
371		};
372
373		etf@ec036000 {
374			compatible = "arm,coresight-tmc", "arm,primecell";
375			reg = <0 0xec036000 0 0x1000>;
376			clocks = <&crg_ctrl HI3660_PCLK>;
377			clock-names = "apb_pclk";
378
379			in-ports {
380				port {
381					top_etf_in: endpoint {
382						remote-endpoint =
383							<&top_funnel_out>;
384					};
385				};
386			};
387
388			out-ports {
389				port {
390					top_etf_out: endpoint {
391						remote-endpoint =
392							<&replicator_in>;
393					};
394				};
395			};
396		};
397
398		replicator {
399			compatible = "arm,coresight-static-replicator";
400			clocks = <&crg_ctrl HI3660_PCLK>;
401			clock-names = "apb_pclk";
402
403			in-ports {
404				port {
405					replicator_in: endpoint {
406						remote-endpoint =
407							<&top_etf_out>;
408					};
409				};
410			};
411
412			out-ports {
413				#address-cells = <1>;
414				#size-cells = <0>;
415
416				port@0 {
417					reg = <0>;
418					replicator0_out0: endpoint {
419						remote-endpoint = <&etr_in>;
420					};
421				};
422
423				port@1 {
424					reg = <1>;
425					replicator0_out1: endpoint {
426						remote-endpoint = <&tpiu_in>;
427					};
428				};
429			};
430		};
431
432		etr@ec033000 {
433			compatible = "arm,coresight-tmc", "arm,primecell";
434			reg = <0 0xec033000 0 0x1000>;
435			clocks = <&crg_ctrl HI3660_PCLK>;
436			clock-names = "apb_pclk";
437
438			in-ports {
439				port {
440					etr_in: endpoint {
441						remote-endpoint =
442							<&replicator0_out0>;
443					};
444				};
445			};
446		};
447
448		tpiu@ec032000 {
449			compatible = "arm,coresight-tpiu", "arm,primecell";
450			reg = <0 0xec032000 0 0x1000>;
451			clocks = <&crg_ctrl HI3660_PCLK>;
452			clock-names = "apb_pclk";
453
454			in-ports {
455				port {
456					tpiu_in: endpoint {
457						remote-endpoint =
458							<&replicator0_out1>;
459					};
460				};
461			};
462		};
463	};
464};
465