1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright (c) 2022, Arm Limited. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited. All rights reserved.
5 *
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	interrupt-parent = <&gic>;
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	aliases {
16		serial0 = &uart0;
17		serial1 = &uart1;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	cpus: cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu: cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a35";
31			reg = <0>;
32			enable-method = "psci";
33			next-level-cache = <&L2_0>;
34		};
35	};
36
37	memory@88200000 {
38		device_type = "memory";
39		reg = <0x88200000 0x77e00000>;
40	};
41
42	gic: interrupt-controller@1c000000 {
43		compatible = "arm,gic-400";
44		#interrupt-cells = <3>;
45		#address-cells = <0>;
46		interrupt-controller;
47		reg = <0x1c010000 0x1000>,
48		      <0x1c02f000 0x2000>,
49		      <0x1c04f000 0x1000>,
50		      <0x1c06f000 0x2000>;
51		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
52			      IRQ_TYPE_LEVEL_LOW)>;
53	};
54
55	L2_0: l2-cache0 {
56		compatible = "cache";
57		cache-unified;
58		cache-level = <2>;
59		cache-size = <0x80000>;
60		cache-line-size = <64>;
61		cache-sets = <1024>;
62	};
63
64	refclk100mhz: clock-100000000 {
65		compatible = "fixed-clock";
66		#clock-cells = <0>;
67		clock-frequency = <100000000>;
68		clock-output-names = "apb_pclk";
69	};
70
71	smbclk: clock-48000000 {
72		/* Reference 24MHz clock x 2 */
73		compatible = "fixed-clock";
74		#clock-cells = <0>;
75		clock-frequency = <48000000>;
76		clock-output-names = "smclk";
77	};
78
79	timer {
80		compatible = "arm,armv8-timer";
81		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
82			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
83			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
84			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
85	};
86
87	uartclk: clock-50000000 {
88		/* UART clock - 50MHz */
89		compatible = "fixed-clock";
90		#clock-cells = <0>;
91		clock-frequency = <50000000>;
92		clock-output-names = "uartclk";
93	};
94
95	psci {
96		compatible = "arm,psci-1.0", "arm,psci-0.2";
97		method = "smc";
98	};
99
100	soc {
101		compatible = "simple-bus";
102		#address-cells = <1>;
103		#size-cells = <1>;
104		interrupt-parent = <&gic>;
105		ranges;
106
107		timer@1a220000 {
108			compatible = "arm,armv7-timer-mem";
109			reg = <0x1a220000 0x1000>;
110			#address-cells = <1>;
111			#size-cells = <1>;
112			clock-frequency = <50000000>;
113			ranges;
114
115			frame@1a230000 {
116				frame-number = <0>;
117				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
118				reg = <0x1a230000 0x1000>;
119			};
120		};
121
122		uart0: serial@1a510000 {
123			compatible = "arm,pl011", "arm,primecell";
124			reg = <0x1a510000 0x1000>;
125			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
126			clocks = <&uartclk>, <&refclk100mhz>;
127			clock-names = "uartclk", "apb_pclk";
128		};
129
130		uart1: serial@1a520000 {
131			compatible = "arm,pl011", "arm,primecell";
132			reg = <0x1a520000 0x1000>;
133			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
134			clocks = <&uartclk>, <&refclk100mhz>;
135			clock-names = "uartclk", "apb_pclk";
136		};
137
138		mhu_hse1: mailbox@1b820000 {
139			compatible = "arm,mhuv2-tx", "arm,primecell";
140			reg = <0x1b820000 0x1000>;
141			clocks = <&refclk100mhz>;
142			clock-names = "apb_pclk";
143			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
144			#mbox-cells = <2>;
145			arm,mhuv2-protocols = <0 0>;
146			secure-status = "okay";     /* secure-world-only */
147			status = "disabled";
148		};
149
150		mhu_seh1: mailbox@1b830000 {
151			compatible = "arm,mhuv2-rx", "arm,primecell";
152			reg = <0x1b830000 0x1000>;
153			clocks = <&refclk100mhz>;
154			clock-names = "apb_pclk";
155			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
156			#mbox-cells = <2>;
157			arm,mhuv2-protocols = <0 0>;
158			secure-status = "okay";     /* secure-world-only */
159			status = "disabled";
160		};
161	};
162};
163