1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DTS file for AMD Seattle XGBE (RevB)
4 *
5 * Copyright (C) 2015 Advanced Micro Devices, Inc.
6 */
7
8	xgmac0: ethernet@e0700000 {
9		compatible = "amd,xgbe-seattle-v1a";
10		reg = <0 0xe0700000 0 0x80000>,
11		      <0 0xe0780000 0 0x80000>,
12		      <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
13		      <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
14		      <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
15		interrupts = <0 325 4>,
16			     <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
17			     <0 323 4>;
18		amd,per-channel-interrupt;
19		amd,speed-set = <0>;
20		amd,serdes-blwc = <1>, <1>, <0>;
21		amd,serdes-cdr-rate = <2>, <2>, <7>;
22		amd,serdes-pq-skew = <10>, <10>, <18>;
23		amd,serdes-tx-amp = <0>, <0>, <0>;
24		amd,serdes-dfe-tap-config = <3>, <3>, <3>;
25		amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
26		mac-address = [ 02 A1 A2 A3 A4 A5 ];
27		clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
28		clock-names = "dma_clk", "ptp_clk";
29		phy-mode = "xgmii";
30		iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
31		dma-coherent;
32	};
33
34	xgmac1: ethernet@e0900000 {
35		compatible = "amd,xgbe-seattle-v1a";
36		reg = <0 0xe0900000 0 0x80000>,
37		      <0 0xe0980000 0 0x80000>,
38		      <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
39		      <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
40		      <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
41		interrupts = <0 324 4>,
42			     <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
43			     <0 322 4>;
44		amd,per-channel-interrupt;
45		amd,speed-set = <0>;
46		amd,serdes-blwc = <1>, <1>, <0>;
47		amd,serdes-cdr-rate = <2>, <2>, <7>;
48		amd,serdes-pq-skew = <10>, <10>, <18>;
49		amd,serdes-tx-amp = <0>, <0>, <0>;
50		amd,serdes-dfe-tap-config = <3>, <3>, <3>;
51		amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
52		mac-address = [ 02 B1 B2 B3 B4 B5 ];
53		clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
54		clock-names = "dma_clk", "ptp_clk";
55		phy-mode = "xgmii";
56		iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
57		dma-coherent;
58	};
59
60	xgmac0_smmu: iommu@e0600000 {
61		 compatible = "arm,mmu-401";
62		 reg = <0 0xe0600000 0 0x10000>;
63		 #global-interrupts = <1>;
64		 interrupts = /* Uses combined intr for both
65			       * global and context
66			       */
67			      <0 336 4>,
68			      <0 336 4>;
69		#iommu-cells = <2>;
70		dma-coherent;
71	 };
72
73	 xgmac1_smmu: iommu@e0800000 {
74		 compatible = "arm,mmu-401";
75		 reg = <0 0xe0800000 0 0x10000>;
76		 #global-interrupts = <1>;
77		 interrupts = /* Uses combined intr for both
78			       * global and context
79			       */
80			      <0 335 4>,
81			      <0 335 4>;
82		#iommu-cells = <2>;
83		dma-coherent;
84	 };
85