1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-a100-ccu.h> 8#include <dt-bindings/clock/sun50i-a100-r-ccu.h> 9#include <dt-bindings/reset/sun50i-a100-ccu.h> 10#include <dt-bindings/reset/sun50i-a100-r-ccu.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a53"; 23 device_type = "cpu"; 24 reg = <0x0>; 25 enable-method = "psci"; 26 clocks = <&ccu CLK_CPUX>; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 reg = <0x1>; 33 enable-method = "psci"; 34 clocks = <&ccu CLK_CPUX>; 35 }; 36 37 cpu2: cpu@2 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 reg = <0x2>; 41 enable-method = "psci"; 42 clocks = <&ccu CLK_CPUX>; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <0x3>; 49 enable-method = "psci"; 50 clocks = <&ccu CLK_CPUX>; 51 }; 52 }; 53 54 pmu { 55 compatible = "arm,cortex-a53-pmu"; 56 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 61 }; 62 63 psci { 64 compatible = "arm,psci-1.0"; 65 method = "smc"; 66 }; 67 68 dcxo24M: dcxo24M-clk { 69 compatible = "fixed-clock"; 70 clock-frequency = <24000000>; 71 clock-output-names = "dcxo24M"; 72 #clock-cells = <0>; 73 }; 74 75 iosc: internal-osc-clk { 76 compatible = "fixed-clock"; 77 clock-frequency = <16000000>; 78 clock-accuracy = <300000000>; 79 clock-output-names = "iosc"; 80 #clock-cells = <0>; 81 }; 82 83 osc32k: osc32k-clk { 84 compatible = "fixed-clock"; 85 clock-frequency = <32768>; 86 clock-output-names = "osc32k"; 87 #clock-cells = <0>; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupts = <GIC_PPI 13 93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 14 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 11 97 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 10 99 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0 0 0x3fffffff>; 107 108 syscon: syscon@3000000 { 109 compatible = "allwinner,sun50i-a100-system-control", 110 "allwinner,sun50i-a64-system-control"; 111 reg = <0x03000000 0x1000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges; 115 116 sram_a1: sram@20000 { 117 compatible = "mmio-sram"; 118 reg = <0x00020000 0x4000>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges = <0 0x00020000 0x4000>; 122 }; 123 124 sram_c: sram@24000 { 125 compatible = "mmio-sram"; 126 reg = <0x024000 0x21000>; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0 0x024000 0x21000>; 130 }; 131 132 sram_a2: sram@100000 { 133 compatible = "mmio-sram"; 134 reg = <0x0100000 0x14000>; 135 #address-cells = <1>; 136 #size-cells = <1>; 137 ranges = <0 0x0100000 0x14000>; 138 }; 139 }; 140 141 ccu: clock@3001000 { 142 compatible = "allwinner,sun50i-a100-ccu"; 143 reg = <0x03001000 0x1000>; 144 clocks = <&dcxo24M>, <&osc32k>, <&iosc>; 145 clock-names = "hosc", "losc", "iosc"; 146 #clock-cells = <1>; 147 #reset-cells = <1>; 148 }; 149 150 dma: dma-controller@3002000 { 151 compatible = "allwinner,sun50i-a100-dma"; 152 reg = <0x03002000 0x1000>; 153 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 155 clock-names = "bus", "mbus"; 156 resets = <&ccu RST_BUS_DMA>; 157 dma-channels = <8>; 158 dma-requests = <52>; 159 #dma-cells = <1>; 160 }; 161 162 gic: interrupt-controller@3021000 { 163 compatible = "arm,gic-400"; 164 reg = <0x03021000 0x1000>, <0x03022000 0x2000>, 165 <0x03024000 0x2000>, <0x03026000 0x2000>; 166 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 167 IRQ_TYPE_LEVEL_HIGH)>; 168 interrupt-controller; 169 #interrupt-cells = <3>; 170 }; 171 172 efuse@3006000 { 173 compatible = "allwinner,sun50i-a100-sid", 174 "allwinner,sun50i-a64-sid"; 175 reg = <0x03006000 0x1000>; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 179 ths_calibration: calib@14 { 180 reg = <0x14 8>; 181 }; 182 183 cpu_speed_grade: cpu-speed-grade@1c { 184 reg = <0x1c 0x2>; 185 }; 186 }; 187 188 watchdog@30090a0 { 189 compatible = "allwinner,sun50i-a100-wdt", 190 "allwinner,sun6i-a31-wdt"; 191 reg = <0x030090a0 0x20>; 192 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&dcxo24M>; 194 }; 195 196 pio: pinctrl@300b000 { 197 compatible = "allwinner,sun50i-a100-pinctrl"; 198 reg = <0x0300b000 0x400>; 199 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; 207 clock-names = "apb", "hosc", "losc"; 208 gpio-controller; 209 #gpio-cells = <3>; 210 interrupt-controller; 211 #interrupt-cells = <3>; 212 213 mmc0_pins: mmc0-pins { 214 pins = "PF0", "PF1", "PF2", "PF3", 215 "PF4", "PF5"; 216 function = "mmc0"; 217 drive-strength = <30>; 218 bias-pull-up; 219 }; 220 221 /omit-if-no-ref/ 222 mmc1_pins: mmc1-pins { 223 pins = "PG0", "PG1", "PG2", "PG3", 224 "PG4", "PG5"; 225 function = "mmc1"; 226 drive-strength = <30>; 227 bias-pull-up; 228 }; 229 230 mmc2_pins: mmc2-pins { 231 pins = "PC0", "PC1", "PC5", "PC6", 232 "PC8", "PC9", "PC10", "PC11", 233 "PC13", "PC14", "PC15", "PC16"; 234 function = "mmc2"; 235 drive-strength = <30>; 236 bias-pull-up; 237 }; 238 239 uart0_pb_pins: uart0-pb-pins { 240 pins = "PB9", "PB10"; 241 function = "uart0"; 242 }; 243 }; 244 245 mmc0: mmc@4020000 { 246 compatible = "allwinner,sun50i-a100-mmc"; 247 reg = <0x04020000 0x1000>; 248 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 249 clock-names = "ahb", "mmc"; 250 resets = <&ccu RST_BUS_MMC0>; 251 reset-names = "ahb"; 252 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&mmc0_pins>; 255 status = "disabled"; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 }; 259 260 mmc1: mmc@4021000 { 261 compatible = "allwinner,sun50i-a100-mmc"; 262 reg = <0x04021000 0x1000>; 263 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 264 clock-names = "ahb", "mmc"; 265 resets = <&ccu RST_BUS_MMC1>; 266 reset-names = "ahb"; 267 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&mmc1_pins>; 270 status = "disabled"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 }; 274 275 mmc2: mmc@4022000 { 276 compatible = "allwinner,sun50i-a100-emmc"; 277 reg = <0x04022000 0x1000>; 278 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 279 clock-names = "ahb", "mmc"; 280 resets = <&ccu RST_BUS_MMC2>; 281 reset-names = "ahb"; 282 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&mmc2_pins>; 285 status = "disabled"; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 }; 289 290 uart0: serial@5000000 { 291 compatible = "snps,dw-apb-uart"; 292 reg = <0x05000000 0x400>; 293 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 294 reg-shift = <2>; 295 reg-io-width = <4>; 296 clocks = <&ccu CLK_BUS_UART0>; 297 resets = <&ccu RST_BUS_UART0>; 298 status = "disabled"; 299 }; 300 301 uart1: serial@5000400 { 302 compatible = "snps,dw-apb-uart"; 303 reg = <0x05000400 0x400>; 304 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 305 reg-shift = <2>; 306 reg-io-width = <4>; 307 clocks = <&ccu CLK_BUS_UART1>; 308 resets = <&ccu RST_BUS_UART1>; 309 status = "disabled"; 310 }; 311 312 uart2: serial@5000800 { 313 compatible = "snps,dw-apb-uart"; 314 reg = <0x05000800 0x400>; 315 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 316 reg-shift = <2>; 317 reg-io-width = <4>; 318 clocks = <&ccu CLK_BUS_UART2>; 319 resets = <&ccu RST_BUS_UART2>; 320 status = "disabled"; 321 }; 322 323 uart3: serial@5000c00 { 324 compatible = "snps,dw-apb-uart"; 325 reg = <0x05000c00 0x400>; 326 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 327 reg-shift = <2>; 328 reg-io-width = <4>; 329 clocks = <&ccu CLK_BUS_UART3>; 330 resets = <&ccu RST_BUS_UART3>; 331 status = "disabled"; 332 }; 333 334 uart4: serial@5001000 { 335 compatible = "snps,dw-apb-uart"; 336 reg = <0x05001000 0x400>; 337 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 338 reg-shift = <2>; 339 reg-io-width = <4>; 340 clocks = <&ccu CLK_BUS_UART4>; 341 resets = <&ccu RST_BUS_UART4>; 342 status = "disabled"; 343 }; 344 345 i2c0: i2c@5002000 { 346 compatible = "allwinner,sun50i-a100-i2c", 347 "allwinner,sun8i-v536-i2c", 348 "allwinner,sun6i-a31-i2c"; 349 reg = <0x05002000 0x400>; 350 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&ccu CLK_BUS_I2C0>; 352 resets = <&ccu RST_BUS_I2C0>; 353 dmas = <&dma 43>, <&dma 43>; 354 dma-names = "rx", "tx"; 355 status = "disabled"; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 }; 359 360 i2c1: i2c@5002400 { 361 compatible = "allwinner,sun50i-a100-i2c", 362 "allwinner,sun8i-v536-i2c", 363 "allwinner,sun6i-a31-i2c"; 364 reg = <0x05002400 0x400>; 365 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&ccu CLK_BUS_I2C1>; 367 resets = <&ccu RST_BUS_I2C1>; 368 dmas = <&dma 44>, <&dma 44>; 369 dma-names = "rx", "tx"; 370 status = "disabled"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 }; 374 375 i2c2: i2c@5002800 { 376 compatible = "allwinner,sun50i-a100-i2c", 377 "allwinner,sun8i-v536-i2c", 378 "allwinner,sun6i-a31-i2c"; 379 reg = <0x05002800 0x400>; 380 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&ccu CLK_BUS_I2C2>; 382 resets = <&ccu RST_BUS_I2C2>; 383 dmas = <&dma 45>, <&dma 45>; 384 dma-names = "rx", "tx"; 385 status = "disabled"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 }; 389 390 i2c3: i2c@5002c00 { 391 compatible = "allwinner,sun50i-a100-i2c", 392 "allwinner,sun8i-v536-i2c", 393 "allwinner,sun6i-a31-i2c"; 394 reg = <0x05002c00 0x400>; 395 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&ccu CLK_BUS_I2C3>; 397 resets = <&ccu RST_BUS_I2C3>; 398 dmas = <&dma 46>, <&dma 46>; 399 dma-names = "rx", "tx"; 400 status = "disabled"; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 }; 404 405 ths: thermal-sensor@5070400 { 406 compatible = "allwinner,sun50i-a100-ths"; 407 reg = <0x05070400 0x100>; 408 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&ccu CLK_BUS_THS>; 410 clock-names = "bus"; 411 resets = <&ccu RST_BUS_THS>; 412 nvmem-cells = <&ths_calibration>; 413 nvmem-cell-names = "calibration"; 414 #thermal-sensor-cells = <1>; 415 }; 416 417 usb_otg: usb@5100000 { 418 compatible = "allwinner,sun50i-a100-musb", 419 "allwinner,sun8i-a33-musb"; 420 reg = <0x05100000 0x0400>; 421 clocks = <&ccu CLK_BUS_OTG>; 422 resets = <&ccu RST_BUS_OTG>; 423 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 424 interrupt-names = "mc"; 425 phys = <&usbphy 0>; 426 phy-names = "usb"; 427 extcon = <&usbphy 0>; 428 status = "disabled"; 429 }; 430 431 usbphy: phy@5100400 { 432 compatible = "allwinner,sun50i-a100-usb-phy", 433 "allwinner,sun20i-d1-usb-phy"; 434 reg = <0x05100400 0x100>, 435 <0x05101800 0x100>, 436 <0x05200800 0x100>; 437 reg-names = "phy_ctrl", 438 "pmu0", 439 "pmu1"; 440 clocks = <&ccu CLK_USB_PHY0>, 441 <&ccu CLK_USB_PHY1>; 442 clock-names = "usb0_phy", 443 "usb1_phy"; 444 resets = <&ccu RST_USB_PHY0>, 445 <&ccu RST_USB_PHY1>; 446 reset-names = "usb0_reset", 447 "usb1_reset"; 448 status = "disabled"; 449 #phy-cells = <1>; 450 }; 451 452 ehci0: usb@5101000 { 453 compatible = "allwinner,sun50i-a100-ehci", 454 "generic-ehci"; 455 reg = <0x05101000 0x100>; 456 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&ccu CLK_BUS_OHCI0>, 458 <&ccu CLK_BUS_EHCI0>, 459 <&ccu CLK_USB_OHCI0>; 460 resets = <&ccu RST_BUS_OHCI0>, 461 <&ccu RST_BUS_EHCI0>; 462 phys = <&usbphy 0>; 463 phy-names = "usb"; 464 status = "disabled"; 465 }; 466 467 ohci0: usb@5101400 { 468 compatible = "allwinner,sun50i-a100-ohci", 469 "generic-ohci"; 470 reg = <0x05101400 0x100>; 471 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&ccu CLK_BUS_OHCI0>, 473 <&ccu CLK_USB_OHCI0>; 474 resets = <&ccu RST_BUS_OHCI0>; 475 phys = <&usbphy 0>; 476 phy-names = "usb"; 477 status = "disabled"; 478 }; 479 480 ehci1: usb@5200000 { 481 compatible = "allwinner,sun50i-a100-ehci", 482 "generic-ehci"; 483 reg = <0x05200000 0x100>; 484 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&ccu CLK_BUS_OHCI1>, 486 <&ccu CLK_BUS_EHCI1>, 487 <&ccu CLK_USB_OHCI1>; 488 resets = <&ccu RST_BUS_OHCI1>, 489 <&ccu RST_BUS_EHCI1>; 490 phys = <&usbphy 1>; 491 phy-names = "usb"; 492 status = "disabled"; 493 }; 494 495 ohci1: usb@5200400 { 496 compatible = "allwinner,sun50i-a100-ohci", 497 "generic-ohci"; 498 reg = <0x05200400 0x100>; 499 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&ccu CLK_BUS_OHCI1>, 501 <&ccu CLK_USB_OHCI1>; 502 resets = <&ccu RST_BUS_OHCI1>; 503 phys = <&usbphy 1>; 504 phy-names = "usb"; 505 status = "disabled"; 506 }; 507 508 r_ccu: clock@7010000 { 509 compatible = "allwinner,sun50i-a100-r-ccu"; 510 reg = <0x07010000 0x300>; 511 clocks = <&dcxo24M>, <&osc32k>, <&iosc>, 512 <&ccu CLK_PLL_PERIPH0>; 513 clock-names = "hosc", "losc", "iosc", "pll-periph"; 514 #clock-cells = <1>; 515 #reset-cells = <1>; 516 }; 517 518 r_intc: interrupt-controller@7010320 { 519 compatible = "allwinner,sun50i-a100-nmi", 520 "allwinner,sun9i-a80-nmi"; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 reg = <0x07010320 0xc>; 524 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 525 }; 526 527 r_pio: pinctrl@7022000 { 528 compatible = "allwinner,sun50i-a100-r-pinctrl"; 529 reg = <0x07022000 0x400>; 530 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; 532 clock-names = "apb", "hosc", "losc"; 533 gpio-controller; 534 #gpio-cells = <3>; 535 interrupt-controller; 536 #interrupt-cells = <3>; 537 538 r_i2c0_pins: r-i2c0-pins { 539 pins = "PL0", "PL1"; 540 function = "s_i2c0"; 541 }; 542 543 r_i2c1_pins: r-i2c1-pins { 544 pins = "PL8", "PL9"; 545 function = "s_i2c1"; 546 }; 547 }; 548 549 r_uart: serial@7080000 { 550 compatible = "snps,dw-apb-uart"; 551 reg = <0x07080000 0x400>; 552 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 553 reg-shift = <2>; 554 reg-io-width = <4>; 555 clocks = <&r_ccu CLK_R_APB2_UART>; 556 resets = <&r_ccu RST_R_APB2_UART>; 557 status = "disabled"; 558 }; 559 560 r_i2c0: i2c@7081400 { 561 compatible = "allwinner,sun50i-a100-i2c", 562 "allwinner,sun8i-v536-i2c", 563 "allwinner,sun6i-a31-i2c"; 564 reg = <0x07081400 0x400>; 565 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&r_ccu CLK_R_APB2_I2C0>; 567 resets = <&r_ccu RST_R_APB2_I2C0>; 568 dmas = <&dma 50>, <&dma 50>; 569 dma-names = "rx", "tx"; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&r_i2c0_pins>; 572 status = "disabled"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 }; 576 577 r_i2c1: i2c@7081800 { 578 compatible = "allwinner,sun50i-a100-i2c", 579 "allwinner,sun8i-v536-i2c", 580 "allwinner,sun6i-a31-i2c"; 581 reg = <0x07081800 0x400>; 582 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&r_ccu CLK_R_APB2_I2C1>; 584 resets = <&r_ccu RST_R_APB2_I2C1>; 585 dmas = <&dma 51>, <&dma 51>; 586 dma-names = "rx", "tx"; 587 pinctrl-names = "default"; 588 pinctrl-0 = <&r_i2c1_pins>; 589 status = "disabled"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 }; 593 }; 594 595 thermal-zones { 596 cpu-thermal { 597 polling-delay-passive = <0>; 598 polling-delay = <0>; 599 thermal-sensors = <&ths 0>; 600 }; 601 602 ddr-thermal { 603 polling-delay-passive = <0>; 604 polling-delay = <0>; 605 thermal-sensors = <&ths 2>; 606 }; 607 608 gpu-thermal { 609 polling-delay-passive = <0>; 610 polling-delay = <0>; 611 thermal-sensors = <&ths 1>; 612 }; 613 }; 614}; 615