1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
3#include <dt-bindings/interrupt-controller/irq.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/en7523-clk.h>
6#include <dt-bindings/reset/airoha,en7581-reset.h>
7
8/ {
9	interrupt-parent = <&gic>;
10	#address-cells = <2>;
11	#size-cells = <2>;
12
13	reserved-memory {
14		#address-cells = <2>;
15		#size-cells = <2>;
16		ranges;
17
18		npu-binary@84000000 {
19			no-map;
20			reg = <0x0 0x84000000 0x0 0xa00000>;
21		};
22
23		npu-flag@84b0000 {
24			no-map;
25			reg = <0x0 0x84b00000 0x0 0x100000>;
26		};
27
28		npu-pkt@85000000 {
29			no-map;
30			reg = <0x0 0x85000000 0x0 0x1a00000>;
31		};
32
33		npu-phyaddr@86b00000 {
34			no-map;
35			reg = <0x0 0x86b00000 0x0 0x100000>;
36		};
37
38		npu-rxdesc@86d00000 {
39			no-map;
40			reg = <0x0 0x86d00000 0x0 0x100000>;
41		};
42	};
43
44	psci {
45		compatible = "arm,psci-1.0";
46		method = "smc";
47	};
48
49	cpus {
50		#address-cells = <1>;
51		#size-cells = <0>;
52
53		cpu-map {
54			cluster0 {
55				core0 {
56					cpu = <&cpu0>;
57				};
58
59				core1 {
60					cpu = <&cpu1>;
61				};
62
63				core2 {
64					cpu = <&cpu2>;
65				};
66
67				core3 {
68					cpu = <&cpu3>;
69				};
70			};
71		};
72
73		cpu0: cpu@0 {
74			device_type = "cpu";
75			compatible = "arm,cortex-a53";
76			reg = <0x0>;
77			enable-method = "psci";
78			clock-frequency = <80000000>;
79			next-level-cache = <&l2>;
80		};
81
82		cpu1: cpu@1 {
83			device_type = "cpu";
84			compatible = "arm,cortex-a53";
85			reg = <0x1>;
86			enable-method = "psci";
87			clock-frequency = <80000000>;
88			next-level-cache = <&l2>;
89		};
90
91		cpu2: cpu@2 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a53";
94			reg = <0x2>;
95			enable-method = "psci";
96			clock-frequency = <80000000>;
97			next-level-cache = <&l2>;
98		};
99
100		cpu3: cpu@3 {
101			device_type = "cpu";
102			compatible = "arm,cortex-a53";
103			reg = <0x3>;
104			enable-method = "psci";
105			clock-frequency = <80000000>;
106			next-level-cache = <&l2>;
107		};
108
109		l2: l2-cache {
110			compatible = "cache";
111			cache-size = <0x80000>;
112			cache-line-size = <64>;
113			cache-level = <2>;
114			cache-unified;
115		};
116	};
117
118	timer {
119		compatible = "arm,armv8-timer";
120		interrupt-parent = <&gic>;
121		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
122			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
123			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
124			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
125	};
126
127	clk20m: clock-20000000 {
128		compatible = "fixed-clock";
129		#clock-cells = <0>;
130		clock-frequency = <20000000>;
131	};
132
133	soc {
134		compatible = "simple-bus";
135		#address-cells = <2>;
136		#size-cells = <2>;
137		ranges;
138
139		gic: interrupt-controller@9000000 {
140			compatible = "arm,gic-v3";
141			interrupt-controller;
142			#interrupt-cells = <3>;
143			#address-cells = <1>;
144			#size-cells = <1>;
145			reg = <0x0 0x09000000 0x0 0x20000>,
146			      <0x0 0x09080000 0x0 0x80000>,
147			      <0x0 0x09400000 0x0 0x2000>,
148			      <0x0 0x09500000 0x0 0x2000>,
149			      <0x0 0x09600000 0x0 0x20000>;
150			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
151		};
152
153		spi@1fa10000 {
154			compatible = "airoha,en7581-snand";
155			reg = <0x0 0x1fa10000 0x0 0x140>,
156			      <0x0 0x1fa11000 0x0 0x160>;
157
158			clocks = <&scuclk EN7523_CLK_SPI>;
159			clock-names = "spi";
160
161			#address-cells = <1>;
162			#size-cells = <0>;
163
164			status = "disabled";
165
166			spi_nand: nand@0 {
167				compatible = "spi-nand";
168				reg = <0>;
169
170				spi-max-frequency = <50000000>;
171				spi-tx-bus-width = <1>;
172				spi-rx-bus-width = <2>;
173			};
174		};
175
176		scuclk: clock-controller@1fb00000 {
177			compatible = "airoha,en7581-scu";
178			reg = <0x0 0x1fb00000 0x0 0x970>;
179			#clock-cells = <1>;
180			#reset-cells = <1>;
181		};
182
183		uart1: serial@1fbf0000 {
184			compatible = "ns16550";
185			reg = <0x0 0x1fbf0000 0x0 0x30>;
186			reg-io-width = <4>;
187			reg-shift = <2>;
188			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
189			clock-frequency = <1843200>;
190		};
191
192		rng@1faa1000 {
193			compatible = "airoha,en7581-trng";
194			reg = <0x0 0x1faa1000 0x0 0xc04>;
195			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
196		};
197
198		system-controller@1fbf0200 {
199			compatible = "airoha,en7581-gpio-sysctl", "syscon",
200				     "simple-mfd";
201			reg = <0x0 0x1fbf0200 0x0 0xc0>;
202
203			en7581_pinctrl: pinctrl {
204				compatible = "airoha,en7581-pinctrl";
205
206				interrupt-parent = <&gic>;
207				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
208
209				gpio-controller;
210				#gpio-cells = <2>;
211
212				interrupt-controller;
213				#interrupt-cells = <2>;
214			};
215		};
216
217		i2c0: i2c@1fbf8000 {
218			compatible = "mediatek,mt7621-i2c";
219			reg = <0x0 0x1fbf8000 0x0 0x100>;
220
221			resets = <&scuclk EN7581_I2C2_RST>;
222
223			clocks = <&clk20m>;
224			clock-frequency = <100000>;
225			#address-cells = <1>;
226			#size-cells = <0>;
227
228			status = "disabled";
229		};
230
231		i2c1: i2c@1fbf8100 {
232			compatible = "mediatek,mt7621-i2c";
233			reg = <0x0 0x1fbf8100 0x0 0x100>;
234
235			resets = <&scuclk EN7581_I2C_MASTER_RST>;
236
237			clocks = <&clk20m>;
238			clock-frequency = <100000>;
239			#address-cells = <1>;
240			#size-cells = <0>;
241
242			status = "disabled";
243		};
244	};
245};
246