1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 - 2014 Xilinx
4 * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
5 */
6/dts-v1/;
7/include/ "zynq-7000.dtsi"
8
9/ {
10	model = "Avnet MicroZed board";
11	compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
12
13	aliases {
14		serial0 = &uart1;
15		spi0 = &qspi;
16		mmc0 = &sdhci0;
17	};
18
19	memory@0 {
20		device_type = "memory";
21		reg = <0x0 0x40000000>;
22	};
23
24	chosen {
25		bootargs = "earlycon";
26		stdout-path = "serial0:115200n8";
27	};
28
29	usb_phy0: phy0 {
30		compatible = "usb-nop-xceiv";
31		#phy-cells = <0>;
32	};
33};
34
35&clkc {
36	ps-clk-frequency = <33333333>;
37};
38
39&qspi {
40	bootph-all;
41	status = "okay";
42};
43
44&gem0 {
45	status = "okay";
46	phy-mode = "rgmii-id";
47	phy-handle = <&ethernet_phy>;
48
49	ethernet_phy: ethernet-phy@0 {
50		reg = <0>;
51	};
52};
53
54&sdhci0 {
55	bootph-all;
56	status = "okay";
57};
58
59&uart1 {
60	bootph-all;
61	status = "okay";
62};
63
64&usb0 {
65	status = "okay";
66	dr_mode = "host";
67	usb-phy = <&usb_phy0>;
68	pinctrl-names = "default";
69	pinctrl-0 = <&pinctrl_usb0_default>;
70};
71
72&pinctrl0 {
73	pinctrl_usb0_default: usb0-default {
74		mux {
75			groups = "usb0_0_grp";
76			function = "usb0";
77		};
78
79		conf {
80			groups = "usb0_0_grp";
81			slew-rate = <0>;
82			io-standard = <1>;
83		};
84
85		conf-rx {
86			pins = "MIO29", "MIO31", "MIO36";
87			bias-high-impedance;
88		};
89
90		conf-tx {
91			pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
92			       "MIO35", "MIO37", "MIO38", "MIO39";
93			bias-disable;
94		};
95	};
96};
97