1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp13-clks.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23	};
24
25	arm-pmu {
26		compatible = "arm,cortex-a7-pmu";
27		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
28		interrupt-affinity = <&cpu0>;
29		interrupt-parent = <&intc>;
30	};
31
32	firmware {
33		optee {
34			method = "smc";
35			compatible = "linaro,optee-tz";
36			interrupt-parent = <&intc>;
37			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
38		};
39
40		scmi: scmi {
41			compatible = "linaro,scmi-optee";
42			#address-cells = <1>;
43			#size-cells = <0>;
44			linaro,optee-channel-id = <0>;
45
46			scmi_clk: protocol@14 {
47				reg = <0x14>;
48				#clock-cells = <1>;
49			};
50
51			scmi_reset: protocol@16 {
52				reg = <0x16>;
53				#reset-cells = <1>;
54			};
55
56			scmi_voltd: protocol@17 {
57				reg = <0x17>;
58
59				scmi_regu: regulators {
60					#address-cells = <1>;
61					#size-cells = <0>;
62
63					scmi_reg11: regulator@0 {
64						reg = <VOLTD_SCMI_REG11>;
65						regulator-name = "reg11";
66					};
67					scmi_reg18: regulator@1 {
68						reg = <VOLTD_SCMI_REG18>;
69						regulator-name = "reg18";
70					};
71					scmi_usb33: regulator@2 {
72						reg = <VOLTD_SCMI_USB33>;
73						regulator-name = "usb33";
74					};
75				};
76			};
77		};
78	};
79
80	intc: interrupt-controller@a0021000 {
81		compatible = "arm,cortex-a7-gic";
82		#interrupt-cells = <3>;
83		interrupt-controller;
84		reg = <0xa0021000 0x1000>,
85		      <0xa0022000 0x2000>;
86	};
87
88	psci {
89		compatible = "arm,psci-1.0";
90		method = "smc";
91	};
92
93	timer {
94		compatible = "arm,armv7-timer";
95		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
96			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
97			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
98			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
99		interrupt-parent = <&intc>;
100		always-on;
101	};
102
103	thermal-zones {
104		cpu_thermal: cpu-thermal {
105			polling-delay-passive = <0>;
106			polling-delay = <0>;
107			thermal-sensors = <&dts>;
108
109			trips {
110				cpu_alert1: cpu-alert1 {
111					temperature = <85000>;
112					hysteresis = <0>;
113					type = "passive";
114				};
115
116				cpu-crit {
117					temperature = <120000>;
118					hysteresis = <0>;
119					type = "critical";
120				};
121			};
122
123			cooling-maps {
124			};
125		};
126	};
127
128	soc {
129		compatible = "simple-bus";
130		#address-cells = <1>;
131		#size-cells = <1>;
132		interrupt-parent = <&intc>;
133		ranges;
134
135		timers2: timer@40000000 {
136			#address-cells = <1>;
137			#size-cells = <0>;
138			compatible = "st,stm32-timers";
139			reg = <0x40000000 0x400>;
140			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
141			interrupt-names = "global";
142			clocks = <&rcc TIM2_K>;
143			clock-names = "int";
144			dmas = <&dmamux1 18 0x400 0x1>,
145			       <&dmamux1 19 0x400 0x1>,
146			       <&dmamux1 20 0x400 0x1>,
147			       <&dmamux1 21 0x400 0x1>,
148			       <&dmamux1 22 0x400 0x1>;
149			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
150			status = "disabled";
151
152			pwm {
153				compatible = "st,stm32-pwm";
154				#pwm-cells = <3>;
155				status = "disabled";
156			};
157
158			timer@1 {
159				compatible = "st,stm32h7-timer-trigger";
160				reg = <1>;
161				status = "disabled";
162			};
163
164			counter {
165				compatible = "st,stm32-timer-counter";
166				status = "disabled";
167			};
168		};
169
170		timers3: timer@40001000 {
171			#address-cells = <1>;
172			#size-cells = <0>;
173			compatible = "st,stm32-timers";
174			reg = <0x40001000 0x400>;
175			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
176			interrupt-names = "global";
177			clocks = <&rcc TIM3_K>;
178			clock-names = "int";
179			dmas = <&dmamux1 23 0x400 0x1>,
180			       <&dmamux1 24 0x400 0x1>,
181			       <&dmamux1 25 0x400 0x1>,
182			       <&dmamux1 26 0x400 0x1>,
183			       <&dmamux1 27 0x400 0x1>,
184			       <&dmamux1 28 0x400 0x1>;
185			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
186			status = "disabled";
187
188			pwm {
189				compatible = "st,stm32-pwm";
190				#pwm-cells = <3>;
191				status = "disabled";
192			};
193
194			timer@2 {
195				compatible = "st,stm32h7-timer-trigger";
196				reg = <2>;
197				status = "disabled";
198			};
199
200			counter {
201				compatible = "st,stm32-timer-counter";
202				status = "disabled";
203			};
204		};
205
206		timers4: timer@40002000 {
207			#address-cells = <1>;
208			#size-cells = <0>;
209			compatible = "st,stm32-timers";
210			reg = <0x40002000 0x400>;
211			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
212			interrupt-names = "global";
213			clocks = <&rcc TIM4_K>;
214			clock-names = "int";
215			dmas = <&dmamux1 29 0x400 0x1>,
216			       <&dmamux1 30 0x400 0x1>,
217			       <&dmamux1 31 0x400 0x1>,
218			       <&dmamux1 32 0x400 0x1>;
219			dma-names = "ch1", "ch2", "ch3", "up";
220			status = "disabled";
221
222			pwm {
223				compatible = "st,stm32-pwm";
224				#pwm-cells = <3>;
225				status = "disabled";
226			};
227
228			timer@3 {
229				compatible = "st,stm32h7-timer-trigger";
230				reg = <3>;
231				status = "disabled";
232			};
233
234			counter {
235				compatible = "st,stm32-timer-counter";
236				status = "disabled";
237			};
238		};
239
240		timers5: timer@40003000 {
241			#address-cells = <1>;
242			#size-cells = <0>;
243			compatible = "st,stm32-timers";
244			reg = <0x40003000 0x400>;
245			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
246			interrupt-names = "global";
247			clocks = <&rcc TIM5_K>;
248			clock-names = "int";
249			dmas = <&dmamux1 55 0x400 0x1>,
250			       <&dmamux1 56 0x400 0x1>,
251			       <&dmamux1 57 0x400 0x1>,
252			       <&dmamux1 58 0x400 0x1>,
253			       <&dmamux1 59 0x400 0x1>,
254			       <&dmamux1 60 0x400 0x1>;
255			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
256			status = "disabled";
257
258			pwm {
259				compatible = "st,stm32-pwm";
260				#pwm-cells = <3>;
261				status = "disabled";
262			};
263
264			timer@4 {
265				compatible = "st,stm32h7-timer-trigger";
266				reg = <4>;
267				status = "disabled";
268			};
269
270			counter {
271				compatible = "st,stm32-timer-counter";
272				status = "disabled";
273			};
274		};
275
276		timers6: timer@40004000 {
277			#address-cells = <1>;
278			#size-cells = <0>;
279			compatible = "st,stm32-timers";
280			reg = <0x40004000 0x400>;
281			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
282			interrupt-names = "global";
283			clocks = <&rcc TIM6_K>;
284			clock-names = "int";
285			dmas = <&dmamux1 69 0x400 0x1>;
286			dma-names = "up";
287			status = "disabled";
288
289			counter {
290				compatible = "st,stm32-timer-counter";
291				status = "disabled";
292			};
293
294			timer@5 {
295				compatible = "st,stm32h7-timer-trigger";
296				reg = <5>;
297				status = "disabled";
298			};
299		};
300
301		timers7: timer@40005000 {
302			#address-cells = <1>;
303			#size-cells = <0>;
304			compatible = "st,stm32-timers";
305			reg = <0x40005000 0x400>;
306			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
307			interrupt-names = "global";
308			clocks = <&rcc TIM7_K>;
309			clock-names = "int";
310			dmas = <&dmamux1 70 0x400 0x1>;
311			dma-names = "up";
312			status = "disabled";
313
314			counter {
315				compatible = "st,stm32-timer-counter";
316				status = "disabled";
317			};
318
319			timer@6 {
320				compatible = "st,stm32h7-timer-trigger";
321				reg = <6>;
322				status = "disabled";
323			};
324		};
325
326		lptimer1: timer@40009000 {
327			#address-cells = <1>;
328			#size-cells = <0>;
329			compatible = "st,stm32-lptimer";
330			reg = <0x40009000 0x400>;
331			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
332			clocks = <&rcc LPTIM1_K>;
333			clock-names = "mux";
334			wakeup-source;
335			status = "disabled";
336
337			pwm {
338				compatible = "st,stm32-pwm-lp";
339				#pwm-cells = <3>;
340				status = "disabled";
341			};
342
343			trigger@0 {
344				compatible = "st,stm32-lptimer-trigger";
345				reg = <0>;
346				status = "disabled";
347			};
348
349			counter {
350				compatible = "st,stm32-lptimer-counter";
351				status = "disabled";
352			};
353
354			timer {
355				compatible = "st,stm32-lptimer-timer";
356				status = "disabled";
357			};
358		};
359
360		i2s2: audio-controller@4000b000 {
361			compatible = "st,stm32h7-i2s";
362			reg = <0x4000b000 0x400>;
363			#sound-dai-cells = <0>;
364			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
365			dmas = <&dmamux1 39 0x400 0x01>,
366			       <&dmamux1 40 0x400 0x01>;
367			dma-names = "rx", "tx";
368			status = "disabled";
369		};
370
371		spi2: spi@4000b000 {
372			compatible = "st,stm32h7-spi";
373			reg = <0x4000b000 0x400>;
374			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
375			clocks = <&rcc SPI2_K>;
376			resets = <&rcc SPI2_R>;
377			#address-cells = <1>;
378			#size-cells = <0>;
379			dmas = <&dmamux1 39 0x400 0x01>,
380			       <&dmamux1 40 0x400 0x01>;
381			dma-names = "rx", "tx";
382			status = "disabled";
383		};
384
385		i2s3: audio-controller@4000c000 {
386			compatible = "st,stm32h7-i2s";
387			reg = <0x4000c000 0x400>;
388			#sound-dai-cells = <0>;
389			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
390			dmas = <&dmamux1 61 0x400 0x01>,
391			       <&dmamux1 62 0x400 0x01>;
392			dma-names = "rx", "tx";
393			status = "disabled";
394		};
395
396		spi3: spi@4000c000 {
397			compatible = "st,stm32h7-spi";
398			reg = <0x4000c000 0x400>;
399			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
400			clocks = <&rcc SPI3_K>;
401			resets = <&rcc SPI3_R>;
402			#address-cells = <1>;
403			#size-cells = <0>;
404			dmas = <&dmamux1 61 0x400 0x01>,
405			       <&dmamux1 62 0x400 0x01>;
406			dma-names = "rx", "tx";
407			status = "disabled";
408		};
409
410		spdifrx: audio-controller@4000d000 {
411			compatible = "st,stm32h7-spdifrx";
412			reg = <0x4000d000 0x400>;
413			#sound-dai-cells = <0>;
414			clocks = <&rcc SPDIF_K>;
415			clock-names = "kclk";
416			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
417			dmas = <&dmamux1 93 0x400 0x01>,
418			       <&dmamux1 94 0x400 0x01>;
419			dma-names = "rx", "rx-ctrl";
420			status = "disabled";
421		};
422
423		usart3: serial@4000f000 {
424			compatible = "st,stm32h7-uart";
425			reg = <0x4000f000 0x400>;
426			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
427			clocks = <&rcc USART3_K>;
428			resets = <&rcc USART3_R>;
429			wakeup-source;
430			dmas = <&dmamux1 45 0x400 0x5>,
431			       <&dmamux1 46 0x400 0x1>;
432			dma-names = "rx", "tx";
433			status = "disabled";
434		};
435
436		uart4: serial@40010000 {
437			compatible = "st,stm32h7-uart";
438			reg = <0x40010000 0x400>;
439			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
440			clocks = <&rcc UART4_K>;
441			resets = <&rcc UART4_R>;
442			wakeup-source;
443			dmas = <&dmamux1 63 0x400 0x5>,
444			       <&dmamux1 64 0x400 0x1>;
445			dma-names = "rx", "tx";
446			status = "disabled";
447		};
448
449		uart5: serial@40011000 {
450			compatible = "st,stm32h7-uart";
451			reg = <0x40011000 0x400>;
452			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
453			clocks = <&rcc UART5_K>;
454			resets = <&rcc UART5_R>;
455			wakeup-source;
456			dmas = <&dmamux1 65 0x400 0x5>,
457			       <&dmamux1 66 0x400 0x1>;
458			dma-names = "rx", "tx";
459			status = "disabled";
460		};
461
462		i2c1: i2c@40012000 {
463			compatible = "st,stm32mp13-i2c";
464			reg = <0x40012000 0x400>;
465			interrupt-names = "event", "error";
466			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
467				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
468			clocks = <&rcc I2C1_K>;
469			resets = <&rcc I2C1_R>;
470			#address-cells = <1>;
471			#size-cells = <0>;
472			dmas = <&dmamux1 33 0x400 0x1>,
473			       <&dmamux1 34 0x400 0x1>;
474			dma-names = "rx", "tx";
475			st,syscfg-fmp = <&syscfg 0x4 0x1>;
476			i2c-analog-filter;
477			status = "disabled";
478		};
479
480		i2c2: i2c@40013000 {
481			compatible = "st,stm32mp13-i2c";
482			reg = <0x40013000 0x400>;
483			interrupt-names = "event", "error";
484			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
485				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
486			clocks = <&rcc I2C2_K>;
487			resets = <&rcc I2C2_R>;
488			#address-cells = <1>;
489			#size-cells = <0>;
490			dmas = <&dmamux1 35 0x400 0x1>,
491			       <&dmamux1 36 0x400 0x1>;
492			dma-names = "rx", "tx";
493			st,syscfg-fmp = <&syscfg 0x4 0x2>;
494			i2c-analog-filter;
495			status = "disabled";
496		};
497
498		uart7: serial@40018000 {
499			compatible = "st,stm32h7-uart";
500			reg = <0x40018000 0x400>;
501			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
502			clocks = <&rcc UART7_K>;
503			resets = <&rcc UART7_R>;
504			wakeup-source;
505			dmas = <&dmamux1 79 0x400 0x5>,
506			       <&dmamux1 80 0x400 0x1>;
507			dma-names = "rx", "tx";
508			status = "disabled";
509		};
510
511		uart8: serial@40019000 {
512			compatible = "st,stm32h7-uart";
513			reg = <0x40019000 0x400>;
514			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
515			clocks = <&rcc UART8_K>;
516			resets = <&rcc UART8_R>;
517			wakeup-source;
518			dmas = <&dmamux1 81 0x400 0x5>,
519			       <&dmamux1 82 0x400 0x1>;
520			dma-names = "rx", "tx";
521			status = "disabled";
522		};
523
524		timers1: timer@44000000 {
525			#address-cells = <1>;
526			#size-cells = <0>;
527			compatible = "st,stm32-timers";
528			reg = <0x44000000 0x400>;
529			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
530				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
531				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
532				     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
533			interrupt-names = "brk", "up", "trg-com", "cc";
534			clocks = <&rcc TIM1_K>;
535			clock-names = "int";
536			dmas = <&dmamux1 11 0x400 0x1>,
537			       <&dmamux1 12 0x400 0x1>,
538			       <&dmamux1 13 0x400 0x1>,
539			       <&dmamux1 14 0x400 0x1>,
540			       <&dmamux1 15 0x400 0x1>,
541			       <&dmamux1 16 0x400 0x1>,
542			       <&dmamux1 17 0x400 0x1>;
543			dma-names = "ch1", "ch2", "ch3", "ch4",
544				    "up", "trig", "com";
545			status = "disabled";
546
547			pwm {
548				compatible = "st,stm32-pwm";
549				#pwm-cells = <3>;
550				status = "disabled";
551			};
552
553			timer@0 {
554				compatible = "st,stm32h7-timer-trigger";
555				reg = <0>;
556				status = "disabled";
557			};
558
559			counter {
560				compatible = "st,stm32-timer-counter";
561				status = "disabled";
562			};
563		};
564
565		timers8: timer@44001000 {
566			#address-cells = <1>;
567			#size-cells = <0>;
568			compatible = "st,stm32-timers";
569			reg = <0x44001000 0x400>;
570			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
571				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
572				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
573				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
574			interrupt-names = "brk", "up", "trg-com", "cc";
575			clocks = <&rcc TIM8_K>;
576			clock-names = "int";
577			dmas = <&dmamux1 47 0x400 0x1>,
578			       <&dmamux1 48 0x400 0x1>,
579			       <&dmamux1 49 0x400 0x1>,
580			       <&dmamux1 50 0x400 0x1>,
581			       <&dmamux1 51 0x400 0x1>,
582			       <&dmamux1 52 0x400 0x1>,
583			       <&dmamux1 53 0x400 0x1>;
584			dma-names = "ch1", "ch2", "ch3", "ch4",
585				    "up", "trig", "com";
586			status = "disabled";
587
588			pwm {
589				compatible = "st,stm32-pwm";
590				#pwm-cells = <3>;
591				status = "disabled";
592			};
593
594			timer@7 {
595				compatible = "st,stm32h7-timer-trigger";
596				reg = <7>;
597				status = "disabled";
598			};
599
600			counter {
601				compatible = "st,stm32-timer-counter";
602				status = "disabled";
603			};
604		};
605
606		usart6: serial@44003000 {
607			compatible = "st,stm32h7-uart";
608			reg = <0x44003000 0x400>;
609			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
610			clocks = <&rcc USART6_K>;
611			resets = <&rcc USART6_R>;
612			wakeup-source;
613			dmas = <&dmamux1 71 0x400 0x5>,
614			       <&dmamux1 72 0x400 0x1>;
615			dma-names = "rx", "tx";
616			status = "disabled";
617		};
618
619		i2s1: audio-controller@44004000 {
620			compatible = "st,stm32h7-i2s";
621			reg = <0x44004000 0x400>;
622			#sound-dai-cells = <0>;
623			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
624			dmas = <&dmamux1 37 0x400 0x01>,
625			       <&dmamux1 38 0x400 0x01>;
626			dma-names = "rx", "tx";
627			status = "disabled";
628		};
629
630		spi1: spi@44004000 {
631			compatible = "st,stm32h7-spi";
632			reg = <0x44004000 0x400>;
633			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
634			clocks = <&rcc SPI1_K>;
635			resets = <&rcc SPI1_R>;
636			#address-cells = <1>;
637			#size-cells = <0>;
638			dmas = <&dmamux1 37 0x400 0x01>,
639			       <&dmamux1 38 0x400 0x01>;
640			dma-names = "rx", "tx";
641			status = "disabled";
642		};
643
644		sai1: sai@4400a000 {
645			compatible = "st,stm32h7-sai";
646			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
647			ranges = <0 0x4400a000 0x400>;
648			#address-cells = <1>;
649			#size-cells = <1>;
650			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
651			resets = <&rcc SAI1_R>;
652			status = "disabled";
653
654			sai1a: audio-controller@4400a004 {
655				compatible = "st,stm32-sai-sub-a";
656				reg = <0x4 0x20>;
657				#sound-dai-cells = <0>;
658				clocks = <&rcc SAI1_K>;
659				clock-names = "sai_ck";
660				dmas = <&dmamux1 87 0x400 0x01>;
661				status = "disabled";
662			};
663
664			sai1b: audio-controller@4400a024 {
665				compatible = "st,stm32-sai-sub-b";
666				reg = <0x24 0x20>;
667				#sound-dai-cells = <0>;
668				clocks = <&rcc SAI1_K>;
669				clock-names = "sai_ck";
670				dmas = <&dmamux1 88 0x400 0x01>;
671				status = "disabled";
672			};
673		};
674
675		sai2: sai@4400b000 {
676			compatible = "st,stm32h7-sai";
677			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
678			ranges = <0 0x4400b000 0x400>;
679			#address-cells = <1>;
680			#size-cells = <1>;
681			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
682			resets = <&rcc SAI2_R>;
683			status = "disabled";
684
685			sai2a: audio-controller@4400b004 {
686				compatible = "st,stm32-sai-sub-a";
687				reg = <0x4 0x20>;
688				#sound-dai-cells = <0>;
689				clocks = <&rcc SAI2_K>;
690				clock-names = "sai_ck";
691				dmas = <&dmamux1 89 0x400 0x01>;
692				status = "disabled";
693			};
694
695			sai2b: audio-controller@4400b024 {
696				compatible = "st,stm32-sai-sub-b";
697				reg = <0x24 0x20>;
698				#sound-dai-cells = <0>;
699				clocks = <&rcc SAI2_K>;
700				clock-names = "sai_ck";
701				dmas = <&dmamux1 90 0x400 0x01>;
702				status = "disabled";
703			};
704		};
705
706		dfsdm: dfsdm@4400d000 {
707			compatible = "st,stm32mp1-dfsdm";
708			reg = <0x4400d000 0x800>;
709			clocks = <&rcc DFSDM_K>;
710			clock-names = "dfsdm";
711			#address-cells = <1>;
712			#size-cells = <0>;
713			status = "disabled";
714
715			dfsdm0: filter@0 {
716				compatible = "st,stm32-dfsdm-adc";
717				reg = <0>;
718				#io-channel-cells = <1>;
719				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
720				dmas = <&dmamux1 101 0x400 0x01>;
721				dma-names = "rx";
722				status = "disabled";
723			};
724
725			dfsdm1: filter@1 {
726				compatible = "st,stm32-dfsdm-adc";
727				reg = <1>;
728				#io-channel-cells = <1>;
729				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
730				dmas = <&dmamux1 102 0x400 0x01>;
731				dma-names = "rx";
732				status = "disabled";
733			};
734		};
735
736		dma1: dma-controller@48000000 {
737			compatible = "st,stm32-dma";
738			reg = <0x48000000 0x400>;
739			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
740				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
741				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
742				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
743				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
744				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
745				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
746				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
747			clocks = <&rcc DMA1>;
748			resets = <&rcc DMA1_R>;
749			#dma-cells = <4>;
750			st,mem2mem;
751			dma-requests = <8>;
752		};
753
754		dma2: dma-controller@48001000 {
755			compatible = "st,stm32-dma";
756			reg = <0x48001000 0x400>;
757			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
758				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
759				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
760				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
761				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
762				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
763				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
764				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
765			clocks = <&rcc DMA2>;
766			resets = <&rcc DMA2_R>;
767			#dma-cells = <4>;
768			st,mem2mem;
769			dma-requests = <8>;
770		};
771
772		dmamux1: dma-router@48002000 {
773			compatible = "st,stm32h7-dmamux";
774			reg = <0x48002000 0x40>;
775			clocks = <&rcc DMAMUX1>;
776			resets = <&rcc DMAMUX1_R>;
777			#dma-cells = <3>;
778			dma-masters = <&dma1 &dma2>;
779			dma-requests = <128>;
780			dma-channels = <16>;
781		};
782
783		rcc: rcc@50000000 {
784			compatible = "st,stm32mp13-rcc", "syscon";
785			reg = <0x50000000 0x1000>;
786			#clock-cells = <1>;
787			#reset-cells = <1>;
788			clock-names = "hse", "hsi", "csi", "lse", "lsi";
789			clocks = <&scmi_clk CK_SCMI_HSE>,
790				 <&scmi_clk CK_SCMI_HSI>,
791				 <&scmi_clk CK_SCMI_CSI>,
792				 <&scmi_clk CK_SCMI_LSE>,
793				 <&scmi_clk CK_SCMI_LSI>;
794		};
795
796		pwr_regulators: pwr@50001000 {
797			compatible = "st,stm32mp1,pwr-reg";
798			reg = <0x50001000 0x10>;
799			status = "disabled";
800
801			reg11: reg11 {
802				regulator-name = "reg11";
803				regulator-min-microvolt = <1100000>;
804				regulator-max-microvolt = <1100000>;
805			};
806
807			reg18: reg18 {
808				regulator-name = "reg18";
809				regulator-min-microvolt = <1800000>;
810				regulator-max-microvolt = <1800000>;
811			};
812
813			usb33: usb33 {
814				regulator-name = "usb33";
815				regulator-min-microvolt = <3300000>;
816				regulator-max-microvolt = <3300000>;
817			};
818		};
819
820		exti: interrupt-controller@5000d000 {
821			compatible = "st,stm32mp1-exti", "syscon";
822			interrupt-controller;
823			#interrupt-cells = <2>;
824			reg = <0x5000d000 0x400>;
825			interrupts-extended =
826				<&intc GIC_SPI 6   IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_0 */
827				<&intc GIC_SPI 7   IRQ_TYPE_LEVEL_HIGH>,
828				<&intc GIC_SPI 8   IRQ_TYPE_LEVEL_HIGH>,
829				<&intc GIC_SPI 9   IRQ_TYPE_LEVEL_HIGH>,
830				<&intc GIC_SPI 10  IRQ_TYPE_LEVEL_HIGH>,
831				<&intc GIC_SPI 24  IRQ_TYPE_LEVEL_HIGH>,
832				<&intc GIC_SPI 65  IRQ_TYPE_LEVEL_HIGH>,
833				<&intc GIC_SPI 66  IRQ_TYPE_LEVEL_HIGH>,
834				<&intc GIC_SPI 67  IRQ_TYPE_LEVEL_HIGH>,
835				<&intc GIC_SPI 68  IRQ_TYPE_LEVEL_HIGH>,
836				<&intc GIC_SPI 41  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_10 */
837				<&intc GIC_SPI 43  IRQ_TYPE_LEVEL_HIGH>,
838				<&intc GIC_SPI 77  IRQ_TYPE_LEVEL_HIGH>,
839				<&intc GIC_SPI 78  IRQ_TYPE_LEVEL_HIGH>,
840				<&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
841				<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
842				<&intc GIC_SPI 1   IRQ_TYPE_LEVEL_HIGH>,
843				<0>,
844				<0>,
845				<&intc GIC_SPI 3   IRQ_TYPE_LEVEL_HIGH>,
846				<0>,						/* EXTI_20 */
847				<&intc GIC_SPI 32  IRQ_TYPE_LEVEL_HIGH>,
848				<&intc GIC_SPI 34  IRQ_TYPE_LEVEL_HIGH>,
849				<&intc GIC_SPI 73  IRQ_TYPE_LEVEL_HIGH>,
850				<&intc GIC_SPI 93  IRQ_TYPE_LEVEL_HIGH>,
851				<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
852				<&intc GIC_SPI 38  IRQ_TYPE_LEVEL_HIGH>,
853				<&intc GIC_SPI 39  IRQ_TYPE_LEVEL_HIGH>,
854				<&intc GIC_SPI 40  IRQ_TYPE_LEVEL_HIGH>,
855				<&intc GIC_SPI 72  IRQ_TYPE_LEVEL_HIGH>,
856				<&intc GIC_SPI 53  IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_30 */
857				<&intc GIC_SPI 54  IRQ_TYPE_LEVEL_HIGH>,
858				<&intc GIC_SPI 83  IRQ_TYPE_LEVEL_HIGH>,
859				<&intc GIC_SPI 84  IRQ_TYPE_LEVEL_HIGH>,
860				<0>,
861				<0>,
862				<0>,
863				<0>,
864				<0>,
865				<0>,
866				<0>,						/* EXTI_40 */
867				<0>,
868				<0>,
869				<0>,
870				<&intc GIC_SPI 96  IRQ_TYPE_LEVEL_HIGH>,
871				<0>,
872				<0>,
873				<&intc GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
874				<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
875				<0>,
876				<&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,	/* EXTI_50 */
877				<0>,
878				<&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
879				<&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
880				<0>,
881				<0>,
882				<0>,
883				<0>,
884				<0>,
885				<0>,
886				<0>,						/* EXTI_60 */
887				<0>,
888				<0>,
889				<0>,
890				<0>,
891				<0>,
892				<0>,
893				<0>,
894				<&intc GIC_SPI 63  IRQ_TYPE_LEVEL_HIGH>,
895				<0>,
896				<&intc GIC_SPI 98  IRQ_TYPE_LEVEL_HIGH>;	/* EXTI_70 */
897		};
898
899		syscfg: syscon@50020000 {
900			compatible = "st,stm32mp157-syscfg", "syscon";
901			reg = <0x50020000 0x400>;
902			clocks = <&rcc SYSCFG>;
903		};
904
905		lptimer4: timer@50023000 {
906			compatible = "st,stm32-lptimer";
907			reg = <0x50023000 0x400>;
908			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
909			clocks = <&rcc LPTIM4_K>;
910			clock-names = "mux";
911			wakeup-source;
912			status = "disabled";
913
914			pwm {
915				compatible = "st,stm32-pwm-lp";
916				#pwm-cells = <3>;
917				status = "disabled";
918			};
919
920			timer {
921				compatible = "st,stm32-lptimer-timer";
922				status = "disabled";
923			};
924		};
925
926		lptimer5: timer@50024000 {
927			compatible = "st,stm32-lptimer";
928			reg = <0x50024000 0x400>;
929			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
930			clocks = <&rcc LPTIM5_K>;
931			clock-names = "mux";
932			wakeup-source;
933			status = "disabled";
934
935			pwm {
936				compatible = "st,stm32-pwm-lp";
937				#pwm-cells = <3>;
938				status = "disabled";
939			};
940
941			timer {
942				compatible = "st,stm32-lptimer-timer";
943				status = "disabled";
944			};
945		};
946
947		dts: thermal@50028000 {
948			compatible = "st,stm32-thermal";
949			reg = <0x50028000 0x100>;
950			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
951			clocks = <&rcc DTS>;
952			clock-names = "pclk";
953			#thermal-sensor-cells = <0>;
954			status = "disabled";
955		};
956
957		mdma: dma-controller@58000000 {
958			compatible = "st,stm32h7-mdma";
959			reg = <0x58000000 0x1000>;
960			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
961			clocks = <&rcc MDMA>;
962			#dma-cells = <5>;
963			dma-channels = <32>;
964			dma-requests = <48>;
965		};
966
967		crc1: crc@58009000 {
968			compatible = "st,stm32f7-crc";
969			reg = <0x58009000 0x400>;
970			clocks = <&rcc CRC1>;
971			status = "disabled";
972		};
973
974		usbh_ohci: usb@5800c000 {
975			compatible = "generic-ohci";
976			reg = <0x5800c000 0x1000>;
977			clocks = <&usbphyc>, <&rcc USBH>;
978			resets = <&rcc USBH_R>;
979			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
980			status = "disabled";
981		};
982
983		usbh_ehci: usb@5800d000 {
984			compatible = "generic-ehci";
985			reg = <0x5800d000 0x1000>;
986			clocks = <&usbphyc>, <&rcc USBH>;
987			resets = <&rcc USBH_R>;
988			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
989			companion = <&usbh_ohci>;
990			status = "disabled";
991		};
992
993		iwdg2: watchdog@5a002000 {
994			compatible = "st,stm32mp1-iwdg";
995			reg = <0x5a002000 0x400>;
996			clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
997			clock-names = "pclk", "lsi";
998			status = "disabled";
999		};
1000
1001		rtc: rtc@5c004000 {
1002			compatible = "st,stm32mp1-rtc";
1003			reg = <0x5c004000 0x400>;
1004			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1005			clocks = <&scmi_clk CK_SCMI_RTCAPB>,
1006				 <&scmi_clk CK_SCMI_RTC>;
1007			clock-names = "pclk", "rtc_ck";
1008			status = "disabled";
1009		};
1010
1011		bsec: efuse@5c005000 {
1012			compatible = "st,stm32mp13-bsec";
1013			reg = <0x5c005000 0x400>;
1014			#address-cells = <1>;
1015			#size-cells = <1>;
1016
1017			part_number_otp: part_number_otp@4 {
1018				reg = <0x4 0x2>;
1019				bits = <0 12>;
1020			};
1021			ts_cal1: calib@5c {
1022				reg = <0x5c 0x2>;
1023			};
1024			ts_cal2: calib@5e {
1025				reg = <0x5e 0x2>;
1026			};
1027			ethernet_mac1_address: mac1@e4 {
1028				reg = <0xe4 0x6>;
1029			};
1030			ethernet_mac2_address: mac2@ea {
1031				reg = <0xea 0x6>;
1032			};
1033		};
1034
1035		etzpc: bus@5c007000 {
1036			compatible = "st,stm32-etzpc", "simple-bus";
1037			reg = <0x5c007000 0x400>;
1038			#address-cells = <1>;
1039			#size-cells = <1>;
1040			#access-controller-cells = <1>;
1041			ranges;
1042
1043			adc_2: adc@48004000 {
1044				compatible = "st,stm32mp13-adc-core";
1045				reg = <0x48004000 0x400>;
1046				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1047				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
1048				clock-names = "bus", "adc";
1049				interrupt-controller;
1050				#interrupt-cells = <1>;
1051				#address-cells = <1>;
1052				#size-cells = <0>;
1053				access-controllers = <&etzpc 33>;
1054				status = "disabled";
1055
1056				adc2: adc@0 {
1057					compatible = "st,stm32mp13-adc";
1058					#io-channel-cells = <1>;
1059					#address-cells = <1>;
1060					#size-cells = <0>;
1061					reg = <0x0>;
1062					interrupt-parent = <&adc_2>;
1063					interrupts = <0>;
1064					dmas = <&dmamux1 10 0x400 0x80000001>;
1065					dma-names = "rx";
1066					status = "disabled";
1067
1068					channel@13 {
1069						reg = <13>;
1070						label = "vrefint";
1071					};
1072					channel@14 {
1073						reg = <14>;
1074						label = "vddcore";
1075					};
1076					channel@16 {
1077						reg = <16>;
1078						label = "vddcpu";
1079					};
1080					channel@17 {
1081						reg = <17>;
1082						label = "vddq_ddr";
1083					};
1084				};
1085			};
1086
1087			usbotg_hs: usb@49000000 {
1088				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1089				reg = <0x49000000 0x40000>;
1090				clocks = <&rcc USBO_K>;
1091				clock-names = "otg";
1092				resets = <&rcc USBO_R>;
1093				reset-names = "dwc2";
1094				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1095				g-rx-fifo-size = <512>;
1096				g-np-tx-fifo-size = <32>;
1097				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1098				dr_mode = "otg";
1099				otg-rev = <0x200>;
1100				usb33d-supply = <&scmi_usb33>;
1101				access-controllers = <&etzpc 34>;
1102				status = "disabled";
1103			};
1104
1105			usart1: serial@4c000000 {
1106				compatible = "st,stm32h7-uart";
1107				reg = <0x4c000000 0x400>;
1108				interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1109				clocks = <&rcc USART1_K>;
1110				resets = <&rcc USART1_R>;
1111				wakeup-source;
1112				dmas = <&dmamux1 41 0x400 0x5>,
1113				<&dmamux1 42 0x400 0x1>;
1114				dma-names = "rx", "tx";
1115				access-controllers = <&etzpc 16>;
1116				status = "disabled";
1117			};
1118
1119			usart2: serial@4c001000 {
1120				compatible = "st,stm32h7-uart";
1121				reg = <0x4c001000 0x400>;
1122				interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
1123				clocks = <&rcc USART2_K>;
1124				resets = <&rcc USART2_R>;
1125				wakeup-source;
1126				dmas = <&dmamux1 43 0x400 0x5>,
1127				<&dmamux1 44 0x400 0x1>;
1128				dma-names = "rx", "tx";
1129				access-controllers = <&etzpc 17>;
1130				status = "disabled";
1131			};
1132
1133			i2s4: audio-controller@4c002000 {
1134				compatible = "st,stm32h7-i2s";
1135				reg = <0x4c002000 0x400>;
1136				#sound-dai-cells = <0>;
1137				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1138				dmas = <&dmamux1 83 0x400 0x01>,
1139				<&dmamux1 84 0x400 0x01>;
1140				dma-names = "rx", "tx";
1141				access-controllers = <&etzpc 13>;
1142				status = "disabled";
1143			};
1144
1145			spi4: spi@4c002000 {
1146				compatible = "st,stm32h7-spi";
1147				reg = <0x4c002000 0x400>;
1148				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1149				clocks = <&rcc SPI4_K>;
1150				resets = <&rcc SPI4_R>;
1151				#address-cells = <1>;
1152				#size-cells = <0>;
1153				dmas = <&dmamux1 83 0x400 0x01>,
1154				       <&dmamux1 84 0x400 0x01>;
1155				dma-names = "rx", "tx";
1156				access-controllers = <&etzpc 18>;
1157				status = "disabled";
1158			};
1159
1160			spi5: spi@4c003000 {
1161				compatible = "st,stm32h7-spi";
1162				reg = <0x4c003000 0x400>;
1163				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1164				clocks = <&rcc SPI5_K>;
1165				resets = <&rcc SPI5_R>;
1166				#address-cells = <1>;
1167				#size-cells = <0>;
1168				dmas = <&dmamux1 85 0x400 0x01>,
1169				       <&dmamux1 86 0x400 0x01>;
1170				dma-names = "rx", "tx";
1171				access-controllers = <&etzpc 19>;
1172				status = "disabled";
1173			};
1174
1175			i2c3: i2c@4c004000 {
1176				compatible = "st,stm32mp13-i2c";
1177				reg = <0x4c004000 0x400>;
1178				interrupt-names = "event", "error";
1179				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1180					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1181				clocks = <&rcc I2C3_K>;
1182				resets = <&rcc I2C3_R>;
1183				#address-cells = <1>;
1184				#size-cells = <0>;
1185				dmas = <&dmamux1 73 0x400 0x1>,
1186				       <&dmamux1 74 0x400 0x1>;
1187				dma-names = "rx", "tx";
1188				st,syscfg-fmp = <&syscfg 0x4 0x4>;
1189				i2c-analog-filter;
1190				access-controllers = <&etzpc 20>;
1191				status = "disabled";
1192			};
1193
1194			i2c4: i2c@4c005000 {
1195				compatible = "st,stm32mp13-i2c";
1196				reg = <0x4c005000 0x400>;
1197				interrupt-names = "event", "error";
1198				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1199					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1200				clocks = <&rcc I2C4_K>;
1201				resets = <&rcc I2C4_R>;
1202				#address-cells = <1>;
1203				#size-cells = <0>;
1204				dmas = <&dmamux1 75 0x400 0x1>,
1205				       <&dmamux1 76 0x400 0x1>;
1206				dma-names = "rx", "tx";
1207				st,syscfg-fmp = <&syscfg 0x4 0x8>;
1208				i2c-analog-filter;
1209				access-controllers = <&etzpc 21>;
1210				status = "disabled";
1211			};
1212
1213			i2c5: i2c@4c006000 {
1214				compatible = "st,stm32mp13-i2c";
1215				reg = <0x4c006000 0x400>;
1216				interrupt-names = "event", "error";
1217				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1218					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1219				clocks = <&rcc I2C5_K>;
1220				resets = <&rcc I2C5_R>;
1221				#address-cells = <1>;
1222				#size-cells = <0>;
1223				dmas = <&dmamux1 115 0x400 0x1>,
1224				       <&dmamux1 116 0x400 0x1>;
1225				dma-names = "rx", "tx";
1226				st,syscfg-fmp = <&syscfg 0x4 0x10>;
1227				i2c-analog-filter;
1228				access-controllers = <&etzpc 22>;
1229				status = "disabled";
1230			};
1231
1232			timers12: timer@4c007000 {
1233				#address-cells = <1>;
1234				#size-cells = <0>;
1235				compatible = "st,stm32-timers";
1236				reg = <0x4c007000 0x400>;
1237				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1238				interrupt-names = "global";
1239				clocks = <&rcc TIM12_K>;
1240				clock-names = "int";
1241				access-controllers = <&etzpc 23>;
1242				status = "disabled";
1243
1244				counter {
1245					compatible = "st,stm32-timer-counter";
1246					status = "disabled";
1247				};
1248
1249				pwm {
1250					compatible = "st,stm32-pwm";
1251					#pwm-cells = <3>;
1252					status = "disabled";
1253				};
1254
1255				timer@11 {
1256					compatible = "st,stm32h7-timer-trigger";
1257					reg = <11>;
1258					status = "disabled";
1259				};
1260			};
1261
1262			timers13: timer@4c008000 {
1263				#address-cells = <1>;
1264				#size-cells = <0>;
1265				compatible = "st,stm32-timers";
1266				reg = <0x4c008000 0x400>;
1267				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1268				interrupt-names = "global";
1269				clocks = <&rcc TIM13_K>;
1270				clock-names = "int";
1271				access-controllers = <&etzpc 24>;
1272				status = "disabled";
1273
1274				counter {
1275					compatible = "st,stm32-timer-counter";
1276					status = "disabled";
1277				};
1278
1279				pwm {
1280					compatible = "st,stm32-pwm";
1281					#pwm-cells = <3>;
1282					status = "disabled";
1283				};
1284
1285				timer@12 {
1286					compatible = "st,stm32h7-timer-trigger";
1287					reg = <12>;
1288					status = "disabled";
1289				};
1290			};
1291
1292			timers14: timer@4c009000 {
1293				#address-cells = <1>;
1294				#size-cells = <0>;
1295				compatible = "st,stm32-timers";
1296				reg = <0x4c009000 0x400>;
1297				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1298				interrupt-names = "global";
1299				clocks = <&rcc TIM14_K>;
1300				clock-names = "int";
1301				access-controllers = <&etzpc 25>;
1302				status = "disabled";
1303
1304				counter {
1305					compatible = "st,stm32-timer-counter";
1306					status = "disabled";
1307				};
1308
1309				pwm {
1310					compatible = "st,stm32-pwm";
1311					#pwm-cells = <3>;
1312					status = "disabled";
1313				};
1314
1315				timer@13 {
1316					compatible = "st,stm32h7-timer-trigger";
1317					reg = <13>;
1318					status = "disabled";
1319				};
1320			};
1321
1322			timers15: timer@4c00a000 {
1323				#address-cells = <1>;
1324				#size-cells = <0>;
1325				compatible = "st,stm32-timers";
1326				reg = <0x4c00a000 0x400>;
1327				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1328				interrupt-names = "global";
1329				clocks = <&rcc TIM15_K>;
1330				clock-names = "int";
1331				dmas = <&dmamux1 105 0x400 0x1>,
1332				<&dmamux1 106 0x400 0x1>,
1333				<&dmamux1 107 0x400 0x1>,
1334				<&dmamux1 108 0x400 0x1>;
1335				dma-names = "ch1", "up", "trig", "com";
1336				access-controllers = <&etzpc 26>;
1337				status = "disabled";
1338
1339				counter {
1340					compatible = "st,stm32-timer-counter";
1341					status = "disabled";
1342				};
1343
1344				pwm {
1345					compatible = "st,stm32-pwm";
1346					#pwm-cells = <3>;
1347					status = "disabled";
1348				};
1349
1350				timer@14 {
1351					compatible = "st,stm32h7-timer-trigger";
1352					reg = <14>;
1353					status = "disabled";
1354				};
1355			};
1356
1357			timers16: timer@4c00b000 {
1358				#address-cells = <1>;
1359				#size-cells = <0>;
1360				compatible = "st,stm32-timers";
1361				reg = <0x4c00b000 0x400>;
1362				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1363				interrupt-names = "global";
1364				clocks = <&rcc TIM16_K>;
1365				clock-names = "int";
1366				dmas = <&dmamux1 109 0x400 0x1>,
1367				<&dmamux1 110 0x400 0x1>;
1368				dma-names = "ch1", "up";
1369				access-controllers = <&etzpc 27>;
1370				status = "disabled";
1371
1372				counter {
1373					compatible = "st,stm32-timer-counter";
1374					status = "disabled";
1375				};
1376
1377				pwm {
1378					compatible = "st,stm32-pwm";
1379					#pwm-cells = <3>;
1380					status = "disabled";
1381				};
1382
1383				timer@15 {
1384					compatible = "st,stm32h7-timer-trigger";
1385					reg = <15>;
1386					status = "disabled";
1387				};
1388			};
1389
1390			timers17: timer@4c00c000 {
1391				#address-cells = <1>;
1392				#size-cells = <0>;
1393				compatible = "st,stm32-timers";
1394				reg = <0x4c00c000 0x400>;
1395				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1396				interrupt-names = "global";
1397				clocks = <&rcc TIM17_K>;
1398				clock-names = "int";
1399				dmas = <&dmamux1 111 0x400 0x1>,
1400				       <&dmamux1 112 0x400 0x1>;
1401				dma-names = "ch1", "up";
1402				access-controllers = <&etzpc 28>;
1403				status = "disabled";
1404
1405				counter {
1406					compatible = "st,stm32-timer-counter";
1407					status = "disabled";
1408				};
1409
1410				pwm {
1411					compatible = "st,stm32-pwm";
1412					#pwm-cells = <3>;
1413					status = "disabled";
1414				};
1415
1416				timer@16 {
1417					compatible = "st,stm32h7-timer-trigger";
1418					reg = <16>;
1419					status = "disabled";
1420				};
1421			};
1422
1423			lptimer2: timer@50021000 {
1424				#address-cells = <1>;
1425				#size-cells = <0>;
1426				compatible = "st,stm32-lptimer";
1427				reg = <0x50021000 0x400>;
1428				interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1429				clocks = <&rcc LPTIM2_K>;
1430				clock-names = "mux";
1431				wakeup-source;
1432				access-controllers = <&etzpc 1>;
1433				status = "disabled";
1434
1435				pwm {
1436					compatible = "st,stm32-pwm-lp";
1437					#pwm-cells = <3>;
1438					status = "disabled";
1439				};
1440
1441				trigger@1 {
1442					compatible = "st,stm32-lptimer-trigger";
1443					reg = <1>;
1444					status = "disabled";
1445				};
1446
1447				counter {
1448					compatible = "st,stm32-lptimer-counter";
1449					status = "disabled";
1450				};
1451
1452				timer {
1453					compatible = "st,stm32-lptimer-timer";
1454					status = "disabled";
1455				};
1456			};
1457
1458			lptimer3: timer@50022000 {
1459				#address-cells = <1>;
1460				#size-cells = <0>;
1461				compatible = "st,stm32-lptimer";
1462				reg = <0x50022000 0x400>;
1463				interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1464				clocks = <&rcc LPTIM3_K>;
1465				clock-names = "mux";
1466				wakeup-source;
1467				access-controllers = <&etzpc 2>;
1468				status = "disabled";
1469
1470				pwm {
1471					compatible = "st,stm32-pwm-lp";
1472					#pwm-cells = <3>;
1473					status = "disabled";
1474				};
1475
1476				trigger@2 {
1477					compatible = "st,stm32-lptimer-trigger";
1478					reg = <2>;
1479					status = "disabled";
1480				};
1481
1482				timer {
1483					compatible = "st,stm32-lptimer-timer";
1484					status = "disabled";
1485				};
1486			};
1487
1488			hash: hash@54003000 {
1489				compatible = "st,stm32mp13-hash";
1490				reg = <0x54003000 0x400>;
1491				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1492				clocks = <&rcc HASH1>;
1493				resets = <&rcc HASH1_R>;
1494				dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>;
1495				dma-names = "in";
1496				access-controllers = <&etzpc 41>;
1497				status = "disabled";
1498			};
1499
1500			rng: rng@54004000 {
1501				compatible = "st,stm32mp13-rng";
1502				reg = <0x54004000 0x400>;
1503				clocks = <&rcc RNG1_K>;
1504				resets = <&rcc RNG1_R>;
1505				access-controllers = <&etzpc 40>;
1506				status = "disabled";
1507			};
1508
1509			fmc: memory-controller@58002000 {
1510				compatible = "st,stm32mp1-fmc2-ebi";
1511				reg = <0x58002000 0x1000>;
1512				ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1513					 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1514					 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1515					 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1516					 <4 0 0x80000000 0x10000000>; /* NAND */
1517				#address-cells = <2>;
1518				#size-cells = <1>;
1519				clocks = <&rcc FMC_K>;
1520				resets = <&rcc FMC_R>;
1521				access-controllers = <&etzpc 54>;
1522				status = "disabled";
1523
1524				nand-controller@4,0 {
1525					compatible = "st,stm32mp1-fmc2-nfc";
1526					reg = <4 0x00000000 0x1000>,
1527					      <4 0x08010000 0x1000>,
1528					      <4 0x08020000 0x1000>,
1529					      <4 0x01000000 0x1000>,
1530					      <4 0x09010000 0x1000>,
1531					      <4 0x09020000 0x1000>;
1532					#address-cells = <1>;
1533					#size-cells = <0>;
1534					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1535					dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
1536					       <&mdma 24 0x2 0x12000a08 0x0 0x0>,
1537					       <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
1538					dma-names = "tx", "rx", "ecc";
1539					status = "disabled";
1540				};
1541			};
1542
1543			qspi: spi@58003000 {
1544				compatible = "st,stm32f469-qspi";
1545				reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1546				reg-names = "qspi", "qspi_mm";
1547				#address-cells = <1>;
1548				#size-cells = <0>;
1549				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1550				dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
1551				       <&mdma 26 0x2 0x10100008 0x0 0x0>;
1552				dma-names = "tx", "rx";
1553				clocks = <&rcc QSPI_K>;
1554				resets = <&rcc QSPI_R>;
1555				access-controllers = <&etzpc 55>;
1556				status = "disabled";
1557			};
1558
1559			sdmmc1: mmc@58005000 {
1560				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1561				arm,primecell-periphid = <0x20253180>;
1562				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
1563				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1564				clocks = <&rcc SDMMC1_K>;
1565				clock-names = "apb_pclk";
1566				resets = <&rcc SDMMC1_R>;
1567				cap-sd-highspeed;
1568				cap-mmc-highspeed;
1569				max-frequency = <130000000>;
1570				access-controllers = <&etzpc 50>;
1571				status = "disabled";
1572			};
1573
1574			sdmmc2: mmc@58007000 {
1575				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1576				arm,primecell-periphid = <0x20253180>;
1577				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
1578				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1579				clocks = <&rcc SDMMC2_K>;
1580				clock-names = "apb_pclk";
1581				resets = <&rcc SDMMC2_R>;
1582				cap-sd-highspeed;
1583				cap-mmc-highspeed;
1584				max-frequency = <130000000>;
1585				access-controllers = <&etzpc 51>;
1586				status = "disabled";
1587			};
1588
1589			ethernet1: ethernet@5800a000 {
1590				compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
1591				reg = <0x5800a000 0x2000>;
1592				reg-names = "stmmaceth";
1593				interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1594						      <&exti 68 1>;
1595				interrupt-names = "macirq", "eth_wake_irq";
1596				clock-names = "stmmaceth",
1597					      "mac-clk-tx",
1598					      "mac-clk-rx",
1599					      "ethstp",
1600					      "eth-ck";
1601				clocks = <&rcc ETH1MAC>,
1602					 <&rcc ETH1TX>,
1603					 <&rcc ETH1RX>,
1604					 <&rcc ETH1STP>,
1605					 <&rcc ETH1CK_K>;
1606				st,syscon = <&syscfg 0x4 0xff0000>;
1607				snps,mixed-burst;
1608				snps,pbl = <2>;
1609				snps,axi-config = <&stmmac_axi_config_1>;
1610				snps,tso;
1611				access-controllers = <&etzpc 48>;
1612				status = "disabled";
1613
1614				stmmac_axi_config_1: stmmac-axi-config {
1615					snps,blen = <0 0 0 0 16 8 4>;
1616					snps,rd_osr_lmt = <0x7>;
1617					snps,wr_osr_lmt = <0x7>;
1618				};
1619			};
1620
1621			usbphyc: usbphyc@5a006000 {
1622				#address-cells = <1>;
1623				#size-cells = <0>;
1624				#clock-cells = <0>;
1625				compatible = "st,stm32mp1-usbphyc";
1626				reg = <0x5a006000 0x1000>;
1627				clocks = <&rcc USBPHY_K>;
1628				resets = <&rcc USBPHY_R>;
1629				vdda1v1-supply = <&scmi_reg11>;
1630				vdda1v8-supply = <&scmi_reg18>;
1631				access-controllers = <&etzpc 5>;
1632				status = "disabled";
1633
1634				usbphyc_port0: usb-phy@0 {
1635					#phy-cells = <0>;
1636					reg = <0>;
1637				};
1638
1639				usbphyc_port1: usb-phy@1 {
1640					#phy-cells = <1>;
1641					reg = <1>;
1642				};
1643			};
1644		};
1645
1646		/*
1647		 * Break node order to solve dependency probe issue between
1648		 * pinctrl and exti.
1649		 */
1650		pinctrl: pinctrl@50002000 {
1651			#address-cells = <1>;
1652			#size-cells = <1>;
1653			compatible = "st,stm32mp135-pinctrl";
1654			ranges = <0 0x50002000 0x8400>;
1655			interrupt-parent = <&exti>;
1656			st,syscfg = <&exti 0x60 0xff>;
1657
1658			gpioa: gpio@50002000 {
1659				gpio-controller;
1660				#gpio-cells = <2>;
1661				interrupt-controller;
1662				#interrupt-cells = <2>;
1663				reg = <0x0 0x400>;
1664				clocks = <&rcc GPIOA>;
1665				st,bank-name = "GPIOA";
1666				ngpios = <16>;
1667				gpio-ranges = <&pinctrl 0 0 16>;
1668			};
1669
1670			gpiob: gpio@50003000 {
1671				gpio-controller;
1672				#gpio-cells = <2>;
1673				interrupt-controller;
1674				#interrupt-cells = <2>;
1675				reg = <0x1000 0x400>;
1676				clocks = <&rcc GPIOB>;
1677				st,bank-name = "GPIOB";
1678				ngpios = <16>;
1679				gpio-ranges = <&pinctrl 0 16 16>;
1680			};
1681
1682			gpioc: gpio@50004000 {
1683				gpio-controller;
1684				#gpio-cells = <2>;
1685				interrupt-controller;
1686				#interrupt-cells = <2>;
1687				reg = <0x2000 0x400>;
1688				clocks = <&rcc GPIOC>;
1689				st,bank-name = "GPIOC";
1690				ngpios = <16>;
1691				gpio-ranges = <&pinctrl 0 32 16>;
1692			};
1693
1694			gpiod: gpio@50005000 {
1695				gpio-controller;
1696				#gpio-cells = <2>;
1697				interrupt-controller;
1698				#interrupt-cells = <2>;
1699				reg = <0x3000 0x400>;
1700				clocks = <&rcc GPIOD>;
1701				st,bank-name = "GPIOD";
1702				ngpios = <16>;
1703				gpio-ranges = <&pinctrl 0 48 16>;
1704			};
1705
1706			gpioe: gpio@50006000 {
1707				gpio-controller;
1708				#gpio-cells = <2>;
1709				interrupt-controller;
1710				#interrupt-cells = <2>;
1711				reg = <0x4000 0x400>;
1712				clocks = <&rcc GPIOE>;
1713				st,bank-name = "GPIOE";
1714				ngpios = <16>;
1715				gpio-ranges = <&pinctrl 0 64 16>;
1716			};
1717
1718			gpiof: gpio@50007000 {
1719				gpio-controller;
1720				#gpio-cells = <2>;
1721				interrupt-controller;
1722				#interrupt-cells = <2>;
1723				reg = <0x5000 0x400>;
1724				clocks = <&rcc GPIOF>;
1725				st,bank-name = "GPIOF";
1726				ngpios = <16>;
1727				gpio-ranges = <&pinctrl 0 80 16>;
1728			};
1729
1730			gpiog: gpio@50008000 {
1731				gpio-controller;
1732				#gpio-cells = <2>;
1733				interrupt-controller;
1734				#interrupt-cells = <2>;
1735				reg = <0x6000 0x400>;
1736				clocks = <&rcc GPIOG>;
1737				st,bank-name = "GPIOG";
1738				ngpios = <16>;
1739				gpio-ranges = <&pinctrl 0 96 16>;
1740			};
1741
1742			gpioh: gpio@50009000 {
1743				gpio-controller;
1744				#gpio-cells = <2>;
1745				interrupt-controller;
1746				#interrupt-cells = <2>;
1747				reg = <0x7000 0x400>;
1748				clocks = <&rcc GPIOH>;
1749				st,bank-name = "GPIOH";
1750				ngpios = <15>;
1751				gpio-ranges = <&pinctrl 0 112 15>;
1752			};
1753
1754			gpioi: gpio@5000a000 {
1755				gpio-controller;
1756				#gpio-cells = <2>;
1757				interrupt-controller;
1758				#interrupt-cells = <2>;
1759				reg = <0x8000 0x400>;
1760				clocks = <&rcc GPIOI>;
1761				st,bank-name = "GPIOI";
1762				ngpios = <8>;
1763				gpio-ranges = <&pinctrl 0 128 8>;
1764			};
1765		};
1766	};
1767};
1768