1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright (C) 2015 Freescale Semiconductor, Inc.
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8
9/ {
10	model = "Freescale i.MX7 SabreSD Board";
11	compatible = "fsl,imx7d-sdb", "fsl,imx7d";
12
13	aliases {
14		ethernet0 = &fec1;
15		ethernet1 = &fec2;
16	};
17
18	chosen {
19		stdout-path = &uart1;
20	};
21
22	memory@80000000 {
23		device_type = "memory";
24		reg = <0x80000000 0x80000000>;
25	};
26
27	gpio-keys {
28		compatible = "gpio-keys";
29		pinctrl-names = "default";
30		pinctrl-0 = <&pinctrl_gpio_keys>;
31
32		key-volume-up {
33			label = "Volume Up";
34			gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
35			linux,code = <KEY_VOLUMEUP>;
36			wakeup-source;
37		};
38
39		key-volume-down {
40			label = "Volume Down";
41			gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
42			linux,code = <KEY_VOLUMEDOWN>;
43			wakeup-source;
44		};
45	};
46
47	spi-4 {
48		compatible = "spi-gpio";
49		pinctrl-names = "default";
50		pinctrl-0 = <&pinctrl_spi4>;
51		sck-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
52		mosi-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
53		cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
54		num-chipselects = <1>;
55		#address-cells = <1>;
56		#size-cells = <0>;
57
58		extended_io: gpio-expander@0 {
59			compatible = "fairchild,74hc595";
60			gpio-controller;
61			#gpio-cells = <2>;
62			reg = <0>;
63			registers-number = <1>;
64			spi-max-frequency = <100000>;
65		};
66	};
67
68	reg_sd1_vmmc: regulator-sd1-vmmc {
69		compatible = "regulator-fixed";
70		regulator-name = "VDD_SD1";
71		regulator-min-microvolt = <3300000>;
72		regulator-max-microvolt = <3300000>;
73		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
74		enable-active-high;
75		startup-delay-us = <200000>;
76		off-on-delay-us = <20000>;
77	};
78
79	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
80		compatible = "regulator-fixed";
81		regulator-name = "usb_otg1_vbus";
82		regulator-min-microvolt = <5000000>;
83		regulator-max-microvolt = <5000000>;
84		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
85		enable-active-high;
86	};
87
88	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
89		compatible = "regulator-fixed";
90		regulator-name = "usb_otg2_vbus";
91		pinctrl-names = "default";
92		pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
93		regulator-min-microvolt = <5000000>;
94		regulator-max-microvolt = <5000000>;
95		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
96		enable-active-high;
97	};
98
99	reg_vref_1v8: regulator-vref-1v8 {
100		compatible = "regulator-fixed";
101		regulator-name = "vref-1v8";
102		regulator-min-microvolt = <1800000>;
103		regulator-max-microvolt = <1800000>;
104	};
105
106	reg_brcm: regulator-brcm {
107		compatible = "regulator-fixed";
108		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
109		enable-active-high;
110		regulator-name = "brcm_reg";
111		pinctrl-names = "default";
112		pinctrl-0 = <&pinctrl_brcm_reg>;
113		regulator-min-microvolt = <3300000>;
114		regulator-max-microvolt = <3300000>;
115		startup-delay-us = <200000>;
116	};
117
118	reg_lcd_3v3: regulator-lcd-3v3 {
119		compatible = "regulator-fixed";
120		regulator-name = "lcd-3v3";
121		regulator-min-microvolt = <3300000>;
122		regulator-max-microvolt = <3300000>;
123		gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
124	};
125
126	reg_can2_3v3: regulator-can2-3v3 {
127		compatible = "regulator-fixed";
128		regulator-name = "can2-3v3";
129		pinctrl-names = "default";
130		pinctrl-0 = <&pinctrl_flexcan2_reg>;
131		regulator-min-microvolt = <3300000>;
132		regulator-max-microvolt = <3300000>;
133		gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
134	};
135
136	reg_fec2_3v3: regulator-fec2-3v3 {
137		compatible = "regulator-fixed";
138		regulator-name = "fec2-3v3";
139		pinctrl-names = "default";
140		pinctrl-0 = <&pinctrl_enet2_reg>;
141		regulator-min-microvolt = <3300000>;
142		regulator-max-microvolt = <3300000>;
143		gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
144	};
145
146	reg_audio_5v: regulator-audio-pwr {
147		compatible = "regulator-fixed";
148		regulator-name = "audio-5v";
149		regulator-min-microvolt = <5000000>;
150		regulator-max-microvolt = <5000000>;
151		regulator-always-on;
152		regulator-boot-on;
153	};
154
155	reg_audio_3v3: regulator-audio-3v3 {
156		compatible = "regulator-fixed";
157		regulator-name = "audio-3v3";
158		regulator-min-microvolt = <3300000>;
159		regulator-max-microvolt = <3300000>;
160		regulator-always-on;
161		regulator-boot-on;
162	};
163
164	reg_audio_1v8: regulator-audio-1v8 {
165		compatible = "regulator-fixed";
166		regulator-name = "audio-1v8";
167		regulator-min-microvolt = <1800000>;
168		regulator-max-microvolt = <1800000>;
169		regulator-always-on;
170		regulator-boot-on;
171	};
172
173	backlight: backlight {
174		compatible = "pwm-backlight";
175		pwms = <&pwm1 0 5000000 0>;
176		brightness-levels = <0 4 8 16 32 64 128 255>;
177		default-brightness-level = <6>;
178		status = "okay";
179	};
180
181	panel {
182		compatible = "innolux,at043tn24";
183		backlight = <&backlight>;
184		power-supply = <&reg_lcd_3v3>;
185
186		port {
187			panel_in: endpoint {
188				remote-endpoint = <&display_out>;
189			};
190		};
191	};
192
193	sound {
194		compatible = "fsl,imx7d-evk-wm8960",
195			     "fsl,imx-audio-wm8960";
196		model = "wm8960-audio";
197		audio-cpu = <&sai1>;
198		audio-codec = <&codec>;
199		hp-det-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
200		audio-routing =
201			"Headphone Jack", "HP_L",
202			"Headphone Jack", "HP_R",
203			"Ext Spk", "SPK_LP",
204			"Ext Spk", "SPK_LN",
205			"Ext Spk", "SPK_RP",
206			"Ext Spk", "SPK_RN",
207			"LINPUT1", "AMIC",
208			"AMIC", "MICB";
209	};
210
211	sound-hdmi {
212		compatible = "fsl,imx-audio-sii902x";
213		model = "sii902x-audio";
214		audio-cpu = <&sai3>;
215		hdmi-out;
216	};
217};
218
219&adc1 {
220	vref-supply = <&reg_vref_1v8>;
221	status = "okay";
222};
223
224&adc2 {
225	vref-supply = <&reg_vref_1v8>;
226	status = "okay";
227};
228
229&cpu0 {
230	cpu-supply = <&sw1a_reg>;
231};
232
233&cpu1 {
234	cpu-supply = <&sw1a_reg>;
235};
236
237&ecspi3 {
238	pinctrl-names = "default";
239	pinctrl-0 = <&pinctrl_ecspi3>;
240	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
241	status = "okay";
242
243	tsc2046@0 {
244		compatible = "ti,tsc2046";
245		reg = <0>;
246		spi-max-frequency = <1000000>;
247		pinctrl-names = "default";
248		pinctrl-0 = <&pinctrl_tsc2046_pendown>;
249		interrupt-parent = <&gpio2>;
250		interrupts = <29 0>;
251		pendown-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
252		touchscreen-max-pressure = <255>;
253		wakeup-source;
254	};
255};
256
257&fec1 {
258	pinctrl-names = "default";
259	pinctrl-0 = <&pinctrl_enet1>;
260	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
261			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
262	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
263	assigned-clock-rates = <0>, <100000000>;
264	phy-mode = "rgmii";
265	phy-handle = <&ethphy0>;
266	fsl,magic-packet;
267	phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
268	status = "okay";
269
270	mdio {
271		#address-cells = <1>;
272		#size-cells = <0>;
273
274		ethphy0: ethernet-phy@0 {
275			reg = <0>;
276		};
277
278		ethphy1: ethernet-phy@1 {
279			reg = <1>;
280		};
281	};
282};
283
284&fec2 {
285	pinctrl-names = "default";
286	pinctrl-0 = <&pinctrl_enet2>;
287	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
288			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
289	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
290	assigned-clock-rates = <0>, <100000000>;
291	phy-mode = "rgmii";
292	phy-handle = <&ethphy1>;
293	phy-supply = <&reg_fec2_3v3>;
294	fsl,magic-packet;
295	status = "okay";
296};
297
298&flexcan2 {
299	pinctrl-names = "default";
300	pinctrl-0 = <&pinctrl_flexcan2>;
301	xceiver-supply = <&reg_can2_3v3>;
302	status = "okay";
303};
304
305&i2c1 {
306	pinctrl-names = "default";
307	pinctrl-0 = <&pinctrl_i2c1>;
308	status = "okay";
309
310	pmic: pmic@8 {
311		compatible = "fsl,pfuze3000";
312		reg = <0x08>;
313
314		regulators {
315			sw1a_reg: sw1a {
316				regulator-min-microvolt = <700000>;
317				regulator-max-microvolt = <1475000>;
318				regulator-boot-on;
319				regulator-always-on;
320				regulator-ramp-delay = <6250>;
321			};
322
323			/* use sw1c_reg to align with pfuze100/pfuze200 */
324			sw1c_reg: sw1b {
325				regulator-min-microvolt = <700000>;
326				regulator-max-microvolt = <1475000>;
327				regulator-boot-on;
328				regulator-always-on;
329				regulator-ramp-delay = <6250>;
330			};
331
332			sw2_reg: sw2 {
333				regulator-min-microvolt = <1800000>;
334				regulator-max-microvolt = <1800000>;
335				regulator-boot-on;
336				regulator-always-on;
337			};
338
339			sw3a_reg: sw3 {
340				regulator-min-microvolt = <900000>;
341				regulator-max-microvolt = <1650000>;
342				regulator-boot-on;
343				regulator-always-on;
344			};
345
346			swbst_reg: swbst {
347				regulator-min-microvolt = <5000000>;
348				regulator-max-microvolt = <5150000>;
349			};
350
351			snvs_reg: vsnvs {
352				regulator-min-microvolt = <1000000>;
353				regulator-max-microvolt = <3000000>;
354				regulator-boot-on;
355				regulator-always-on;
356			};
357
358			vref_reg: vrefddr {
359				regulator-boot-on;
360				regulator-always-on;
361			};
362
363			vgen1_reg: vldo1 {
364				regulator-min-microvolt = <1800000>;
365				regulator-max-microvolt = <3300000>;
366				regulator-always-on;
367			};
368
369			vgen2_reg: vldo2 {
370				regulator-min-microvolt = <800000>;
371				regulator-max-microvolt = <1550000>;
372			};
373
374			vgen3_reg: vccsd {
375				regulator-min-microvolt = <2850000>;
376				regulator-max-microvolt = <3300000>;
377				regulator-always-on;
378			};
379
380			vgen4_reg: v33 {
381				regulator-min-microvolt = <2850000>;
382				regulator-max-microvolt = <3300000>;
383				regulator-always-on;
384			};
385
386			vgen5_reg: vldo3 {
387				regulator-min-microvolt = <1800000>;
388				regulator-max-microvolt = <3300000>;
389				regulator-always-on;
390			};
391
392			vgen6_reg: vldo4 {
393				regulator-min-microvolt = <2800000>;
394				regulator-max-microvolt = <2800000>;
395				regulator-always-on;
396			};
397		};
398	};
399};
400
401&i2c2 {
402	pinctrl-names = "default";
403	pinctrl-0 = <&pinctrl_i2c2>;
404	status = "okay";
405
406	mpl3115@60 {
407		compatible = "fsl,mpl3115";
408		reg = <0x60>;
409	};
410};
411
412&i2c3 {
413	pinctrl-names = "default";
414	pinctrl-0 = <&pinctrl_i2c3>;
415	status = "okay";
416};
417
418&i2c4 {
419	pinctrl-names = "default";
420	pinctrl-0 = <&pinctrl_i2c4>;
421	status = "okay";
422
423	codec: wm8960@1a {
424		compatible = "wlf,wm8960";
425		reg = <0x1a>;
426		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
427		clock-names = "mclk";
428		wlf,shared-lrclk;
429		wlf,hp-cfg = <2 2 3>;
430		wlf,gpio-cfg = <1 3>;
431		assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
432				  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
433				  <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
434		assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
435		assigned-clock-rates = <0>, <884736000>, <12288000>;
436		AVDD-supply = <&reg_audio_3v3>;
437		DBVDD-supply = <&reg_audio_1v8>;
438		DCVDD-supply = <&reg_audio_1v8>;
439		SPKVDD1-supply = <&reg_audio_5v>;
440		SPKVDD2-supply = <&reg_audio_5v>;
441	};
442};
443
444&lcdif {
445	pinctrl-names = "default";
446	pinctrl-0 = <&pinctrl_lcdif>;
447	status = "okay";
448
449	port {
450		display_out: endpoint {
451			remote-endpoint = <&panel_in>;
452		};
453	};
454};
455
456&pcie {
457	reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
458	status = "okay";
459};
460
461&reg_1p0d {
462	vin-supply = <&sw2_reg>;
463};
464
465&reg_1p2 {
466	vin-supply = <&sw2_reg>;
467};
468
469&sai1 {
470	pinctrl-names = "default";
471	pinctrl-0 = <&pinctrl_sai1>;
472	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
473			  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
474			  <&clks IMX7D_SAI1_ROOT_CLK>;
475	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
476	assigned-clock-rates = <0>, <884736000>, <36864000>;
477	status = "okay";
478};
479
480&sai3 {
481	pinctrl-names = "default";
482	pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
483	assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
484			  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
485			  <&clks IMX7D_SAI3_ROOT_CLK>;
486	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
487	assigned-clock-rates = <0>, <884736000>, <36864000>;
488	status = "okay";
489};
490
491&snvs_pwrkey {
492	status = "okay";
493};
494
495&uart1 {
496	pinctrl-names = "default";
497	pinctrl-0 = <&pinctrl_uart1>;
498	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
499	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
500	status = "okay";
501};
502
503&uart6 {
504	pinctrl-names = "default";
505	pinctrl-0 = <&pinctrl_uart6>;
506	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
507	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
508	uart-has-rtscts;
509	status = "okay";
510};
511
512&usbotg1 {
513	vbus-supply = <&reg_usb_otg1_vbus>;
514	status = "okay";
515};
516
517&usbotg2 {
518	vbus-supply = <&reg_usb_otg2_vbus>;
519	dr_mode = "host";
520	status = "okay";
521};
522
523&usdhc1 {
524	pinctrl-names = "default", "state_100mhz", "state_200mhz";
525	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
526	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
527	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
528	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
529	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
530	vmmc-supply = <&reg_sd1_vmmc>;
531	wakeup-source;
532	keep-power-in-suspend;
533	status = "okay";
534};
535
536&usdhc2 {
537	pinctrl-names = "default", "state_100mhz", "state_200mhz";
538	pinctrl-0 = <&pinctrl_usdhc2>;
539	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
540	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
541	wakeup-source;
542	keep-power-in-suspend;
543	non-removable;
544	vmmc-supply = <&reg_brcm>;
545	fsl,tuning-step = <2>;
546	status = "okay";
547};
548
549&usdhc3 {
550	pinctrl-names = "default", "state_100mhz", "state_200mhz";
551	pinctrl-0 = <&pinctrl_usdhc3>;
552	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
553	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
554	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
555	assigned-clock-rates = <400000000>;
556	bus-width = <8>;
557	fsl,tuning-step = <2>;
558	non-removable;
559	status = "okay";
560};
561
562&wdog1 {
563	pinctrl-names = "default";
564	pinctrl-0 = <&pinctrl_wdog>;
565	fsl,ext-reset-output;
566};
567
568&iomuxc {
569	pinctrl-names = "default";
570	pinctrl-0 = <&pinctrl_hog>;
571
572	pinctrl_brcm_reg: brcmreggrp {
573		fsl,pins = <
574			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x14
575		>;
576	};
577
578	pinctrl_ecspi3: ecspi3grp {
579		fsl,pins = <
580			MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO	0x2
581			MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI	0x2
582			MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK	0x2
583			MX7D_PAD_SD2_CD_B__GPIO5_IO9		0x59
584		>;
585	};
586
587	pinctrl_enet1: enet1grp {
588		fsl,pins = <
589			MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
590			MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
591			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
592			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
593			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
594			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
595			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
596			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
597			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
598			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
599			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
600			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
601			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
602			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
603		>;
604	};
605
606	pinctrl_enet2: enet2grp {
607		fsl,pins = <
608			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC		0x1
609			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0		0x1
610			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1		0x1
611			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2		0x1
612			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3		0x1
613			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL		0x1
614			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC		0x1
615			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0		0x1
616			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1		0x1
617			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2		0x1
618			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3		0x1
619			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL		0x1
620		>;
621	};
622
623	pinctrl_enet2_reg: enet2reggrp {
624		fsl,pins = <
625			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4	0x14
626		>;
627	};
628
629	pinctrl_flexcan2: flexcan2grp {
630		fsl,pins = <
631			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x59
632			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x59
633		>;
634	};
635
636	pinctrl_flexcan2_reg: flexcan2reggrp {
637		fsl,pins = <
638			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x59	/* CAN_STBY */
639		>;
640	};
641
642	pinctrl_gpio_keys: gpio-keysgrp {
643		fsl,pins = <
644			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x59
645			MX7D_PAD_SD2_WP__GPIO5_IO10		0x59
646		>;
647	};
648
649	pinctrl_hog: hoggrp {
650		fsl,pins = <
651			MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x34  /* bt reg on */
652			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x59  /* headphone detect */
653		>;
654	};
655
656	pinctrl_i2c1: i2c1grp {
657		fsl,pins = <
658			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
659			MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
660		>;
661	};
662
663	pinctrl_i2c2: i2c2grp {
664		fsl,pins = <
665			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
666			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
667		>;
668	};
669
670	pinctrl_i2c3: i2c3grp {
671		fsl,pins = <
672			MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
673			MX7D_PAD_I2C3_SCL__I2C3_SCL		0x4000007f
674		>;
675	};
676
677	pinctrl_i2c4: i2c4grp {
678		fsl,pins = <
679			MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
680			MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL		0x4000007f
681		>;
682	};
683
684	pinctrl_lcdif: lcdifgrp {
685		fsl,pins = <
686			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
687			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
688			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
689			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
690			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
691			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
692			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
693			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
694			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
695			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
696			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
697			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
698			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
699			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
700			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
701			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
702			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
703			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
704			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
705			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
706			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
707			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
708			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
709			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
710			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
711			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
712			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
713			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
714			MX7D_PAD_LCD_RESET__LCD_RESET		0x79
715		>;
716	};
717
718	pinctrl_sai1: sai1grp {
719		fsl,pins = <
720			MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
721			MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
722			MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f
723			MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
724			MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
725		>;
726	};
727
728	pinctrl_sai2: sai2grp {
729		fsl,pins = <
730			MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
731			MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
732			MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0x30
733			MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0    0x1f
734		>;
735	};
736
737	pinctrl_sai3: sai3grp {
738		fsl,pins = <
739			MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK   0x1f
740			MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC     0x1f
741			MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0    0x30
742		>;
743	};
744
745	pinctrl_spi4: spi4grp {
746		fsl,pins = <
747			MX7D_PAD_GPIO1_IO09__GPIO1_IO9	0x59
748			MX7D_PAD_GPIO1_IO12__GPIO1_IO12	0x59
749			MX7D_PAD_GPIO1_IO13__GPIO1_IO13	0x59
750		>;
751	};
752
753	pinctrl_tsc2046_pendown: tsc2046-pendowngrp {
754		fsl,pins = <
755			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x59
756		>;
757	};
758
759	pinctrl_uart1: uart1grp {
760		fsl,pins = <
761			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
762			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
763		>;
764	};
765
766	pinctrl_uart5: uart5grp {
767		fsl,pins = <
768			MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX	0x79
769			MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX	0x79
770			MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS	0x79
771			MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS	0x79
772		>;
773	};
774
775	pinctrl_uart6: uart6grp {
776		fsl,pins = <
777			MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX	0x79
778			MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX	0x79
779			MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS	0x79
780			MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS	0x79
781		>;
782	};
783
784	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
785		fsl,pins = <
786			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
787			MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
788			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
789			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
790		>;
791	};
792
793	pinctrl_usdhc1: usdhc1grp {
794		fsl,pins = <
795			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
796			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
797			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
798			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
799			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
800			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
801		>;
802	};
803
804	pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
805		fsl,pins = <
806			MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
807			MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
808			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
809			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
810			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
811			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
812		>;
813	};
814
815	pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
816		fsl,pins = <
817			MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
818			MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
819			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
820			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
821			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
822			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
823		>;
824	};
825
826	pinctrl_usdhc2: usdhc2grp {
827		fsl,pins = <
828			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
829			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
830			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
831			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
832			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
833			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
834		>;
835	};
836
837	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
838		fsl,pins = <
839			MX7D_PAD_SD2_CMD__SD2_CMD		0x5a
840			MX7D_PAD_SD2_CLK__SD2_CLK		0x1a
841			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5a
842			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5a
843			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5a
844			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5a
845		>;
846	};
847
848	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
849		fsl,pins = <
850			MX7D_PAD_SD2_CMD__SD2_CMD		0x5b
851			MX7D_PAD_SD2_CLK__SD2_CLK		0x1b
852			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x5b
853			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x5b
854			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x5b
855			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x5b
856		>;
857	};
858
859
860	pinctrl_usdhc3: usdhc3grp {
861		fsl,pins = <
862			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
863			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
864			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
865			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
866			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
867			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
868			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
869			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
870			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
871			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
872			MX7D_PAD_SD3_STROBE__SD3_STROBE		0x19
873		>;
874	};
875
876	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
877		fsl,pins = <
878			MX7D_PAD_SD3_CMD__SD3_CMD		0x5a
879			MX7D_PAD_SD3_CLK__SD3_CLK		0x1a
880			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5a
881			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5a
882			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5a
883			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5a
884			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5a
885			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5a
886			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5a
887			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5a
888			MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1a
889		>;
890	};
891
892	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
893		fsl,pins = <
894			MX7D_PAD_SD3_CMD__SD3_CMD		0x5b
895			MX7D_PAD_SD3_CLK__SD3_CLK		0x1b
896			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x5b
897			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x5b
898			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x5b
899			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x5b
900			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x5b
901			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x5b
902			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x5b
903			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x5b
904			MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1b
905		>;
906	};
907};
908
909&pwm1 {
910	pinctrl-names = "default";
911	pinctrl-0 = <&pinctrl_pwm1>;
912	status = "okay";
913};
914
915&iomuxc_lpsr {
916	pinctrl_wdog: wdoggrp {
917		fsl,pins = <
918			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B		0x74
919		>;
920	};
921
922	pinctrl_pwm1: pwm1grp {
923		fsl,pins = <
924			MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT		0x30
925		>;
926	};
927
928	pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
929		fsl,pins = <
930			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	  0x14
931		>;
932	};
933
934	pinctrl_sai3_mclk: sai3-mclk-grp {
935		fsl,pins = <
936			MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK	0x1f
937		>;
938	};
939};
940