1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL
4 * Variscite SoM mounted on it
5 *
6 * Copyright 2019 Variscite Ltd.
7 * Copyright 2025 Bootlin
8 */
9
10#include "imx6ul-var-som.dtsi"
11#include <dt-bindings/leds/common.h>
12
13/ {
14	model = "Variscite VAR-SOM-MX6UL Concerto Board";
15	compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
16
17	chosen {
18		stdout-path = &uart1;
19	};
20
21	gpio-keys {
22		compatible = "gpio-keys";
23		pinctrl-names = "default";
24		pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
25
26		key-back {
27			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
28			linux,code = <KEY_BACK>;
29		};
30
31		key-wakeup {
32			gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
33			linux,code = <KEY_WAKEUP>;
34			wakeup-source;
35		};
36	};
37
38	leds {
39		compatible = "gpio-leds";
40		pinctrl-names = "default";
41		pinctrl-0 = <&pinctrl_gpio_leds>;
42
43		led-0 {
44			function = LED_FUNCTION_STATUS;
45			color = <LED_COLOR_ID_GREEN>;
46			label = "gpled2";
47			gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
48			linux,default-trigger = "heartbeat";
49		};
50	};
51};
52
53&can1 {
54	pinctrl-names = "default";
55	pinctrl-0 = <&pinctrl_flexcan1>;
56	status = "okay";
57};
58
59&fec1 {
60	status = "disabled";
61};
62
63&fec2 {
64	pinctrl-names = "default";
65	pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
66	phy-mode = "rmii";
67	phy-handle = <&ethphy1>;
68	status = "okay";
69
70	mdio {
71		#address-cells = <1>;
72		#size-cells = <0>;
73
74		ethphy1: ethernet-phy@3 {
75			compatible = "ethernet-phy-ieee802.3-c22";
76			reg = <3>;
77			clocks = <&rmii_ref_clk>;
78			clock-names = "rmii-ref";
79			reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
80			reset-assert-us = <100000>;
81			micrel,led-mode = <0>;
82			micrel,rmii-reference-clock-select-25-mhz = <1>;
83		};
84	};
85};
86
87&i2c1 {
88	clock-frequency = <100000>;
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_i2c1>;
91	status = "okay";
92
93	rtc@68 {
94		/*
95		 * To actually use this interrupt
96		 * connect pins J14.8 & J14.10 on the Concerto-Board.
97		 */
98		compatible = "dallas,ds1337";
99		reg = <0x68>;
100		pinctrl-names = "default";
101		pinctrl-0 = <&pinctrl_rtc>;
102		interrupt-parent = <&gpio1>;
103		interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
104	};
105};
106
107&iomuxc {
108	pinctrl_enet2: enet2grp {
109		fsl,pins = <
110			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
111			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
112			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
113			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
114			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
115			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
116			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
117			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
118		>;
119	};
120
121	pinctrl_enet2_gpio: enet2-gpiogrp {
122		fsl,pins = <
123			MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x1b0b0 /* fec2 reset */
124		>;
125	};
126
127	pinctrl_enet2_mdio: enet2-mdiogrp {
128		fsl,pins = <
129			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
130			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
131		>;
132	};
133
134	pinctrl_flexcan1: flexcan1grp {
135		fsl,pins = <
136			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
137			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
138		>;
139	};
140
141	pinctrl_gpio_key_back: gpio-key-backgrp {
142		fsl,pins = <
143			MX6UL_PAD_NAND_CE1_B__GPIO4_IO14	0x17059
144		>;
145	};
146
147	pinctrl_gpio_leds: gpio-ledsgrp {
148		fsl,pins = <
149			MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25	0x1b0b0	/* GPLED2 */
150		>;
151	};
152
153	pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
154		fsl,pins = <
155			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x17059
156		>;
157	};
158
159	pinctrl_i2c1: i2c1grp {
160		fsl,pins = <
161			MX6UL_PAD_CSI_PIXCLK__I2C1_SCL		0x4001b8b0
162			MX6UL_PAD_CSI_MCLK__I2C1_SDA		0x4001b8b0
163		>;
164	};
165
166	pinctrl_pwm4: pwm4grp {
167		fsl,pins = <
168			MX6UL_PAD_GPIO1_IO05__PWM4_OUT		0x110b0
169		>;
170	};
171
172	pinctrl_rtc: rtcgrp {
173		fsl,pins = <
174			MX6UL_PAD_JTAG_MOD__GPIO1_IO10		0x1b0b0 /* RTC alarm IRQ */
175		>;
176	};
177
178	pinctrl_uart1: uart1grp {
179		fsl,pins = <
180			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX	0x1b0b1
181			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX	0x1b0b1
182		>;
183	};
184
185	pinctrl_uart5: uart5grp {
186		fsl,pins = <
187			MX6UL_PAD_CSI_DATA00__UART5_DCE_TX	0x1b0b1
188			MX6UL_PAD_CSI_DATA01__UART5_DCE_RX	0x1b0b1
189			MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS	0x1b0b1
190			MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS	0x1b0b1
191		>;
192	};
193
194	pinctrl_usb_otg1_id: usbotg1idgrp {
195		fsl,pins = <
196			MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID	0x17059
197		>;
198	};
199
200	pinctrl_usdhc1: usdhc1grp {
201		fsl,pins = <
202			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
203			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x17059
204			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
205			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
206			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
207			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
208		>;
209	};
210
211	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
212		fsl,pins = <
213			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170b9
214			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100b9
215			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170b9
216			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170b9
217			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170b9
218			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170b9
219		>;
220	};
221
222	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
223		fsl,pins = <
224			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x170f9
225			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x100f9
226			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x170f9
227			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x170f9
228			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x170f9
229			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x170f9
230		>;
231	};
232
233	pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
234		fsl,pins = <
235			MX6UL_PAD_GPIO1_IO00__GPIO1_IO00	0x1b0b1 /* CD */
236		>;
237	};
238
239	pinctrl_wdog: wdoggrp {
240		fsl,pins = <
241			MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B	0x78b0
242		>;
243	};
244};
245
246&pwm4 {
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_pwm4>;
249	status = "okay";
250};
251
252&snvs_pwrkey {
253	status = "disabled";
254};
255
256&snvs_rtc {
257	status = "disabled";
258};
259
260&tsc {
261	/*
262	 * Conflics with wdog1 ext-reset-output & SD CD pins,
263	 * so we keep it disabled by default.
264	 */
265	status = "disabled";
266};
267
268/* Console UART */
269&uart1 {
270	pinctrl-names = "default";
271	pinctrl-0 = <&pinctrl_uart1>;
272	status = "okay";
273};
274
275/* ttymxc4 UART */
276&uart5 {
277	pinctrl-names = "default";
278	pinctrl-0 = <&pinctrl_uart5>;
279	uart-has-rtscts;
280	status = "okay";
281};
282
283&usbotg1 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_usb_otg1_id>;
286	dr_mode = "otg";
287	disable-over-current;
288	srp-disable;
289	hnp-disable;
290	adp-disable;
291	status = "okay";
292};
293
294&usbotg2 {
295	dr_mode = "host";
296	disable-over-current;
297	status = "okay";
298};
299
300&usdhc1 {
301	pinctrl-names = "default", "state_100mhz", "state_200mhz";
302	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
303	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
304	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
305	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
306	no-1-8-v;
307	keep-power-in-suspend;
308	wakeup-source;
309	status = "okay";
310};
311
312&wdog1 {
313	pinctrl-names = "default";
314	pinctrl-0 = <&pinctrl_wdog>;
315	/*
316	 * To actually use ext-reset-output
317	 * connect pins J17.3 & J17.8 on the Concerto-Board
318	 */
319	fsl,ext-reset-output;
320};
321