1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/media/video-interfaces.h> 6 7/ { 8 chosen { 9 stdout-path = &uart1; 10 }; 11 12 memory@80000000 { 13 device_type = "memory"; 14 reg = <0x80000000 0x20000000>; 15 }; 16 17 backlight_display: backlight-display { 18 compatible = "pwm-backlight"; 19 pwms = <&pwm1 0 5000000 0>; 20 brightness-levels = <0 4 8 16 32 64 128 255>; 21 default-brightness-level = <6>; 22 status = "okay"; 23 }; 24 25 26 reg_sd1_vmmc: regulator-sd1-vmmc { 27 compatible = "regulator-fixed"; 28 regulator-name = "VSD_3V3"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 32 enable-active-high; 33 }; 34 35 reg_peri_3v3: regulator-peri-3v3 { 36 compatible = "regulator-fixed"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_peri_3v3>; 39 regulator-name = "VPERI_3V3"; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 43 /* 44 * If you want to want to make this dynamic please 45 * check schematics and test all affected peripherals: 46 * 47 * - sensors 48 * - ethernet phy 49 * - can 50 * - bluetooth 51 * - wm8960 audio codec 52 * - ov5640 camera 53 */ 54 regulator-always-on; 55 }; 56 57 reg_can_3v3: regulator-can-3v3 { 58 compatible = "regulator-fixed"; 59 regulator-name = "can-3v3"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; 63 }; 64 65 reg_audio_5v: regulator-audio-pwr { 66 compatible = "regulator-fixed"; 67 regulator-name = "audio-5v"; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 regulator-always-on; 71 regulator-boot-on; 72 }; 73 74 reg_audio_3v3: regulator-audio-3v3 { 75 compatible = "regulator-fixed"; 76 regulator-name = "audio-3v3"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 regulator-always-on; 80 regulator-boot-on; 81 }; 82 83 reg_audio_1v8: regulator-audio-1v8 { 84 compatible = "regulator-fixed"; 85 regulator-name = "audio-1v8"; 86 regulator-min-microvolt = <1800000>; 87 regulator-max-microvolt = <1800000>; 88 regulator-always-on; 89 regulator-boot-on; 90 }; 91 92 sound-wm8960 { 93 compatible = "fsl,imx-audio-wm8960"; 94 model = "wm8960-audio"; 95 audio-cpu = <&sai2>; 96 audio-codec = <&codec>; 97 audio-asrc = <&asrc>; 98 hp-det-gpios = <&gpio5 4 0>; 99 audio-routing = 100 "Headphone Jack", "HP_L", 101 "Headphone Jack", "HP_R", 102 "Ext Spk", "SPK_LP", 103 "Ext Spk", "SPK_LN", 104 "Ext Spk", "SPK_RP", 105 "Ext Spk", "SPK_RN", 106 "LINPUT2", "Mic Jack", 107 "LINPUT3", "Mic Jack", 108 "RINPUT1", "AMIC", 109 "RINPUT2", "AMIC", 110 "Mic Jack", "MICB", 111 "AMIC", "MICB"; 112 }; 113 114 spi-4 { 115 compatible = "spi-gpio"; 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_spi4>; 118 status = "okay"; 119 sck-gpios = <&gpio5 11 0>; 120 mosi-gpios = <&gpio5 10 0>; 121 cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; 122 num-chipselects = <1>; 123 #address-cells = <1>; 124 #size-cells = <0>; 125 126 gpio_spi: gpio@0 { 127 compatible = "fairchild,74hc595"; 128 gpio-controller; 129 #gpio-cells = <2>; 130 reg = <0>; 131 registers-number = <1>; 132 spi-max-frequency = <100000>; 133 enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 134 }; 135 }; 136 137 panel { 138 compatible = "innolux,at043tn24"; 139 backlight = <&backlight_display>; 140 141 port { 142 panel_in: endpoint { 143 remote-endpoint = <&display_out>; 144 }; 145 }; 146 }; 147}; 148 149&clks { 150 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 151 assigned-clock-rates = <786432000>; 152}; 153 154&i2c2 { 155 clock-frequency = <100000>; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_i2c2>; 158 status = "okay"; 159 160 codec: wm8960@1a { 161 #sound-dai-cells = <0>; 162 compatible = "wlf,wm8960"; 163 reg = <0x1a>; 164 wlf,shared-lrclk; 165 wlf,hp-cfg = <3 2 3>; 166 wlf,gpio-cfg = <1 3>; 167 clocks = <&clks IMX6UL_CLK_SAI2>; 168 clock-names = "mclk"; 169 AVDD-supply = <®_audio_3v3>; 170 DBVDD-supply = <®_audio_1v8>; 171 DCVDD-supply = <®_audio_1v8>; 172 SPKVDD1-supply = <®_audio_5v>; 173 SPKVDD2-supply = <®_audio_5v>; 174 }; 175 176 camera@3c { 177 compatible = "ovti,ov5640"; 178 reg = <0x3c>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_camera_clock>; 181 clocks = <&clks IMX6UL_CLK_CSI>; 182 clock-names = "xclk"; 183 powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; 184 reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; 185 186 port { 187 ov5640_to_parallel: endpoint { 188 remote-endpoint = <¶llel_from_ov5640>; 189 bus-width = <8>; 190 data-shift = <2>; /* lines 9:2 are used */ 191 hsync-active = <0>; 192 vsync-active = <0>; 193 pclk-sample = <1>; 194 }; 195 }; 196 }; 197}; 198 199&csi { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_csi1>; 202 status = "okay"; 203 204 port { 205 parallel_from_ov5640: endpoint { 206 remote-endpoint = <&ov5640_to_parallel>; 207 bus-type = <MEDIA_BUS_TYPE_PARALLEL>; 208 }; 209 }; 210}; 211 212&fec1 { 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_enet1>; 215 phy-mode = "rmii"; 216 phy-handle = <ðphy0>; 217 phy-supply = <®_peri_3v3>; 218 status = "okay"; 219}; 220 221&fec2 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_enet2>; 224 phy-mode = "rmii"; 225 phy-handle = <ðphy1>; 226 phy-supply = <®_peri_3v3>; 227 status = "okay"; 228 229 mdio { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 233 ethphy0: ethernet-phy@2 { 234 compatible = "ethernet-phy-id0022.1560"; 235 reg = <2>; 236 micrel,led-mode = <1>; 237 clocks = <&clks IMX6UL_CLK_ENET_REF>; 238 clock-names = "rmii-ref"; 239 240 }; 241 242 ethphy1: ethernet-phy@1 { 243 compatible = "ethernet-phy-id0022.1560"; 244 reg = <1>; 245 micrel,led-mode = <1>; 246 clocks = <&clks IMX6UL_CLK_ENET2_REF>; 247 clock-names = "rmii-ref"; 248 }; 249 }; 250}; 251 252&can1 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_flexcan1>; 255 xceiver-supply = <®_can_3v3>; 256 status = "okay"; 257}; 258 259&can2 { 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_flexcan2>; 262 xceiver-supply = <®_can_3v3>; 263 status = "okay"; 264}; 265 266&gpio_spi { 267 eth0-phy-hog { 268 gpio-hog; 269 gpios = <1 GPIO_ACTIVE_HIGH>; 270 output-high; 271 line-name = "eth0-phy"; 272 }; 273 274 eth1-phy-hog { 275 gpio-hog; 276 gpios = <2 GPIO_ACTIVE_HIGH>; 277 output-high; 278 line-name = "eth1-phy"; 279 }; 280}; 281 282&i2c1 { 283 clock-frequency = <100000>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_i2c1>; 286 status = "okay"; 287 288 magnetometer@e { 289 compatible = "fsl,mag3110"; 290 reg = <0x0e>; 291 vdd-supply = <®_peri_3v3>; 292 vddio-supply = <®_peri_3v3>; 293 }; 294}; 295 296&lcdif { 297 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; 298 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_lcdif_dat 301 &pinctrl_lcdif_ctrl>; 302 status = "okay"; 303 304 port { 305 display_out: endpoint { 306 remote-endpoint = <&panel_in>; 307 }; 308 }; 309}; 310 311&pwm1 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_pwm1>; 314 status = "okay"; 315}; 316 317&qspi { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_qspi>; 320 status = "okay"; 321 322 flash0: flash@0 { 323 #address-cells = <1>; 324 #size-cells = <1>; 325 compatible = "micron,n25q256a", "jedec,spi-nor"; 326 spi-max-frequency = <29000000>; 327 spi-rx-bus-width = <4>; 328 spi-tx-bus-width = <1>; 329 reg = <0>; 330 }; 331}; 332 333&sai2 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_sai2>; 336 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 337 <&clks IMX6UL_CLK_SAI2>; 338 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 339 assigned-clock-rates = <0>, <12288000>; 340 fsl,sai-mclk-direction-output; 341 status = "okay"; 342}; 343 344&snvs_poweroff { 345 status = "okay"; 346}; 347 348&snvs_pwrkey { 349 status = "okay"; 350}; 351 352&tsc { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_tsc>; 355 xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 356 measure-delay-time = <0xffff>; 357 pre-charge-time = <0xfff>; 358 status = "okay"; 359}; 360 361&uart1 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_uart1>; 364 status = "okay"; 365}; 366 367&uart2 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_uart2>; 370 uart-has-rtscts; 371 status = "okay"; 372}; 373 374&usbotg1 { 375 dr_mode = "otg"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_usb_otg1>; 378 status = "okay"; 379}; 380 381&usbotg2 { 382 dr_mode = "host"; 383 disable-over-current; 384 status = "okay"; 385}; 386 387&usbphy1 { 388 fsl,tx-d-cal = <106>; 389}; 390 391&usbphy2 { 392 fsl,tx-d-cal = <106>; 393}; 394 395&usdhc1 { 396 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 397 pinctrl-0 = <&pinctrl_usdhc1>; 398 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 399 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 400 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 401 keep-power-in-suspend; 402 wakeup-source; 403 vmmc-supply = <®_sd1_vmmc>; 404 status = "okay"; 405}; 406 407&usdhc2 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_usdhc2>; 410 no-1-8-v; 411 broken-cd; 412 keep-power-in-suspend; 413 wakeup-source; 414 status = "okay"; 415}; 416 417&wdog1 { 418 pinctrl-names = "default"; 419 pinctrl-0 = <&pinctrl_wdog>; 420 fsl,ext-reset-output; 421}; 422 423&iomuxc { 424 pinctrl-names = "default"; 425 426 pinctrl_camera_clock: cameraclockgrp { 427 fsl,pins = < 428 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 429 >; 430 }; 431 432 pinctrl_csi1: csi1grp { 433 fsl,pins = < 434 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 435 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 436 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 437 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 438 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 439 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 440 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 441 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 442 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 443 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 444 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 445 >; 446 }; 447 448 pinctrl_enet1: enet1grp { 449 fsl,pins = < 450 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 451 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 452 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 453 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 454 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 455 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 456 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 457 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 458 >; 459 }; 460 461 pinctrl_enet2: enet2grp { 462 fsl,pins = < 463 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 464 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 465 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 466 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 467 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 468 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 469 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 470 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 471 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 472 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 473 >; 474 }; 475 476 pinctrl_flexcan1: flexcan1grp { 477 fsl,pins = < 478 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 479 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 480 >; 481 }; 482 483 pinctrl_flexcan2: flexcan2grp { 484 fsl,pins = < 485 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 486 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 487 >; 488 }; 489 490 pinctrl_i2c1: i2c1grp { 491 fsl,pins = < 492 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 493 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 494 >; 495 }; 496 497 pinctrl_i2c2: i2c2grp { 498 fsl,pins = < 499 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 500 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 501 >; 502 }; 503 504 pinctrl_lcdif_dat: lcdifdatgrp { 505 fsl,pins = < 506 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 507 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 508 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 509 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 510 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 511 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 512 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 513 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 514 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 515 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 516 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 517 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 518 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 519 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 520 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 521 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 522 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 523 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 524 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 525 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 526 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 527 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 528 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 529 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 530 >; 531 }; 532 533 pinctrl_lcdif_ctrl: lcdifctrlgrp { 534 fsl,pins = < 535 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 536 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 537 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 538 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 539 /* used for lcd reset */ 540 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 541 >; 542 }; 543 544 pinctrl_qspi: qspigrp { 545 fsl,pins = < 546 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 547 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 548 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 549 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 550 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 551 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 552 >; 553 }; 554 555 pinctrl_sai2: sai2grp { 556 fsl,pins = < 557 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 558 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 559 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 560 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 561 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 562 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 563 >; 564 }; 565 566 pinctrl_peri_3v3: peri3v3grp { 567 fsl,pins = < 568 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 569 >; 570 }; 571 572 pinctrl_pwm1: pwm1grp { 573 fsl,pins = < 574 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 575 >; 576 }; 577 578 pinctrl_sim2: sim2grp { 579 fsl,pins = < 580 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 581 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 582 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 583 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 584 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 585 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 586 >; 587 }; 588 589 pinctrl_spi4: spi4grp { 590 fsl,pins = < 591 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 592 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 593 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 594 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 595 >; 596 }; 597 598 pinctrl_tsc: tscgrp { 599 fsl,pins = < 600 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 601 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 602 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 603 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 604 >; 605 }; 606 607 pinctrl_uart1: uart1grp { 608 fsl,pins = < 609 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 610 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 611 >; 612 }; 613 614 pinctrl_uart2: uart2grp { 615 fsl,pins = < 616 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 617 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 618 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 619 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 620 >; 621 }; 622 623 pinctrl_usb_otg1: usbotg1grp { 624 fsl,pins = < 625 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 626 >; 627 }; 628 629 pinctrl_usdhc1: usdhc1grp { 630 fsl,pins = < 631 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 632 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 633 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 634 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 635 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 636 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 637 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ 638 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ 639 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ 640 >; 641 }; 642 643 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 644 fsl,pins = < 645 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 646 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 647 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 648 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 649 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 650 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 651 652 >; 653 }; 654 655 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 656 fsl,pins = < 657 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 658 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 659 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 660 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 661 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 662 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 663 >; 664 }; 665 666 pinctrl_usdhc2: usdhc2grp { 667 fsl,pins = < 668 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 669 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 670 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 671 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 672 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 673 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 674 >; 675 }; 676 677 pinctrl_wdog: wdoggrp { 678 fsl,pins = < 679 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 680 >; 681 }; 682}; 683