1// SPDX-License-Identifier: ISC
2/*
3 * Device Tree file for Netgear WG302v2 based on IXP422BB
4 * Derived from boardfiles written by Imre Kaloz
5 */
6
7/dts-v1/;
8
9#include "intel-ixp42x.dtsi"
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/leds/common.h>
12
13/ {
14	model = "Netgear WG302 v1";
15	compatible = "netgear,wg302v1", "intel,ixp42x";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	memory@0 {
20		/* 32 MB SDRAM according to boot arguments */
21		device_type = "memory";
22		reg = <0x00000000 0x02000000>;
23	};
24
25	chosen {
26		/* The RedBoot comes up in 9600 baud so let's keep this */
27		bootargs = "console=ttyS0,9600n8";
28		stdout-path = "uart1:9600n8";
29	};
30
31	aliases {
32		/* These are switched around */
33		serial0 = &uart1;
34	};
35
36	leds {
37		compatible = "gpio-leds";
38		test_led: led-test {
39			color = <LED_COLOR_ID_AMBER>;
40			function = "test";
41			gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
42			default-state = "off";
43		};
44		wlan_led: led-wlan {
45			color = <LED_COLOR_ID_GREEN>;
46			function = LED_FUNCTION_WLAN;
47			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
48			default-state = "off";
49			linux,default-trigger = "phy0tx";
50		};
51	};
52
53	gpio_keys {
54		/* RESET is on GPIO13 which can't fire interrupts */
55		compatible = "gpio-keys-polled";
56		poll-interval = <100>;
57
58		button-reset {
59			linux,code = <KEY_RESTART>;
60			label = "reset";
61			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
62		};
63	};
64
65	soc {
66		bus@c4000000 {
67			flash@0,0 {
68				compatible = "intel,ixp4xx-flash", "cfi-flash";
69				bank-width = <2>;
70				/*
71				 * 8 MB of Flash in 64 0x20000 sized blocks
72				 * mapped in at CS0.
73				 */
74				reg = <0 0x00000000 0x800000>;
75
76				/* Configure expansion bus to allow writes */
77				intel,ixp4xx-eb-write-enable = <1>;
78
79				partitions {
80					compatible = "redboot-fis";
81					fis-index-block = <0x3f>;
82				};
83			};
84		};
85
86		pci@c0000000 {
87			status = "okay";
88
89			/*
90			 * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c)
91			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ
92			 * each handling all IRQs.
93			 */
94			#interrupt-cells = <1>;
95			interrupt-map-mask = <0xf800 0 0 7>;
96			interrupt-map =
97			/* IDSEL 1 */
98			<0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */
99			<0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */
100			<0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */
101			<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
102			/* IDSEL 2 */
103			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
104			<0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */
105			<0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */
106			<0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */
107		};
108
109		ethernet@c8009000 {
110			status = "okay";
111			queue-rx = <&qmgr 3>;
112			queue-txready = <&qmgr 20>;
113			phy-mode = "rgmii";
114			phy-handle = <&phy30>;
115
116			mdio {
117				#address-cells = <1>;
118				#size-cells = <0>;
119
120				phy30: ethernet-phy@30 {
121					reg = <30>;
122				};
123			};
124		};
125	};
126};
127