1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Maxim MAX77705 definitions.
4  *
5  * Copyright (C) 2015 Samsung Electronics, Inc.
6  * Copyright (C) 2025 Dzmitry Sankouski <dsankouski@gmail.com>
7  */
8 
9 #ifndef __MAX77705_CHARGER_H
10 #define __MAX77705_CHARGER_H __FILE__
11 
12 /* MAX77705_CHG_REG_CHG_INT */
13 #define MAX77705_BYP_I		BIT(0)
14 #define MAX77705_INP_LIMIT_I	BIT(1)
15 #define MAX77705_BATP_I		BIT(2)
16 #define MAX77705_BAT_I		BIT(3)
17 #define MAX77705_CHG_I		BIT(4)
18 #define MAX77705_WCIN_I		BIT(5)
19 #define MAX77705_CHGIN_I	BIT(6)
20 #define MAX77705_AICL_I		BIT(7)
21 
22 /* MAX77705_CHG_REG_CHG_INT_MASK */
23 #define MAX77705_BYP_IM		BIT(0)
24 #define MAX77705_INP_LIMIT_IM	BIT(1)
25 #define MAX77705_BATP_IM	BIT(2)
26 #define MAX77705_BAT_IM		BIT(3)
27 #define MAX77705_CHG_IM		BIT(4)
28 #define MAX77705_WCIN_IM	BIT(5)
29 #define MAX77705_CHGIN_IM	BIT(6)
30 #define MAX77705_AICL_IM	BIT(7)
31 
32 /* MAX77705_CHG_REG_CHG_INT_OK */
33 #define MAX77705_BYP_OK		BIT(0)
34 #define MAX77705_DISQBAT_OK	BIT(1)
35 #define MAX77705_BATP_OK	BIT(2)
36 #define MAX77705_BAT_OK		BIT(3)
37 #define MAX77705_CHG_OK		BIT(4)
38 #define MAX77705_WCIN_OK	BIT(5)
39 #define MAX77705_CHGIN_OK	BIT(6)
40 #define MAX77705_AICL_OK	BIT(7)
41 
42 /* MAX77705_CHG_REG_DETAILS_00 */
43 #define MAX77705_BATP_DTLS		BIT(0)
44 #define MAX77705_WCIN_DTLS		GENMASK(4, 3)
45 #define MAX77705_WCIN_DTLS_SHIFT	3
46 #define MAX77705_CHGIN_DTLS		GENMASK(6, 5)
47 #define MAX77705_CHGIN_DTLS_SHIFT	5
48 
49 /* MAX77705_CHG_REG_DETAILS_01 */
50 #define MAX77705_CHG_DTLS	GENMASK(3, 0)
51 #define MAX77705_CHG_DTLS_SHIFT	0
52 #define MAX77705_BAT_DTLS	GENMASK(6, 4)
53 #define MAX77705_BAT_DTLS_SHIFT	4
54 
55 /* MAX77705_CHG_REG_DETAILS_02 */
56 #define MAX77705_BYP_DTLS	GENMASK(3, 0)
57 #define MAX77705_BYP_DTLS_SHIFT	0
58 
59 /* MAX77705_CHG_REG_CNFG_00 */
60 #define MAX77705_CHG_SHIFT	0
61 #define MAX77705_UNO_SHIFT	1
62 #define MAX77705_OTG_SHIFT	1
63 #define MAX77705_BUCK_SHIFT	2
64 #define MAX77705_BOOST_SHIFT	3
65 #define MAX77705_WDTEN_SHIFT	4
66 #define MAX77705_MODE_MASK	GENMASK(3, 0)
67 #define MAX77705_CHG_MASK	BIT(MAX77705_CHG_SHIFT)
68 #define MAX77705_UNO_MASK	BIT(MAX77705_UNO_SHIFT)
69 #define MAX77705_OTG_MASK	BIT(MAX77705_OTG_SHIFT)
70 #define MAX77705_BUCK_MASK	BIT(MAX77705_BUCK_SHIFT)
71 #define MAX77705_BOOST_MASK	BIT(MAX77705_BOOST_SHIFT)
72 #define MAX77705_WDTEN_MASK	BIT(MAX77705_WDTEN_SHIFT)
73 #define MAX77705_UNO_CTRL	(MAX77705_UNO_MASK | MAX77705_BOOST_MASK)
74 #define MAX77705_OTG_CTRL	(MAX77705_OTG_MASK | MAX77705_BOOST_MASK)
75 
76 /* MAX77705_CHG_REG_CNFG_01 */
77 #define MAX77705_FCHGTIME_SHIFT		0
78 #define MAX77705_FCHGTIME_MASK		GENMASK(2, 0)
79 #define MAX77705_CHG_RSTRT_SHIFT	4
80 #define MAX77705_CHG_RSTRT_MASK		GENMASK(5, 4)
81 #define MAX77705_FCHGTIME_DISABLE	0
82 #define MAX77705_CHG_RSTRT_DISABLE	0x3
83 
84 #define MAX77705_PQEN_SHIFT		7
85 #define MAX77705_PQEN_MASK		BIT(7)
86 #define MAX77705_CHG_PQEN_DISABLE	0
87 #define MAX77705_CHG_PQEN_ENABLE	1
88 
89 /* MAX77705_CHG_REG_CNFG_02 */
90 #define MAX77705_OTG_ILIM_SHIFT		6
91 #define MAX77705_OTG_ILIM_MASK		GENMASK(7, 6)
92 #define MAX77705_OTG_ILIM_500		0
93 #define MAX77705_OTG_ILIM_900		1
94 #define MAX77705_OTG_ILIM_1200		2
95 #define MAX77705_OTG_ILIM_1500		3
96 #define MAX77705_CHG_CC			GENMASK(5, 0)
97 
98 /* MAX77705_CHG_REG_CNFG_03 */
99 #define MAX77705_TO_ITH_SHIFT		0
100 #define MAX77705_TO_ITH_MASK		GENMASK(2, 0)
101 #define MAX77705_TO_TIME_SHIFT		3
102 #define MAX77705_TO_TIME_MASK		GENMASK(5, 3)
103 #define MAX77705_SYS_TRACK_DIS_SHIFT	7
104 #define MAX77705_SYS_TRACK_DIS_MASK	BIT(7)
105 #define MAX77705_TO_ITH_150MA		0
106 #define MAX77705_TO_TIME_30M		3
107 #define MAX77705_SYS_TRACK_ENABLE	0
108 #define MAX77705_SYS_TRACK_DISABLE	1
109 
110 /* MAX77705_CHG_REG_CNFG_04 */
111 #define MAX77705_CHG_MINVSYS_SHIFT	6
112 #define MAX77705_CHG_MINVSYS_MASK	GENMASK(7, 6)
113 #define MAX77705_CHG_PRM_SHIFT		0
114 #define MAX77705_CHG_PRM_MASK		GENMASK(5, 0)
115 
116 #define MAX77705_CHG_CV_PRM_SHIFT	0
117 #define MAX77705_CHG_CV_PRM_MASK	GENMASK(5, 0)
118 
119 /* MAX77705_CHG_REG_CNFG_05 */
120 #define MAX77705_REG_B2SOVRC_SHIFT	0
121 #define MAX77705_REG_B2SOVRC_MASK	GENMASK(3, 0)
122 #define MAX77705_B2SOVRC_DISABLE	0
123 #define MAX77705_B2SOVRC_4_5A		6
124 #define MAX77705_B2SOVRC_4_8A		8
125 #define MAX77705_B2SOVRC_5_0A		9
126 
127 /* MAX77705_CHG_CNFG_06 */
128 #define MAX77705_WDTCLR_SHIFT		0
129 #define MAX77705_WDTCLR_MASK		GENMASK(1, 0)
130 #define MAX77705_WDTCLR			1
131 #define MAX77705_CHGPROT_MASK		GENMASK(3, 2)
132 #define MAX77705_CHGPROT_UNLOCKED	GENMASK(3, 2)
133 #define MAX77705_SLOWEST_LX_SLOPE	GENMASK(6, 5)
134 
135 /* MAX77705_CHG_REG_CNFG_07 */
136 #define MAX77705_CHG_FMBST		4
137 #define MAX77705_REG_FMBST_SHIFT	2
138 #define MAX77705_REG_FMBST_MASK		BIT(MAX77705_REG_FMBST_SHIFT)
139 #define MAX77705_REG_FGSRC_SHIFT	1
140 #define MAX77705_REG_FGSRC_MASK		BIT(MAX77705_REG_FGSRC_SHIFT)
141 
142 /* MAX77705_CHG_REG_CNFG_08 */
143 #define MAX77705_REG_FSW_SHIFT		0
144 #define MAX77705_REG_FSW_MASK		GENMASK(1, 0)
145 #define MAX77705_CHG_FSW_3MHz		0
146 #define MAX77705_CHG_FSW_2MHz		1
147 #define MAX77705_CHG_FSW_1_5MHz		2
148 
149 /* MAX77705_CHG_REG_CNFG_09 */
150 #define MAX77705_CHG_CHGIN_LIM_MASK		GENMASK(6, 0)
151 #define MAX77705_CHG_EN_MASK			BIT(7)
152 #define MAX77705_CHG_DISABLE			0
153 #define MAX77705_CHARGER_CHG_CHARGING(_reg) \
154 				(((_reg) & MAX77705_CHG_EN_MASK) > 1)
155 
156 
157 /* MAX77705_CHG_REG_CNFG_10 */
158 #define MAX77705_CHG_WCIN_LIM		GENMASK(5, 0)
159 
160 /* MAX77705_CHG_REG_CNFG_11 */
161 #define MAX77705_VBYPSET_SHIFT		0
162 #define MAX77705_VBYPSET_MASK		GENMASK(6, 0)
163 
164 /* MAX77705_CHG_REG_CNFG_12 */
165 #define MAX77705_CHGINSEL_SHIFT		5
166 #define MAX77705_CHGINSEL_MASK		BIT(MAX77705_CHGINSEL_SHIFT)
167 #define MAX77705_WCINSEL_SHIFT		6
168 #define MAX77705_WCINSEL_MASK		BIT(MAX77705_WCINSEL_SHIFT)
169 #define MAX77705_VCHGIN_REG_MASK	GENMASK(4, 3)
170 #define MAX77705_WCIN_REG_MASK		GENMASK(2, 1)
171 #define MAX77705_REG_DISKIP_SHIFT	0
172 #define MAX77705_REG_DISKIP_MASK	BIT(MAX77705_REG_DISKIP_SHIFT)
173 /* REG=4.5V, UVLO=4.7V */
174 #define MAX77705_VCHGIN_4_5		0
175 /* REG=4.5V, UVLO=4.7V */
176 #define MAX77705_WCIN_4_5		0
177 #define MAX77705_DISABLE_SKIP		1
178 #define MAX77705_AUTO_SKIP		0
179 
180 /* uA */
181 #define MAX77705_CURRENT_CHGIN_STEP	25000
182 #define MAX77705_CURRENT_CHG_STEP	50000
183 #define MAX77705_CURRENT_CHGIN_MIN	100000
184 #define MAX77705_CURRENT_CHGIN_MAX	3200000
185 
186 struct max77705_charger_data {
187 	struct device			*dev;
188 	struct regmap		*regmap;
189 	struct power_supply_battery_info *bat_info;
190 	struct workqueue_struct *wqueue;
191 	struct work_struct	chgin_work;
192 	struct power_supply	*psy_chg;
193 };
194 
195 #endif /* __MAX77705_CHARGER_H */
196