1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
4 *
5 * Authors:
6 * Peter Pan <peterpandong@micron.com>
7 */
8 #ifndef __LINUX_MTD_SPINAND_H
9 #define __LINUX_MTD_SPINAND_H
10
11 #include <linux/mutex.h>
12 #include <linux/bitops.h>
13 #include <linux/device.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
18
19 /**
20 * Standard SPI NAND flash operations
21 */
22
23 #define SPINAND_RESET_OP \
24 SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1), \
25 SPI_MEM_OP_NO_ADDR, \
26 SPI_MEM_OP_NO_DUMMY, \
27 SPI_MEM_OP_NO_DATA)
28
29 #define SPINAND_WR_EN_DIS_OP(enable) \
30 SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1), \
31 SPI_MEM_OP_NO_ADDR, \
32 SPI_MEM_OP_NO_DUMMY, \
33 SPI_MEM_OP_NO_DATA)
34
35 #define SPINAND_READID_OP(naddr, ndummy, buf, len) \
36 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
37 SPI_MEM_OP_ADDR(naddr, 0, 1), \
38 SPI_MEM_OP_DUMMY(ndummy, 1), \
39 SPI_MEM_OP_DATA_IN(len, buf, 1))
40
41 #define SPINAND_SET_FEATURE_OP(reg, valptr) \
42 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
43 SPI_MEM_OP_ADDR(1, reg, 1), \
44 SPI_MEM_OP_NO_DUMMY, \
45 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
46
47 #define SPINAND_GET_FEATURE_OP(reg, valptr) \
48 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1), \
49 SPI_MEM_OP_ADDR(1, reg, 1), \
50 SPI_MEM_OP_NO_DUMMY, \
51 SPI_MEM_OP_DATA_IN(1, valptr, 1))
52
53 #define SPINAND_BLK_ERASE_OP(addr) \
54 SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1), \
55 SPI_MEM_OP_ADDR(3, addr, 1), \
56 SPI_MEM_OP_NO_DUMMY, \
57 SPI_MEM_OP_NO_DATA)
58
59 #define SPINAND_PAGE_READ_OP(addr) \
60 SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1), \
61 SPI_MEM_OP_ADDR(3, addr, 1), \
62 SPI_MEM_OP_NO_DUMMY, \
63 SPI_MEM_OP_NO_DATA)
64
65 #define SPINAND_PAGE_READ_FROM_CACHE_OP(addr, ndummy, buf, len, ...) \
66 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
67 SPI_MEM_OP_ADDR(2, addr, 1), \
68 SPI_MEM_OP_DUMMY(ndummy, 1), \
69 SPI_MEM_OP_DATA_IN(len, buf, 1), \
70 SPI_MEM_OP_MAX_FREQ(__VA_ARGS__ + 0))
71
72 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_OP(addr, ndummy, buf, len) \
73 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
74 SPI_MEM_OP_ADDR(2, addr, 1), \
75 SPI_MEM_OP_DUMMY(ndummy, 1), \
76 SPI_MEM_OP_DATA_IN(len, buf, 1))
77
78 #define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(addr, ndummy, buf, len) \
79 SPI_MEM_OP(SPI_MEM_OP_CMD(0x03, 1), \
80 SPI_MEM_OP_ADDR(3, addr, 1), \
81 SPI_MEM_OP_DUMMY(ndummy, 1), \
82 SPI_MEM_OP_DATA_IN(len, buf, 1))
83
84 #define SPINAND_PAGE_READ_FROM_CACHE_FAST_OP_3A(addr, ndummy, buf, len) \
85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
86 SPI_MEM_OP_ADDR(3, addr, 1), \
87 SPI_MEM_OP_DUMMY(ndummy, 1), \
88 SPI_MEM_OP_DATA_IN(len, buf, 1))
89
90 #define SPINAND_PAGE_READ_FROM_CACHE_DTR_OP(addr, ndummy, buf, len, freq) \
91 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
92 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
93 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
94 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
95 SPI_MEM_OP_MAX_FREQ(freq))
96
97 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
98 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
99 SPI_MEM_OP_ADDR(2, addr, 1), \
100 SPI_MEM_OP_DUMMY(ndummy, 1), \
101 SPI_MEM_OP_DATA_IN(len, buf, 2))
102
103 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \
104 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
105 SPI_MEM_OP_ADDR(3, addr, 1), \
106 SPI_MEM_OP_DUMMY(ndummy, 1), \
107 SPI_MEM_OP_DATA_IN(len, buf, 2))
108
109 #define SPINAND_PAGE_READ_FROM_CACHE_X2_DTR_OP(addr, ndummy, buf, len, freq) \
110 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3d, 1), \
111 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
112 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
113 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
114 SPI_MEM_OP_MAX_FREQ(freq))
115
116 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
117 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
118 SPI_MEM_OP_ADDR(2, addr, 1), \
119 SPI_MEM_OP_DUMMY(ndummy, 1), \
120 SPI_MEM_OP_DATA_IN(len, buf, 4))
121
122 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \
123 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
124 SPI_MEM_OP_ADDR(3, addr, 1), \
125 SPI_MEM_OP_DUMMY(ndummy, 1), \
126 SPI_MEM_OP_DATA_IN(len, buf, 4))
127
128 #define SPINAND_PAGE_READ_FROM_CACHE_X4_DTR_OP(addr, ndummy, buf, len, freq) \
129 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
130 SPI_MEM_DTR_OP_ADDR(2, addr, 1), \
131 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
132 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
133 SPI_MEM_OP_MAX_FREQ(freq))
134
135 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
136 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
137 SPI_MEM_OP_ADDR(2, addr, 2), \
138 SPI_MEM_OP_DUMMY(ndummy, 2), \
139 SPI_MEM_OP_DATA_IN(len, buf, 2))
140
141 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP_3A(addr, ndummy, buf, len) \
142 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
143 SPI_MEM_OP_ADDR(3, addr, 2), \
144 SPI_MEM_OP_DUMMY(ndummy, 2), \
145 SPI_MEM_OP_DATA_IN(len, buf, 2))
146
147 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_DTR_OP(addr, ndummy, buf, len, freq) \
148 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
149 SPI_MEM_DTR_OP_ADDR(2, addr, 2), \
150 SPI_MEM_DTR_OP_DUMMY(ndummy, 2), \
151 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
152 SPI_MEM_OP_MAX_FREQ(freq))
153
154 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len) \
155 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
156 SPI_MEM_OP_ADDR(2, addr, 4), \
157 SPI_MEM_OP_DUMMY(ndummy, 4), \
158 SPI_MEM_OP_DATA_IN(len, buf, 4))
159
160 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP_3A(addr, ndummy, buf, len) \
161 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
162 SPI_MEM_OP_ADDR(3, addr, 4), \
163 SPI_MEM_OP_DUMMY(ndummy, 4), \
164 SPI_MEM_OP_DATA_IN(len, buf, 4))
165
166 #define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_DTR_OP(addr, ndummy, buf, len, freq) \
167 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
168 SPI_MEM_DTR_OP_ADDR(2, addr, 4), \
169 SPI_MEM_DTR_OP_DUMMY(ndummy, 4), \
170 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
171 SPI_MEM_OP_MAX_FREQ(freq))
172
173 #define SPINAND_PROG_EXEC_OP(addr) \
174 SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \
175 SPI_MEM_OP_ADDR(3, addr, 1), \
176 SPI_MEM_OP_NO_DUMMY, \
177 SPI_MEM_OP_NO_DATA)
178
179 #define SPINAND_PROG_LOAD(reset, addr, buf, len) \
180 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1), \
181 SPI_MEM_OP_ADDR(2, addr, 1), \
182 SPI_MEM_OP_NO_DUMMY, \
183 SPI_MEM_OP_DATA_OUT(len, buf, 1))
184
185 #define SPINAND_PROG_LOAD_X4(reset, addr, buf, len) \
186 SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1), \
187 SPI_MEM_OP_ADDR(2, addr, 1), \
188 SPI_MEM_OP_NO_DUMMY, \
189 SPI_MEM_OP_DATA_OUT(len, buf, 4))
190
191 /**
192 * Standard SPI NAND flash commands
193 */
194 #define SPINAND_CMD_PROG_LOAD_X4 0x32
195 #define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4 0x34
196
197 /* feature register */
198 #define REG_BLOCK_LOCK 0xa0
199 #define BL_ALL_UNLOCKED 0x00
200
201 /* configuration register */
202 #define REG_CFG 0xb0
203 #define CFG_OTP_ENABLE BIT(6)
204 #define CFG_ECC_ENABLE BIT(4)
205 #define CFG_QUAD_ENABLE BIT(0)
206
207 /* status register */
208 #define REG_STATUS 0xc0
209 #define STATUS_BUSY BIT(0)
210 #define STATUS_ERASE_FAILED BIT(2)
211 #define STATUS_PROG_FAILED BIT(3)
212 #define STATUS_ECC_MASK GENMASK(5, 4)
213 #define STATUS_ECC_NO_BITFLIPS (0 << 4)
214 #define STATUS_ECC_HAS_BITFLIPS (1 << 4)
215 #define STATUS_ECC_UNCOR_ERROR (2 << 4)
216
217 struct spinand_op;
218 struct spinand_device;
219
220 #define SPINAND_MAX_ID_LEN 5
221 /*
222 * For erase, write and read operation, we got the following timings :
223 * tBERS (erase) 1ms to 4ms
224 * tPROG 300us to 400us
225 * tREAD 25us to 100us
226 * In order to minimize latency, the min value is divided by 4 for the
227 * initial delay, and dividing by 20 for the poll delay.
228 * For reset, 5us/10us/500us if the device is respectively
229 * reading/programming/erasing when the RESET occurs. Since we always
230 * issue a RESET when the device is IDLE, 5us is selected for both initial
231 * and poll delay.
232 */
233 #define SPINAND_READ_INITIAL_DELAY_US 6
234 #define SPINAND_READ_POLL_DELAY_US 5
235 #define SPINAND_RESET_INITIAL_DELAY_US 5
236 #define SPINAND_RESET_POLL_DELAY_US 5
237 #define SPINAND_WRITE_INITIAL_DELAY_US 75
238 #define SPINAND_WRITE_POLL_DELAY_US 15
239 #define SPINAND_ERASE_INITIAL_DELAY_US 250
240 #define SPINAND_ERASE_POLL_DELAY_US 50
241
242 #define SPINAND_WAITRDY_TIMEOUT_MS 400
243
244 /**
245 * struct spinand_id - SPI NAND id structure
246 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
247 * be extended if required
248 * @len: ID length
249 */
250 struct spinand_id {
251 u8 data[SPINAND_MAX_ID_LEN];
252 int len;
253 };
254
255 enum spinand_readid_method {
256 SPINAND_READID_METHOD_OPCODE,
257 SPINAND_READID_METHOD_OPCODE_ADDR,
258 SPINAND_READID_METHOD_OPCODE_DUMMY,
259 };
260
261 /**
262 * struct spinand_devid - SPI NAND device id structure
263 * @id: device id of current chip
264 * @len: number of bytes in device id
265 * @method: method to read chip id
266 * There are 3 possible variants:
267 * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
268 * after read_id opcode.
269 * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
270 * read_id opcode + 1-byte address.
271 * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
272 * read_id opcode + 1 dummy byte.
273 */
274 struct spinand_devid {
275 const u8 *id;
276 const u8 len;
277 const enum spinand_readid_method method;
278 };
279
280 /**
281 * struct manufacurer_ops - SPI NAND manufacturer specific operations
282 * @init: initialize a SPI NAND device
283 * @cleanup: cleanup a SPI NAND device
284 *
285 * Each SPI NAND manufacturer driver should implement this interface so that
286 * NAND chips coming from this vendor can be initialized properly.
287 */
288 struct spinand_manufacturer_ops {
289 int (*init)(struct spinand_device *spinand);
290 void (*cleanup)(struct spinand_device *spinand);
291 };
292
293 /**
294 * struct spinand_manufacturer - SPI NAND manufacturer instance
295 * @id: manufacturer ID
296 * @name: manufacturer name
297 * @devid_len: number of bytes in device ID
298 * @chips: supported SPI NANDs under current manufacturer
299 * @nchips: number of SPI NANDs available in chips array
300 * @ops: manufacturer operations
301 */
302 struct spinand_manufacturer {
303 u8 id;
304 char *name;
305 const struct spinand_info *chips;
306 const size_t nchips;
307 const struct spinand_manufacturer_ops *ops;
308 };
309
310 /* SPI NAND manufacturers */
311 extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;
312 extern const struct spinand_manufacturer ato_spinand_manufacturer;
313 extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
314 extern const struct spinand_manufacturer foresee_spinand_manufacturer;
315 extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
316 extern const struct spinand_manufacturer macronix_spinand_manufacturer;
317 extern const struct spinand_manufacturer micron_spinand_manufacturer;
318 extern const struct spinand_manufacturer paragon_spinand_manufacturer;
319 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
320 extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
321 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
322 extern const struct spinand_manufacturer xtx_spinand_manufacturer;
323
324 /**
325 * struct spinand_op_variants - SPI NAND operation variants
326 * @ops: the list of variants for a given operation
327 * @nops: the number of variants
328 *
329 * Some operations like read-from-cache/write-to-cache have several variants
330 * depending on the number of IO lines you use to transfer data or address
331 * cycles. This structure is a way to describe the different variants supported
332 * by a chip and let the core pick the best one based on the SPI mem controller
333 * capabilities.
334 */
335 struct spinand_op_variants {
336 const struct spi_mem_op *ops;
337 unsigned int nops;
338 };
339
340 #define SPINAND_OP_VARIANTS(name, ...) \
341 const struct spinand_op_variants name = { \
342 .ops = (struct spi_mem_op[]) { __VA_ARGS__ }, \
343 .nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) / \
344 sizeof(struct spi_mem_op), \
345 }
346
347 /**
348 * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
349 * chip
350 * @get_status: get the ECC status. Should return a positive number encoding
351 * the number of corrected bitflips if correction was possible or
352 * -EBADMSG if there are uncorrectable errors. I can also return
353 * other negative error codes if the error is not caused by
354 * uncorrectable bitflips
355 * @ooblayout: the OOB layout used by the on-die ECC implementation
356 */
357 struct spinand_ecc_info {
358 int (*get_status)(struct spinand_device *spinand, u8 status);
359 const struct mtd_ooblayout_ops *ooblayout;
360 };
361
362 #define SPINAND_HAS_QE_BIT BIT(0)
363 #define SPINAND_HAS_CR_FEAT_BIT BIT(1)
364 #define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
365 #define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
366 #define SPINAND_NO_RAW_ACCESS BIT(4)
367
368 /**
369 * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
370 * @status: status of the last wait operation that will be used in case
371 * ->get_status() is not populated by the spinand device.
372 */
373 struct spinand_ondie_ecc_conf {
374 u8 status;
375 };
376
377 /**
378 * struct spinand_otp_layout - structure to describe the SPI NAND OTP area
379 * @npages: number of pages in the OTP
380 * @start_page: start page of the user/factory OTP area.
381 */
382 struct spinand_otp_layout {
383 unsigned int npages;
384 unsigned int start_page;
385 };
386
387 /**
388 * struct spinand_fact_otp_ops - SPI NAND OTP methods for factory area
389 * @info: get the OTP area information
390 * @read: read from the SPI NAND OTP area
391 */
392 struct spinand_fact_otp_ops {
393 int (*info)(struct spinand_device *spinand, size_t len,
394 struct otp_info *buf, size_t *retlen);
395 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
396 size_t *retlen, u8 *buf);
397 };
398
399 /**
400 * struct spinand_user_otp_ops - SPI NAND OTP methods for user area
401 * @info: get the OTP area information
402 * @lock: lock an OTP region
403 * @erase: erase an OTP region
404 * @read: read from the SPI NAND OTP area
405 * @write: write to the SPI NAND OTP area
406 */
407 struct spinand_user_otp_ops {
408 int (*info)(struct spinand_device *spinand, size_t len,
409 struct otp_info *buf, size_t *retlen);
410 int (*lock)(struct spinand_device *spinand, loff_t from, size_t len);
411 int (*erase)(struct spinand_device *spinand, loff_t from, size_t len);
412 int (*read)(struct spinand_device *spinand, loff_t from, size_t len,
413 size_t *retlen, u8 *buf);
414 int (*write)(struct spinand_device *spinand, loff_t from, size_t len,
415 size_t *retlen, const u8 *buf);
416 };
417
418 /**
419 * struct spinand_fact_otp - SPI NAND OTP grouping structure for factory area
420 * @layout: OTP region layout
421 * @ops: OTP access ops
422 */
423 struct spinand_fact_otp {
424 const struct spinand_otp_layout layout;
425 const struct spinand_fact_otp_ops *ops;
426 };
427
428 /**
429 * struct spinand_user_otp - SPI NAND OTP grouping structure for user area
430 * @layout: OTP region layout
431 * @ops: OTP access ops
432 */
433 struct spinand_user_otp {
434 const struct spinand_otp_layout layout;
435 const struct spinand_user_otp_ops *ops;
436 };
437
438 /**
439 * struct spinand_info - Structure used to describe SPI NAND chips
440 * @model: model name
441 * @devid: device ID
442 * @flags: OR-ing of the SPINAND_XXX flags
443 * @memorg: memory organization
444 * @eccreq: ECC requirements
445 * @eccinfo: on-die ECC info
446 * @op_variants: operations variants
447 * @op_variants.read_cache: variants of the read-cache operation
448 * @op_variants.write_cache: variants of the write-cache operation
449 * @op_variants.update_cache: variants of the update-cache operation
450 * @select_target: function used to select a target/die. Required only for
451 * multi-die chips
452 * @set_cont_read: enable/disable continuous cached reads
453 * @fact_otp: SPI NAND factory OTP info.
454 * @user_otp: SPI NAND user OTP info.
455 * @read_retries: the number of read retry modes supported
456 * @set_read_retry: enable/disable read retry for data recovery
457 *
458 * Each SPI NAND manufacturer driver should have a spinand_info table
459 * describing all the chips supported by the driver.
460 */
461 struct spinand_info {
462 const char *model;
463 struct spinand_devid devid;
464 u32 flags;
465 struct nand_memory_organization memorg;
466 struct nand_ecc_props eccreq;
467 struct spinand_ecc_info eccinfo;
468 struct {
469 const struct spinand_op_variants *read_cache;
470 const struct spinand_op_variants *write_cache;
471 const struct spinand_op_variants *update_cache;
472 } op_variants;
473 int (*select_target)(struct spinand_device *spinand,
474 unsigned int target);
475 int (*set_cont_read)(struct spinand_device *spinand,
476 bool enable);
477 struct spinand_fact_otp fact_otp;
478 struct spinand_user_otp user_otp;
479 unsigned int read_retries;
480 int (*set_read_retry)(struct spinand_device *spinand,
481 unsigned int read_retry);
482 };
483
484 #define SPINAND_ID(__method, ...) \
485 { \
486 .id = (const u8[]){ __VA_ARGS__ }, \
487 .len = sizeof((u8[]){ __VA_ARGS__ }), \
488 .method = __method, \
489 }
490
491 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
492 { \
493 .read_cache = __read, \
494 .write_cache = __write, \
495 .update_cache = __update, \
496 }
497
498 #define SPINAND_ECCINFO(__ooblayout, __get_status) \
499 .eccinfo = { \
500 .ooblayout = __ooblayout, \
501 .get_status = __get_status, \
502 }
503
504 #define SPINAND_SELECT_TARGET(__func) \
505 .select_target = __func
506
507 #define SPINAND_CONT_READ(__set_cont_read) \
508 .set_cont_read = __set_cont_read
509
510 #define SPINAND_FACT_OTP_INFO(__npages, __start_page, __ops) \
511 .fact_otp = { \
512 .layout = { \
513 .npages = __npages, \
514 .start_page = __start_page, \
515 }, \
516 .ops = __ops, \
517 }
518
519 #define SPINAND_USER_OTP_INFO(__npages, __start_page, __ops) \
520 .user_otp = { \
521 .layout = { \
522 .npages = __npages, \
523 .start_page = __start_page, \
524 }, \
525 .ops = __ops, \
526 }
527
528 #define SPINAND_READ_RETRY(__read_retries, __set_read_retry) \
529 .read_retries = __read_retries, \
530 .set_read_retry = __set_read_retry
531
532 #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \
533 __flags, ...) \
534 { \
535 .model = __model, \
536 .devid = __id, \
537 .memorg = __memorg, \
538 .eccreq = __eccreq, \
539 .op_variants = __op_variants, \
540 .flags = __flags, \
541 __VA_ARGS__ \
542 }
543
544 struct spinand_dirmap {
545 struct spi_mem_dirmap_desc *wdesc;
546 struct spi_mem_dirmap_desc *rdesc;
547 struct spi_mem_dirmap_desc *wdesc_ecc;
548 struct spi_mem_dirmap_desc *rdesc_ecc;
549 };
550
551 /**
552 * struct spinand_device - SPI NAND device instance
553 * @base: NAND device instance
554 * @spimem: pointer to the SPI mem object
555 * @lock: lock used to serialize accesses to the NAND
556 * @id: NAND ID as returned by READ_ID
557 * @flags: NAND flags
558 * @op_templates: various SPI mem op templates
559 * @op_templates.read_cache: read cache op template
560 * @op_templates.write_cache: write cache op template
561 * @op_templates.update_cache: update cache op template
562 * @select_target: select a specific target/die. Usually called before sending
563 * a command addressing a page or an eraseblock embedded in
564 * this die. Only required if your chip exposes several dies
565 * @cur_target: currently selected target/die
566 * @eccinfo: on-die ECC information
567 * @cfg_cache: config register cache. One entry per die
568 * @databuf: bounce buffer for data
569 * @oobbuf: bounce buffer for OOB data
570 * @scratchbuf: buffer used for everything but page accesses. This is needed
571 * because the spi-mem interface explicitly requests that buffers
572 * passed in spi_mem_op be DMA-able, so we can't based the bufs on
573 * the stack
574 * @manufacturer: SPI NAND manufacturer information
575 * @cont_read_possible: Field filled by the core once the whole system
576 * configuration is known to tell whether continuous reads are
577 * suitable to use or not in general with this chip/configuration.
578 * A per-transfer check must of course be done to ensure it is
579 * actually relevant to enable this feature.
580 * @set_cont_read: Enable/disable the continuous read feature
581 * @priv: manufacturer private data
582 * @fact_otp: SPI NAND factory OTP info.
583 * @user_otp: SPI NAND user OTP info.
584 * @read_retries: the number of read retry modes supported
585 * @set_read_retry: Enable/disable the read retry feature
586 */
587 struct spinand_device {
588 struct nand_device base;
589 struct spi_mem *spimem;
590 struct mutex lock;
591 struct spinand_id id;
592 u32 flags;
593
594 struct {
595 const struct spi_mem_op *read_cache;
596 const struct spi_mem_op *write_cache;
597 const struct spi_mem_op *update_cache;
598 } op_templates;
599
600 struct spinand_dirmap *dirmaps;
601
602 int (*select_target)(struct spinand_device *spinand,
603 unsigned int target);
604 unsigned int cur_target;
605
606 struct spinand_ecc_info eccinfo;
607
608 u8 *cfg_cache;
609 u8 *databuf;
610 u8 *oobbuf;
611 u8 *scratchbuf;
612 const struct spinand_manufacturer *manufacturer;
613 void *priv;
614
615 bool cont_read_possible;
616 int (*set_cont_read)(struct spinand_device *spinand,
617 bool enable);
618
619 const struct spinand_fact_otp *fact_otp;
620 const struct spinand_user_otp *user_otp;
621
622 unsigned int read_retries;
623 int (*set_read_retry)(struct spinand_device *spinand,
624 unsigned int retry_mode);
625 };
626
627 /**
628 * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
629 * @mtd: MTD instance
630 *
631 * Return: the SPI NAND device attached to @mtd.
632 */
mtd_to_spinand(struct mtd_info * mtd)633 static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
634 {
635 return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
636 }
637
638 /**
639 * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
640 * @spinand: SPI NAND device
641 *
642 * Return: the MTD device embedded in @spinand.
643 */
spinand_to_mtd(struct spinand_device * spinand)644 static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
645 {
646 return nanddev_to_mtd(&spinand->base);
647 }
648
649 /**
650 * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
651 * @nand: NAND object
652 *
653 * Return: the SPI NAND device embedding @nand.
654 */
nand_to_spinand(struct nand_device * nand)655 static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
656 {
657 return container_of(nand, struct spinand_device, base);
658 }
659
660 /**
661 * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
662 * @spinand: SPI NAND device
663 *
664 * Return: the NAND device embedded in @spinand.
665 */
666 static inline struct nand_device *
spinand_to_nand(struct spinand_device * spinand)667 spinand_to_nand(struct spinand_device *spinand)
668 {
669 return &spinand->base;
670 }
671
672 /**
673 * spinand_set_of_node - Attach a DT node to a SPI NAND device
674 * @spinand: SPI NAND device
675 * @np: DT node
676 *
677 * Attach a DT node to a SPI NAND device.
678 */
spinand_set_of_node(struct spinand_device * spinand,struct device_node * np)679 static inline void spinand_set_of_node(struct spinand_device *spinand,
680 struct device_node *np)
681 {
682 nanddev_set_of_node(&spinand->base, np);
683 }
684
685 int spinand_match_and_init(struct spinand_device *spinand,
686 const struct spinand_info *table,
687 unsigned int table_size,
688 enum spinand_readid_method rdid_method);
689
690 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
691 int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val);
692 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
693
694 int spinand_wait(struct spinand_device *spinand, unsigned long initial_delay_us,
695 unsigned long poll_delay_us, u8 *s);
696
697 int spinand_read_page(struct spinand_device *spinand,
698 const struct nand_page_io_req *req);
699
700 int spinand_write_page(struct spinand_device *spinand,
701 const struct nand_page_io_req *req);
702
703 size_t spinand_otp_page_size(struct spinand_device *spinand);
704 size_t spinand_fact_otp_size(struct spinand_device *spinand);
705 size_t spinand_user_otp_size(struct spinand_device *spinand);
706
707 int spinand_fact_otp_read(struct spinand_device *spinand, loff_t ofs,
708 size_t len, size_t *retlen, u8 *buf);
709 int spinand_user_otp_read(struct spinand_device *spinand, loff_t ofs,
710 size_t len, size_t *retlen, u8 *buf);
711 int spinand_user_otp_write(struct spinand_device *spinand, loff_t ofs,
712 size_t len, size_t *retlen, const u8 *buf);
713
714 int spinand_set_mtd_otp_ops(struct spinand_device *spinand);
715
716 #endif /* __LINUX_MTD_SPINAND_H */
717